Universit`
a di Pisa
DIPARTIMENTO DI INGEGNERIA DELL’INFORMAZIONE Laurea Magistrale in Ingegneria Informatica
Viv2XDL: a bridge between Vivado
and
XDL based software
Master’s Thesis
Supervisor:
Prof. Cinzia Bernardeschi Prof. Andrea Domenici
Candidate: Luca Santangelo
Contents
Introduction 10
1 FPGA 12
1.1 Introduction . . . 12
1.2 High Level Structure . . . 14
1.3 Tiled Structure . . . 16
1.4 Tiles Details . . . 18
1.4.1 INT . . . 18
1.4.2 CLB . . . 20
Look-UP Table (LUT) . . . 21
Storage Elements . . . 22 1.4.3 “IOB” . . . 22 2 XDL 24 2.1 Report . . . 24 2.2 Design . . . 27 3 Vivado 28 3.1 TCL . . . 30 3.1.1 Vivado Objects[8] . . . 31 4 Viv2XDL 34 4.1 Report . . . 34 4.1.1 Analysis of XDL . . . 34 Header . . . 35 Tiles . . . 35
Primitive Definitions . . . 39
Summary . . . 43
4.1.2 Analysis of TCL commands . . . 44
Objects . . . 44
Properties . . . 45
4.1.3 Using TCL to get XDL information . . . 50
Tiles . . . 50 4.2 Design . . . 53 4.2.1 Analysis of XDL[5] . . . 54 4.2.2 Analysis of TCL commands . . . 57 Objects . . . 57 Properties . . . 58
4.2.3 Using TCL to get XDL information . . . 61
LUT . . . 63
LATCH and FLIP FLOP . . . 64
Signal Net . . . 66
Special Net . . . 67
4.3 Software Design and Implementation . . . 68
4.3.1 Report . . . 69 4.3.2 Design . . . 70 4.4 Future Work . . . 73 5 Examples 75 5.1 Report . . . 75 5.2 Design . . . 77 5.2.1 Parity Checker . . . 78 Conclusions 85 A Slice HW 86 A.1 SLICEL . . . 86 A.2 SLICEM . . . 87 B XDL Grammar 88 B.1 Report . . . 88
List of Figures
1.1 Example of Mapper work. . . 13
1.2 FPGA Structure. . . 14
1.3 FPGA High Level Structure[2]. . . 15
1.4 Example of routing in FPGAs. . . 16
1.5 Tiled representation of XC7A8 (Artix7). . . 17
1.6 Zoomed view of XC7A8 (Artix7). . . 18
1.7 Switch matrix of an INT tile. . . 19
1.8 CLB structure. . . 20
1.9 CLB Carry Chain[3]. . . 21
1.10 SLICEM “B” LUT in FPGA Editor. . . 22
1.11 SLICE Storage Elements. . . 23
1.12 IOB Primitive Site internal structure. . . 23
2.1 Using XDL to change synthesis flow. . . 25
2.2 XDL Report Hierarchy. . . 26
3.1 Vivado. . . 28
3.2 Vivado and FPGAs encrypted information. . . 29
4.1 Route-through example. . . 38
4.2 Objects relationships in Vivado (Report). . . 46
4.3 Objects relationships in Vivado (Design). . . 59
4.4 Viv2XDL using API infrastructure. . . 68
4.5 Viv2XDL using direct access infrastructure. . . 69
4.6 Strategy Pattern in UML . . . 70
5.1 Parity Checker structure. . . 78 5.2 Vivado implementation of Parity Checker. . . 82 5.3 FPGAEditor design of VIvado2XDL conversion of Parity
Checker. . . 83 5.4 Site zoom of Vivado implementation of Parity Checker. . . . 83 5.5 FPGAEditor site zoom of VIvado2XDL conversion of Parity
Checker. . . 84 A.1 SLICEL structure. . . 86 A.2 SLICEM structure. . . 87
Listings
3.1 Example of getting property in Vivado . . . 31
3.2 Example of the use of “-of objects” . . . 32
3.3 Example of filtering in Vivado . . . 32
3.4 Second example of filtering in Vivado . . . 32
3.5 Third example of filtering in Vivado . . . 33
4.1 XDL Report Header . . . 35
4.2 Example of tile in XDL Report . . . 36
4.3 Example of tile in XDL Report . . . 36
4.4 Example of pinwire in XDL Report . . . 36
4.5 Example of wire and connection in XDL Report . . . 36
4.6 Example of PIP in XDL Report . . . 37
4.7 Example of routethrough . . . 38
4.8 XDL report tiles[4] . . . 38
4.9 XDL tile summary . . . 39
4.10 Example of primitive definition in XDL Report . . . 39
4.11 Example of pin definition in XDL Report . . . 39
4.12 Example of element definition in XDL Report . . . 40
4.13 Example of internal pin definition in XDL Report . . . 40
4.14 Example of configuration options in XDL Report . . . 41
4.15 Example of configuration element . . . 41
4.16 Example of pin element . . . 42
4.17 Example of route-through element . . . 42
4.18 Example of primitive definition. . . 42
4.19 Example of report summary. . . 43
4.21 Spartan-6 bus macro implementation in XDL . . . 55
4.22 XDL Design Port definition . . . 55
4.23 Syntax of design instance definitions . . . 56
4.24 Command to obtain all Signal Net . . . 66
4.25 Example of accessing to special nets . . . 67
4.26 Example of “Command Substitution” . . . 70
4.27 Example of Plug-in . . . 72
5.1 Example of Fake XDL report . . . 76
5.2 VHDL of Parity Checker project (“Container.vhd”) . . . 78
5.3 VHDL of Parity Checker project (“ParityChecker.vhd”) . . . 79
5.4 VHDL of Parity Checker project (“shifterigister.vhd”) . . . . 80
5.5 Viv2XDL log output for Parity Checker. . . 80
5.6 ISE XDL log output for Parity Checker . . . 81
B.1 EBNF of XDL report file (for COCO/R) . . . 88
List of Tables
4.1 Properties of Tile objects (Report) . . . 45
4.2 Properties of Site objects (Report) . . . 46
4.3 Properties of Site pin objects (Report) . . . 47
4.4 Properties of PIP objects (Report) . . . 48
4.5 Properties of Wire objects (Report) . . . 49
4.6 Properties of Node objects (Report) . . . 50
4.7 Properties of Package Pin objects (Report) . . . 50
4.8 PIP properties to XDL direction arrow . . . 52
4.9 Properties of Port objects (Design) . . . 58
4.10 Properties of Cell objects (Design) . . . 59
4.11 Properties of LUT (Cell) objects (Design) . . . 60
4.12 Properties of LATCH/FLIP FLOP (Cell) objects (Design) . . 60
4.13 Properties of Net objects (Design) . . . 61
4.14 Properties of Pin objects (Design) . . . 61
Abstract
Xilinx is one of the best known FPGA vendors and its FPGAs are used in research, industrial and military environments. For the ISE design suite Xilinx has provided a powerful tool to extract information of the FPGA structure (up to 7th series devices) and to read and modify designs through the Xilinx Design Language (XDL). For the new Xilinx IDE Vivado however, XDL became unsupported and the tool was removed from the IDE. Instead, Vivado offers a TCL based API to get access to the information of the internal FPGA architecture as well as to modify designs. In this work a TCL script has been developed to build a bridge from Vivado to XDL based software, like RapidSmith and DHHarMa, through the creation of a compatible XDL files.
Introduction
FPGAs are commonly used in research, industrial and military applications because of theirs versatility. The possibility of changing configuration and thus behaviour is one of the reasons why FPGAs are often used, especially for rapid prototyping because is possible to test and debug applications faster and at low cost.
In the FPGAs market, Xilinx is one of the leaders and its FPGAs and tools are among the most used. The first tool that Xilinx provided to users is the ISE Design Suite and it is the only one that supports Xilinx FPGAs up to the 6th Series. Together with the 7th Series, Xilinx launched a new tool called Vivado, which will replace ISE for the next generations.
In addition to software provided by Xilinx, there are many third-party tools that interact with the ones in the ISE Suite. This interaction was made easier mainly because Xilinx provided a tool that can be used to get a description of FPGA structure and synthesised design in a human readable form based on a proprietary description language called Xilinx Design Language (XDL). With the replacement of ISE and therefore the removal of XDL, all those tools are not longer usable for the next series. The aim of this work is to make possible to keep using these tools with the new device series, by making them interoperable with Vivado.
The thesis is organised as follows:
1. Chapter FPGA describes the structure of FPGAs;
2. Chapter XDL provides a brief introduction to Xilinx Design Language for FPGA and design descriptions;
3. Chapter Vivado explains what Vivado is, its characteristics and its
differences from ISE;
4. Chapter Viv2XDL shows the tool developed in this thesis; 5. Chapter Examples reports some examples of use of the tools.
