A Low–Noise, High-Linearity Balanced Amplifier in
Enhancement-mode GaAs pHEMT Technology for
Wireless Base-Stations
Thomas Chong
Wireless Semiconductor Division, Agilent Technologies (Malaysia) Bayan Lepas Free Industrial Zone, 11900 Bayan Lepas
Penang, Malaysia
Tel: 60-4-6805791 Fax: 60-4-6423732 Email: thomas-ck_chong@agilent.com
Abstract — This paper describes the design and
realization of a balanced low-noise amplifier (LNA) module in the 2GHz band suitable for wireless infrastructure (base-station) receiver front-end applications. The design effort entails both aspects of MMIC and module/packaging design to realize a fully-matched solution in a miniature 5mmx6mm footprint. The MMIC design leverages Agilent Technologies’ proprietary 0.5 micron enhancement-mode Pseudomorphic High-Electron-Mobility Transistor (e-pHEMT) technology for best-in-class noise performance and linearity. In a balanced amplifier application with external 3-dB hybrids, this design exhibits a very low noise figure (NF) of 0.9dB, coupled with a high OIP3 (Output Third Order Intercept Point) of 46dBm at 31dB gain. It is also capable of delivering a P-1dB of 31dBm at 2.0GHz with a 5.0V supply.
I. INTRODUCTION
Designers of wireless base-station circuits face increasing challenges in terms of size, cost and design cycle-time without compromising the stringent requirements imposed on them. For example, Tower-Mounted Amplifiers (TMA) and Receiver Front Ends must meet the duality of low NF (<1dB) and high OIP3 (45dBm). In addition, these amplifiers have to be load- and source-insensitive, meaning that the input and output return losses have to be 20dB or better. To achieve this, such amplifiers are typically balanced amplifiers employing hybrid couplers [1]. Although there are many solutions in the market capable of meeting these requirements, they typically are multi-stage designs using many discrete components thus requiring much engineering effort to realize. At Agilent Technologies, significant progress has been made in overcoming the low noise-vs-linearity-vs-efficiency conundrum through a proprietary 0.5um GaAs e-pHEMT process [2]. This paper demonstrates that with appropriate device sizing, biasing and matching at the die level and in combination with a few miniature surface-mount discrete components in an encapsulated chip-on-board (COB) package, an extremely low-noise, high-linearity, high-power amplifier can be designed without resorting to fancy and complicated circuitries. The result is an easy-to-use module measuring 5x6x1.1mm3 requiring only external 3-dB hybrid couplers and some external standard de-coupling capacitors.
II. BALANCED AMPLIFIER DESIGN PHILOSOPHY
Figure 1 shows the simplified diagram of the balanced amplifier module. Basically the topology consists of two identical mirror-imaged amplifier chains, each having two amplifying stages. The first (input) stage is a high-gain, low noise amplifier, which determines the NF, while the second (output) stage delivers the power and determines the overall OIP3. The amplifier stages and associated bias and matching components are all contained within the module. The 3-dB hybrid couplers are connected externally. The advantage of such a design is the flexibility it affords to the user in the choice of couplers for reasons of cost, size and performance (especially the insertion loss). In some applications, users may use the (single-ended) amplifiers independently.
Fig. 1. Block diagram of the balanced amplifier III. THE DIE-LEVEL AMPLIFIER DESIGN
Figure 2 shows the simplified schematic of each amplifier chain within the module. As indicated, each amplifier chain consists of an on-chip section and some off-chip discrete (surface-mount) passive components. The Agilent Technologies Advanced Design System (ADS) simulator was used extensively to predict and
Input match
Interstage
match Outputmatch
Input
match Interstagematch Outputmatch
In Bias V dd Vdd Bias 1 Out Bias2 3-dB Hybrid 3-dB Hybrid 50 Ohms 50 Ohms Bias
optimize the small-signal and non-linear performance of each amplifier stage during the design phase. The simulation schematic for the amplifier stages is shown in Figs. 3 and 4. Agilent’s proprietary non-linear, small-signal and noise models for the FETs were used to ensure accurate simulation results. The transistor (FET) Q1 is connected as a conventional common-source amplifier and input-matched using a high-Q wirewound shunt inductor for the best NF. This is followed by a series coupling capacitor to the gate of Q1. The latter is sized at 800um to give 16dB of gain.
Fig. 2. Simplified schematic of each amplifier chain.
Fig. 3. Simulation schematic of the first stage amplifier.
Fig. 4. Simulation schematic of the second stage amplifier. Since the amplifiers will be used in balanced configuration the input matching inductor is selected not for optimum return loss, but for best NF. Source tuning is featured as it affords easier input matching as close to Fmin as possible (see Fig. 5). Being a low-noise high-gain stage, extreme care is needed to stabilize the device without compromising NF. In this respect the amount of source inductance, which is provided by a bond wire,
must be carefully chosen. Stabilization is achieved by means of a resistor-loaded inductor at the output of Q1. The gate bias for Q1 is provided via a diode-connected current mirror FET Q2. The size of Q2 is carefully chosen for its noise contribution and current delivery to the gate of Q1. Noise from Q2 is mitigated by appropriate choice of a shunt capacitor and isolating resistor at the gate of Q1. The value of the isolating resistor must be big enough to block the noise, yet small enough to not add significant thermal noise into Q1. The value of the resistor is also critical in setting the P1-dB of Q1 to effectively drive Q3. Through simulation, a 10k-ohm resistor was found to be appropriate.
Fig. 5. Fmin vs Ids and Vds of a 800um FET in Agilent’s 0.5um GaAs E-pHEMT process
The output FET Q3 is also connected as a common – source amplifier. It is sized at 6400um to give at least 27dBm of OP1-dB, 45dBm of OIP3 and 15dB of gain. Unlike Q1, the source of Q3 is hard-grounded using vias for optimum gain and power output performance. The bias circuit for Q3 consists of a dual-pHEMT self-compensating current source [3]. The output matching for Q3 is of a high-pass configuration to kill low-frequency gain to maintain stability in that region. All the inter-stage matching between Q1 and Q3 are located on-chip. A CMOS-compatible switch Q4 enables independent switching/control of either amplifier chain. The simulated performance of each amplifier chain is shown in Figs. 8 to 11.
Fig. 6. Photomicrograph of the actual MMIC. The die occupies an area of 2.75mm2
.
Fig. 7. PCB layout of the module showing the MMIC and discrete components.
Figure 6 shows the layout of the MMIC in Agilent’s proprietary 0.5um enhancement-mode GaAs-AlGaAs
Q1 STAGE R R3 SRL L2 SRL L1 Port PA_ON Num=1 L L10 L=27 pH R R1 Port VDD Num=3 M LIN TL74 MLIN TL73 VIA2 V1 Port RF_IN Num=2 MLOC TL70 MLIN TL75 MLOC TL79 PCTRACE TL69 PCTRACE TL78 BONDW1 WIRESET6 1 R R2 MLOC TL76 MLOC TL71 MLOC TL77 BONDW1 WIRESET3 1 Port RF_OUT Num=4 Q2 STAGE Port PA_ON Num=1 R R35 GaAsFET FET 4 PCTRACE TL11 MLOC TL29Port RF_OUT Num=4 VIA2 C21 VIA2 C18 Port RF _IN Num=2 MLOC TL16 Port VD D Num =3 SRL SRL4 MLOC TL17 MLOC TL18 MLOC TL23 PCTRACE TL26 MLOC TL24 MLOC TL21 MLOC TL19 PCTRACE TL25 PCTRACE TL27 PCTRACETL28 C C4 GaAsFET FET 3 R R34 VIA2 C20 GaAsFET FET2 SRL SRL5 SRL SRL2 SRL SRL1 BONDW 4 WIR ESET6 1 2 3 4 L L22 R= L=27 pH L L16 L=27 pH 0.00 0.10 0.20 0.30 0.40 0.50 0 20 40 60 80 100 Ids (mA) Fm in (dB ) Vds=2V Vds=3V Vds=4V 2 GHz F400-024C Vctrl Vdd On-Chip Schematic RF_IN RF_OUT Off-chip components (on module PCB) Off-chip components (on module PCB) Q1 Q3 Q4 Q2 Vctrl Vctrl Vdd Vdd On-Chip Schematic RF_IN RF_OUT Off-chip components (on module PCB) Off-chip components (on module PCB) Q1 Q3 Q4 Q2
Source bond w ire
pHEMT process. The fabrication uses molecular beam epitaxy (MBE) on 6” wafers. Being an enhancement-mode technology means that the device requires only positive voltage supplies thus doing away with the problematic power-up sequence required of (negative-gate-bias) depletion-mode types. Threshold voltage is about 0.4V with 550mS/mm transconductance, and a respectable fT of about 30GHz. The extremely low Fmin
in combination with high fT at the die level enables the
design of amplifiers with the duality of very low noise and high linearity.
IV. THE MODULE AND PACKAGING DESIGN
The simulation schematics in Figs. 3 and 4 also include packaging parasitics, i.e. bond wires, bond pads, board traces, component pads and via holes. The layout of the module is shown in Fig. 7. The PCB material is Getek®
Fig. 8. S-parameter simulation results.
Fig. 9. Harmonic balance simulation results.
with a dielectric constant of 3.9. It is imperative that the simulation effort be an on-going exercise to track
changes in the layout and design. As a result all critical electrical parameters were met after just one turn of wafer and module PCB fabrication! Figure 12 shows the final encapsulated module mounted on a Rogers® RO4350 evaluation demoboard with a dielectric constant of 3.48.
Fig. 10. Noise figure simulation.
Fig. 11. Source and load stability circles to ensure stability of the design up to 20GHz.
Fig. 12. The module mounted on demoboards for single-ended (left) and balanced (right) measurements.
For the balanced application, the 3dB quadrature hybrid couplers used here are Anaren®’s commercially available components with datasheet performance of 0.12dBmax insertion loss and >20dB return loss [4].
indep(Source_stabcir) (0.000 to 51.000) S our ce_st abci r indep(Load_stabcir) (0.000 to 51.000) Load_st a bc ir
V. MEASURED PERFORMANCE
The typical single-ended performance for each amplifier channel is shown below in Table 1. Fig. 13 shows the actual s-parameter plots.
Table 1 : Single-Ended Performance at 2GHz Supply voltage: 5.0V Small-signal Gain: 31dB Noise Figure: 0.60dB Psat/Current: 29.3dBm/340mA OP-1dB/Current/PAE: 27.8dBm/309mA/39% OIP3: 46dBm
Pout/Current @ OIP3: 15dBm/381mA Input/Output Return Loss: 12dB/10dB
Fig. 13. S-parameter plots of actual single-ended performance. Table 2. Summary of simulated vs actual performance over the design bandwidth of 1.8-2.2GHz
Table 2 shows the comparison between simulated and actual performance. Very good correlation was obtained for most parameters. Simulated noise figure is typically slightly more optimistic than actual due to unaccounted-for sources of noise such as the power supply, ambient radiation and package molding material. Simulated OIP3 is typically poorly correlated. When connected as a balanced amplifier, the overall performance depends on the quality of the hybrids used. Typical insertion loss ranges from 0.1dB to 0.3dB. At the input of the amplifier, this would cause a dB-for-dB degradation in the NF. At the output, due to the 3dB combining effect of the coupler, the OP-1dB and OIP3 should theoretically be increased by 3dB. Fig. 14 shows the s-parameter plots of
the balanced amplifier. The return losses have been improved by the hybrids over that of the single-ended performance, i.e. the S11 and S22 improved to about 19dB (at 2GHz) compared to 12 and 10dB respectively. Noise figure degraded to 0.9dB, which is more than the insertion loss (0.1dB) of the input coupler. The additional loss can be attributed to trace losses between the coupler and the module, and coupling between the two halves of the balanced amplifier due to non-optimum layout. The OP-1dB and OIP3 measured 31dBm and 46dBm respectively.
Fig. 14. S-Parameter plots for the balanced amplifier.
VI. CONCLUSION
The design and measured performance of a low-noise, high-linearity, high-power amplifier module at 1.8-2.2GHz has been presented. At 2GHz, an extremely low NF of 0.6dB (single-ended) and 0.9dB (balanced) has been achieved, in addition to providing 46dBm of OIP3 and OP-1dB of 31dBm. With internal matching, an easy-to-use solution has been realized with a performance level meeting the stringent requirements of wireless base-station receiver front-end amplifiers. To our knowledge this represents a significant breakthrough in terms of performance, size, cost and convenience versus that of currently available solutions.
ACKNOWLEDGEMENT
I would like to thank my colleagues, YH Chow, CK Yong, CC Loh, Zulfa Hasan and KO Yap for their valuable assistance, and my managers EK Teoh, KP Ho and EC Chew.
REFERENCES
[1] S. Liao, “Microwave Devices and Circuits”, 3ed, pp154-156, Prentice-Hall,1990
[2] Wu et al, “An Enhancement-Mode pHEMT for Single- Supply Power Amplifiers”, HP Journal, Feb 1998, pp39-51. [3] P. R. Gray et al, “ Analysis and Design of Analog Integrated Circuits,” 4ed, pp 308-309, Wiley, 2001
[4] Anaren Xinger II XC1900A-03 datasheet
380-400 370 mA Current 9-27 10-13 15 43-46 27-29 30-32 0.5-0.65 Actual 10-24 10-15 14-15.5 36-37 25-26 29-31 0.4-0.5 Simulated dB Noise Figure dBm P1dB dBm dBm
OIP3 - Fund power - OIP3 Output RL Input RL Gain Parameter dB dB dB Units 380-400 370 mA Current 9-27 10-13 15 43-46 27-29 30-32 0.5-0.65 Actual 10-24 10-15 14-15.5 36-37 25-26 29-31 0.4-0.5 Simulated dB Noise Figure dBm P1dB dBm dBm
OIP3 - Fund power - OIP3 Output RL Input RL Gain Parameter dB dB dB Units m 1 freq= m 1=23.276563 .0 MHz m 2 freq= m 2=31 .3 281.800G Hz m 3 freq = m 3 =31.2732.000G Hz m 4 freq= m 4=29.5882.200 GHz m 5 freq= m 5=24.99 12.400GHz m 1 2 freq = m 1 2=31.7551.60 0GHz 1 2 3 4 5 0 6 -40 -30 -20 -10 0 10 20 30 -50 40 freq, GHz d B (S (2 ,1 )) m 1 m 2m 3m 4 m 5 m 12 d B (S (1 ,2 )) d B (S (1 ,1 )) d B (S (2 ,2 )) Vctrl=2.2V m1 freq= m1=24.032647.0MHz m 2 freq= m 2=31.0461.800G Hz m3 freq= m3=31.2962.000G Hz m4 freq= m4=30.1522.200G Hz m5 freq= m5=25.9922.400G Hz m12 freq= m12=31.1321.600GHz 1 2 3 4 5 0 6 -40 -30 -20 -10 0 10 20 30 -50 40 freq, GHz d B (S (2 ,1 )) m 1 m2m3m4 m5 m 12 d B (S (1 ,2 )) d B (S (1 ,1 )) d B (S (2 ,2 )) Vctrl=2.2V
