Codice VHDL Appendice B

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Appendice B

Codice VHDL

Blocco di bisezione doppia………...164

Blocco del Vernier (Nonio)………..170

Controllore di fase………175

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-- Nome file : Bisezione.vhd; -- Autori : Gelasio Gregorio ;

-- Montepaone Maria Concetta ; -- Librerie

library IEEE;

use IEEE. std_logic_1164. all; use IEEE. std_logic_arith. all;

-- Entita'

entity Bisezione is

port (Trig,Trig_n,ck,reset : in std_logic; sel1,sel2,e1,e2,e_nonio : out std_logic;

b_1,b_2 : out std_logic_vector ( 6 downto 0)); end Bisezione;

-- Architettura

architecture Bisezione_behav of Bisezione is

type state_type is (start,s0,s1,s1_A,s2_A,s3_A,s4_A,s5_A,s6_A,s7_A,s8_A, s1_B,s2_B,s3_B,s4_B,s5_B,s6_B,s7_B,s8_B,sf);

signal stato : state_type;

signal reg_1,reg_2 : std_logic_vector ( 6 downto 0 ); signal flag : std_logic;

begin

process begin

wait until (ck'event and ck = '1'); if (reset ='1') then reg_1 <= "0000000"; reg_2 <= "0000000"; stato <= start; else case stato is when start => reg_1 <= "0000000"; reg_2 <= "0000000"; e_nonio <= '0'; sel1 <='0'; sel2 <='1';

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e1 <='0'; e2 <='1'; stato <= s0; when s0 =>

if (Trig ='1') and (Trig_n ='0') then -- Clk_A anticipo su Clk_B

sel1 <='1';

sel2 <='0';

flag <='0';

stato <= s1;

else if (Trig ='0') and (Trig_n ='1') then -- Clk_B anticipo su Clk_A flag <='1'; stato <= s1; else stato <= s0; end if; end if; when s1 => e1 <='1'; e2 <='0'; reg_1 <= "1111111"; reg_2 <= "0000000";

if flag ='0' then stato <= s1_A; else stato <= s1_B; end if;

-- se la configurazione iniziale dello sfasamento produce (Trig=0; Trig_n=1)

when s1_B =>

reg_1(6) <= '0';

reg_2(6) <= '1';

stato <= s2_B; when s2_B =>

if (Trig ='1') and (Trig_n ='0') then reg_1(6) <= '1'; reg_2(6) <= '0'; reg_1(5) <= '0'; reg_2(5) <= '1'; stato <= s3_B; else reg_1(5) <= '0'; reg_2(5) <= '1'; stato <= s3_B; end if; when s3_B =>

if (Trig ='1') and (Trig_n ='0') then reg_1(5) <= '1';

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reg_1(4) <= '0'; reg_2(4) <= '1'; stato <= s4_B; else reg_1(4) <= '0'; reg_2(4) <= '1'; stato <= s4_B; end if; when s4_B =>

if (Trig ='1') and (Trig_n ='0') then reg_1(2) <= '1'; reg_2(2) <= '0'; reg_1(1) <= '0'; reg_2(1) <= '1'; stato <= s7_B; else reg_1(1) <= '0'; reg_2(1) <= '1'; stato <= s7_B;

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end if;

when s7_B =>

if (Trig ='1') and (Trig_n ='0') then reg_1(0) <= '1'; reg_2(0) <= '0'; stato <= sf; else reg_1(0) <= '0'; reg_2(0) <= '1'; stato <= sf; end if;

when s1_A =>

reg_1(6) <= '0';

reg_2(6) <= '1';

stato <= s2_A; when s2_A =>

if (Trig ='0') and (Trig_n ='1') then reg_1(6) <= '1'; reg_2(6) <= '0'; reg_1(5) <= '0'; reg_2(5) <= '1'; stato <= s3_A; else reg_1(5) <= '0'; reg_2(5) <= '1'; stato <= s3_A; end if; when s3_A =>

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if (Trig ='0') and (Trig_n ='1') then reg_1(2) <= '1'; reg_2(2) <= '0'; reg_1(1) <= '0'; reg_2(1) <= '1'; stato <= s7_A; else

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reg_1(1) <= '0'; reg_2(1) <= '1'; stato <= s7_A; end if; when s7_A =>

if (Trig ='0') and (Trig_n ='1') then reg_1(0) <= '1'; reg_2(0) <= '0'; stato <= sf; else reg_1(0) <= '0'; reg_2(0) <= '1'; stato <= sf; end if; when sf => e_nonio <= '1'; reg_1 <= reg_1; reg_2 <= reg_2; end case; end if; end process ; b_1 <= reg_1; b_2 <= reg_2; end Bisezione_behav;

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-- Nome file : Vernier.vhd; -- Autori : Gelasio Gregorio;

-- Montepaone Maria Concetta;

-- Librerie

library IEEE;

-- Entita'

entity Vernier is

port (e_nonio,Trig,Trig_n,ck,reset : in std_logic; c : out std_logic_vector (9 downto 0)); end Vernier;

-- Architettura

architecture Vernier_behav of Vernier is

type state_type is (s0,s1,s2_A,s3_A,s4_A,s5_A,s6_A,s7_A,s8_A,s9_A,s10_A, s11_A,s2_B,s3_B,s4_B,s5_B,s6_B,s7_B,s8_B,s9_B,s10_B,s11_B,sf); signal state : state_type;

signal reg : std_logic_vector (9 downto 0); begin

process begin

wait until (ck 'event and ck ='1'); if (e_nonio ='0') then state <= s0; reg <= "0000000000"; else state <= s1; case state is when s0 => reg <="0000000000"; when s1 =>

if (Trig ='0') and (Trig_n ='1') then state <= s2_B;

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state <= s2_A; end if;

end if;

when s2_B =>

if (Trig ='0') and (Trig_n ='1') then reg(0) <='1'; state <= s3_B; else reg <=reg; state <= sf; end if; when s3_B =>

if (Trig ='0') and (Trig_n ='1') then reg(4) <='1'; state <= s7_B; else reg <=reg; state <= sf; end if;

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when s7_B =>

if (Trig ='0') and (Trig_n ='1') then reg(9) <='1'; state <= sf; else reg <=reg; state <= sf; end if;

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when s2_A =>

if (Trig ='1') and (Trig_n ='0') then reg(0) <='1'; state <= s3_A; else reg <=reg; state <= sf; end if; when s3_A =>

if (Trig ='1') and (Trig_n ='0') then reg(5) <='1';

state <= s8_A; else reg <=reg;

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state <= sf;

end if;

when s8_A =>

if (Trig ='1') and (Trig_n ='0') then reg(9) <='1'; state <= sf; else reg <=reg; state <= sf; end if; when sf => state <= sf; reg <= reg; end case; end if; end process; c <= reg; end Vernier_behav;

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-- Nome file : Controller.vhd; -- Autori : Gelasio Gregorio ;

-- Montepaone Maria Concetta ;

-- Librerie

library IEEE;

-- Entita'

entity Controller is

port ( Trig,Trig_n,ck,reset : in std_logic;

b_1,b_2 : out std_logic_vector (6 downto 0); c : out std_logic_vector (9 downto 0); sel1,sel2,e1,e2: out std_logic);

end Controller;

-- Architettura

architecture Controller_arch of Controller is component Bisezione

port ( Trig,Trig_n,ck,reset : in std_logic;

b_1,b_2 : out std_logic_vector (6 downto 0); sel1,sel2,e1,e2,e_nonio : out std_logic);

end component; component Vernier

port ( Trig,Trig_n,e_nonio,ck,reset : in std_logic;

c : out std_logic_vector (9 downto 0)); end component;

signal n1 : std_logic;

begin

u1 : Bisezione port map ( Trig,Trig_n,ck,reset,b_1,b_2,sel1,sel2,e1,e2,n1); u2 : Vernier port map ( Trig,Trig_n,n1,ck,reset,c);

end Controller_arch;

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-- Nome file : Controller_tb.vhd; -- Autori : Gelasio Gregorio ;

-- Montepaone Maria Concetta ;

-- Librerie

library IEEE;

-- Entita'

entity Controller_tb is end Controller_tb;

-- Architettura

architecture Controller_tb_arch of Controller_tb is component Controller is

port ( Trig,Trig_n,ck,reset : in std_logic;

b_1,b_2 : out std_logic_vector (6 downto 0); c : out std_logic_vector (9 downto 0); sel1,sel2,e1,e2 : out std_logic);

end component;

constant period_clock : time:= 20 ns; signal clock,Trig,Trig_n,reset : std_logic;

signal b_1,b_2 : std_logic_vector (6 downto 0); signal c : std_logic_vector (9 downto 0);

-- Inizio Simulazione

begin

-- Units under test

U0: Controller

port map ( ck => clock, Trig => Trig,

Trig_n => Trig_n,

reset => reset,

b_1 => b_1, b_2 => b_2,

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c => c); process

begin

clock <= '1';

waitfor period_clock/2; clock <= '0';

wait for period_clock/2; end process; -- Ingressi process begin reset <= '0'; wait for 10 ns; reset <= '1'; wait for 10 ns; reset <= '0'; -- wait for 60 ns; -- reset <= '1'; -- wait for 20 ns; -- reset <= '0'; wait; end process;

-- Generazione dei segnali Trig e /Trig prodotti dal phase detector.

process begin Trig <='1'; wait for 50 ns; Trig <='0'; wait for 60 ns; Trig <='1'; wait for 40 ns; Trig <='0'; wait for 20 ns; Trig <='1'; wait for 40 ns; Trig <='0'; wait for 180 ns; Trig <='1'; wait; end process;

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process begin Trig_n <='0'; wait for 50 ns; Trig_n <='1'; wait for 60 ns; Trig_n <='0'; wait for 40 ns; Trig_n <='1'; wait for 20 ns; Trig_n <='0'; wait for 40 ns; Trig_n <='1'; wait for 180 ns; Trig_n <='0'; wait; end process; end Controller_tb_arch; -- Configurazione

configuration Controller_tb_config of Controller_tb is for Controller_tb_arch

for U0: Controller

use entity work.Controller(SYN); end for;

end for;

end Controller_tb_config;