Chapter 7: Conclusion
148
7 CONCLUSION
In this work a complete verification and validation flow for a new software programmable I2C/SPI interface on APB BUS is presented.
The two key elements to interface verification are verifying compliance with the specification, and verifying interoperability with other compliant devices.
According to the verification methodology and approach shown in the section 1.7 the figure below shows the validation steps performed for our interface.
• Block- and Bus-level verification • System-level verification • Hardware emulation μP DSP block-set memory IP#3 IP#4 μPμP DSP block-set DSP block-set memory memory IP#3 IP#3 IP#4 IP#4 4 4 4 IP#2 IP#1 B R I D G E IP#2 IP#2 IP#1 IP#1 B R I D G E system-level TEST #p system-level TEST #p software pattern #p software pattern #p 3 3 DUT DUT block-level TEST #n 1 block-level TEST #n block-level TEST #n 11 bus-level TEST #m 2 bus-level TEST #m bus-level TEST #m 2 2
Chapter 7: Conclusion
149 Our I2C/SPI interface has been first validated in I2C slave mode vs. a public available I2C master, whose behavioural HDL description can be found on www.opencores.org.
The two interfaces have been linked on the I2C bus and then several tests (see conformance matrix below have been performed. All the slave features are checked with positive results.
After that the validation of the I2C/SPI interface in I2C master mode has been carried out vs. the I2C slave module validated at the previous step and no difference has been detected on the behaviour of our I2C/SPI interface in I2C master mode with respect to the public available I2C master model.
Feature Test SPI/I2C in slave mode vs. external master I2C Test master mode vs. validated slave
Start/Stop generation N.A. 9
Start/Stop detection 9 9
7- or 10-bit address gen. N.A. 9
7- or 10- bit address detection 9 9
Data sampling sync. with SCL 9 9
Data TX/RX 9 9
Multibyte data TX/RX 9 9
Fast mode 9 9
Clock Stretching N.A. 9
Arbitration Lost N.A. 9
Chapter 7: Conclusion
150 After the functional verification at the previous two steps a timing verification has been performed. The I2C/SPI interface has been synthesized then the gate-level DUT has been feed with the same tests as at the previous steps and a design timing constraint check has been done with positive result.
After the interface has been verified stand-alone an embedded system has been designed featuring the I2C/SPI interface. Due to the collaboration with the company Sensor Dynamics that performs research and development activities based on the LEON-2 platform, our embedded system has been designed using this processor.
The LEON-2 is a synthesizable processor developed by ESA and maintained by Gaisler Research and it targets both the ASIC and FPGA markets. It’s a 32-bit RISC SPARC V8 compliant architecture. The IP has been first validated at system level within the Leon CVS environment. The I2C/SPI interface has been linked on the APB bus inside the Leon Core and then several tests files in SPARC-V8 assembly language have been written to check the functionalities of our interface. Many of the tests already executed at Block- and Bus- Level have been performed again at system level with positive result.
The last step of the validation flow has been the prototyping on the Virtex-II development board from Memec of the Leon core featuring the I2C/SPI interface.
The development board includes a Xilinx Virtex-II FPGA (XC2V1000-4FG456C), which is clocked by an onboard oscillator operating at 24 MHz and the P160 expansion module which enables further application specific prototyping and testing.
The hardware design has been downloaded to the FPGA via the onboard JTAG interface and several tests has been executed
Assembly programs to test the functionality of the I2C/SPI interface have been written. Transfers at 100 kbit/s (Standard-mode) and 400 kbit/s (Fast-mode) have been performed and both give positive result.
To probe the I2C Bus on the board the Tektronix TDS3000B Digital Phosphor Oscilloscope has been used. The automatic measure functions of the oscilloscope have been used to check the peak to peak voltage for both lines and the rise time, period and frequency of the SCL clock with positive result.
Chapter 7: Conclusion
151 The compliance to the I2C protocol and the interoperability of the new interface have been shown. The I2C/SPI VHDL model verified and validated can be used as "golden
model" across the industry to ensure quality and interoperability of new interfaces
