POLITECNICO DI TORINO ESAMI DI STATO PER L’ABILITAZIONE ALLA PROFESSIONE DI INGEGNERE DELL’INFORMAZIONE II Sessione 2016 - Sezione A Settore dell’Informazione PROVA PRATICA del 22 dicembre 2016

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POLITECNICO DI TORINO

ESAMI DI STATO PER L’ABILITAZIONE ALLA PROFESSIONE DI INGEGNERE DELL’INFORMAZIONE

II Sessione 2016 - Sezione A Settore dell’Informazione

PROVA PRATICA del 22 dicembre 2016

Il candidato svolga uno a scelta fra i seguenti temi proposti.

Gli elaborati prodotti dovranno essere stilati in forma chiara e ordinata.

La completezza, l’attinenza e la chiarezza espositiva costituiranno elementi di valutazione.

Tema n. 1

La maggioranza dei trattori agricoli e delle macchine movimento terra è costruita senza alcun tipo di sospensione tra le ruote ed il telaio: le vibrazioni trasmesse all’operatore vengono controllate mediante la sospensione del sedile. Esistono molti tipi di sospensione in commercio; nei casi più semplici vengono utilizzati soltanto dei cuscini assemblati con molle e schiuma; nei casi più complessi vengono realizzati veri e propri meccanismi di sospensione dotati di molla e smorzatore.

In tutti i casi il sistema di sospensione del sedile è caratterizzato da una frequenza di risonanza in corrispondenza della quale le vibrazioni vengono amplificate. Nel cuscino di schiuma e molle normalmente questa frequenza si situa nell’intorno dei 4 Hz, mentre nel caso della sospensione con molla e smorzatore questa frequenza è più bassa e pari a circa 2 Hz. La seguente figura riporta due andamenti tipici della funzione di trasmissibilità, cioè del rapporto tra lo spostamento in ingresso alla base del sedile e quello percepito dall’autista.

Segue Tema 1 >>

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Considerando un conducente, di massa pari a 90 kg, alla guida di un veicolo che deve superare un dosso artificiale di profilo esattamente sinusoidale di lunghezza pari a 50 cm ed altezza pari a 5 cm, si richiede, utilizzando un semplice sistema ad un grado di libertà, di eseguire le seguenti valutazioni:

1. Sulla base della curva foam and metal sprung seat indicare quale procedimento si dovrebbe seguire per ottenere valori approssimati dei parametri k e c della sospensione realizzata mediante cuscino di schiuma e molle;

2. Dati k = 201324 N/m e c = 4300 Ns/m, si tracci la curva di trasmissibilità teorica;

3. Si calcoli l’accelerazione massima a

_max

sopportata dal conducente alla velocità di 15 km/h.

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Tema n. 2

Il candidato progetti un controllo per un sistema meccanico massa-molla-smorzatore.

Prima parte

A) In base alla figura seguente il candidato ricavi un modello fisico del sistema meccanico,

considerando come ingresso la forza F e come uscita la posizione p della massa e i seguenti valori numerici dei parametri:

K = 5 N/m , β= 1 Ns/m , M = 10 kg

B) Il candidato identifichi un modello dinamico lineare sulla base della risposta ad una successione di gradini mostrata in figura, dove la linea tratteggiata rappresenta la variazione della forza F in newton e la linea continua rappresenta la conseguente variazione della posizione p in metri.

Il candidato scelga l'ordine del modello in modo che sia minimo, pur riproducendo ragionevolmente bene l'andamento dell'uscita, e ne ricavi i valori numerici dei parametri argomentando le scelte fatte.

C) Il candidato confronti i risultati ottenuti al punto A e al punto B.

Segue Tema 2 >>

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Seconda parte

A prescindere dai risultati ottenuti nella Prima parte, si assuma come modello complessivo dell'impianto (comprendente attuatore e trasduttore considerati ideali) la seguente funzione di trasferimento:

P ( s)

F ( s) = 4 1+1.36 s+6 s

²

Il committente richiede il progetto di un dispositivo di controllo che soddisfi i seguenti requisiti:

1 – la posizione p a regime deve essere esattamente uguale alla posizione di riferimento supposta costante;

2 – la posizione p deve raggiungere il 90% della posizione di riferimento al massimo in 15 secondi;

3 – la forza F non deve superare 8 N se si impone uno spostamento pari a 1 m.

Il candidato trasformi questi requisiti qualitativi in specifiche (come intese abitualmente in ambito controllistico), ed eventualmente ne aggiunga altre ritenute necessarie.

Quindi, sulla base delle specifiche da lui definite e del modello complessivo dell'impianto, progetti un dispositivo di controllo digitale, caratterizzandone la struttura e l'algoritmo; inoltre illustri le caratteristiche dei dispositivi di conversione A/D e D/A che intende utilizzare.

Se possibile si progetti il compensatore analogico (da discretizzare) o direttamente il compensatore digitale utilizzando almeno due metodi tra progetto in frequenza, sintesi diretta e retroazione dagli stati con osservatore.

Nota: l'eventuale tracciamento di diagrammi di Bode e/o di Nichols sia fatto sugli appositi fogli da

richiedersi alla Commissione.

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Pulsazione ω

Carta semilogaritmica a 6 decadi

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Pulsazione ω

Carta semilogaritmica a 9 decadi

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C

D (s) =

1+ s

!

D

1+ s

m

D

!

D

; m

D

> 1

10⁻¹ 10⁰ 10¹ 10²

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25

ω / ω_D

m_D=2 3 4 5 6 8 10 12 14 16

10⁻¹ 10⁰ 10¹ 10²

0 5 10 15 20 25 30 35 40 45 50 55 60 65

ω / ω_D m_D= 2

3 4

5 6

8 10

12 14

16

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Tema n. 3

I sistemi di comunicazioni mobile 5G di prossima generazione utilizzeranno anche bande di frequenze più elevate di quelle dei sistemi 2G/3G/4G attuali, ad esempio 6 GHz, 30 GHz, 100 GHz.

1. Si discutano le problematiche relative al funzionamento di un sistema di trasmissione ad onde millimetriche.

Si supponga di dover progettare un sistema radio capace di trasmettere su di un canale di trasmissione di ampiezza totale pari a 100 MHz, attorno alla frequenza di trasmissione di 6 GHz.

Si supponga di utilizzare un dispositivo mobile che utilizza una modulazione 4-PSK a singola portante con filtri di trasmissione e di ricezione del tipo radice di coseno rialzato con coefficiente di roll-off pari a 0.2. La potenza di trasmissione è pari a 1 W.

2. Si scelgano valori realistici per le seguenti grandezze e parametri:

a. Tipo e guadagni di antenna in trasmissione (dispositivo mobile) ed in ricezione (base station).

b. Cifra di rumore.

Come canale di trasmissione semplificato si consideri in prima battuta un collegamento in piena vista.

3. Si supponga un margine di 30 dB e si discuta quali sono tutte le perdite aggiuntive che questo margine deve neutralizzare.

Si supponga di dover garantire una probabilità di errore pari a 1e-12.

4. Si calcoli la massima distanza che si può coprire con questo sistema radio.

Si consideri ora l’utilizzo di una modulazione multiportante OFDM nel caso di trasmissione su canale con multipath con delay spread pari a 1 µs.

5. Si scelgano i parametri caratteristici della modulazione OFDM, in particolare l’ampiezza di ogni sotto-banda, il numero di portanti, il prefisso ciclico ed il numero di portanti utilizzate.

6. Si presentino gli schemi del modulatore e del demodulatore, discutendo i blocchi costituenti, e la dimensione degli algoritmi FFT da utilizzare.

7. Si discutano le criticità generate dall’uso di una modulazione OFDM.

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Tema n. 4

Il candidato progetti un sistema di monitoraggio di un velivolo, che tenga sotto controllo alcuni parametri, fra cui la temperatura del motore e le vibrazioni delle ali, avente preferibilmente le seguenti caratteristiche:

1) Temperature del motore:

a. Intervallo di misura: +200°C ... +1000°C b. Accuratezza: +/- 1°C

c. Unità di misura della memorizzazione: 1K d. Risoluzione della memorizzazione: 1/8 K e. Frequenza di acquisizione: 1 campione/s 2) vibrazioni:

a. Intervallo di misura: -10 … +10 g b. Accuratezza: +/- 0.1 m/s

²

c. Unità di misura della memorizzazione: 1 m/s

²

d. Risoluzione della memorizzazione: 0.01 m/s

²

e. Intervallo di frequenze utili: [1 Hz .. 100 Hz) 3) Capacità di memoria:

a. Minimo 100 ore di volo 4) Sorgente di alimentazione:

a. Il sistema dovrà funzionare con alimentazione esterna 12 +/- 2V DC; max 100mA.

b. In assenza di alimentazione esterna, il sistema dovrà continuare a funzionare per almeno 10 ore con batterie ricaricabili interne che si ricaricano automaticamente in presenza di tensione di alimentazione.

Il candidato dovrà, nell’ordine:

1) Ipotizzare e descrivere operativamente alcune funzionalità del sistema, che contemplino almeno la possibilità di avviare e terminare l’acquisizione dei dati automaticamente quando il motore è in moto, di scaricare i dati su un PC (in qualunque modalità a scelta del candidato), di segnalare un basso livello di carica della batteria.

2) Selezionare i trasduttori o sensori di temperatura e accelerazione e le batterie ricaricabili, eventualmente selezionandoli fra quelli proposti o, se si preferisce, qualunque altro modello commercialmente disponibile (in quest’ultimo caso, citando chiaramente modello e costruttore).

3) Sviluppare il progetto architetturale del sistema e predisporre uno schema a blocchi completo del sistema, ove siano inclusi almeno tutti gli elementi HW e SW necessari al funzionamento del sistema secondo le modalità operative definite al punto precedente.

4) Si scelga un microcontrollore adatto al sistema, eventualmente scegliendo il modello MSP430F5438 della Texas Instruments di cui viene dato stralcio del datasheet.

5) Sviluppare lo schema elettrico di:

a. Sensore di temperatura b. Sensore di vibrazione c. Alimentatore

Tali da poter essere connessi direttamente all’alimentazione interna e agli ingressi analogici e/o digitali del microcontrollore.

I circuiti dovranno essere tali da poter soddisfare i requisiti. Alternativamente motivare l’impossibilità di soddisfarli.

6) Si imposti il diagramma di flusso di tutto il SW.

7) Si sviluppi, in qualsiasi linguaggio compilabile per microcontrollore la routine di inizializzazione dell’ADC del microcontrollore selezionato.

Segue Tema 4 >>

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8) Si sviluppi, in qualsiasi linguaggio compilabile per microcontrollore la routine di

inizializzazione del sensore di accelerazione.

9) Si stimi la durata delle batterie, considerando un uso continuativo ed il funzionamento definito dal diagramma di flusso sviluppato in precedenza

Allegati al testo d’esame:

1) Stralcio datasheet microcontrollore MSP430F5438 2) Stralcio user guide dell’ADC12 del MSP430F5438 3) Stralcio datasheet termocoppia TMPTJ

4) Stralcio datasheet sensore accelerazione LSM303D 5) Stralcio datasheet OP-AMP OPA378

6) Stralcio datasheet OP-AMP TSB611 7) Stralcio datasheet batteria ricaricabile

Segue: tabella temperatura-tensione termocoppia tipo K:

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Product Folder

Sample &

Buy

Technical Documents

Tools &

Software

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Community

Reference Design

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

SLAS655E – JANUARY 2010 – REVISED JULY 2015

MSP430F543xA, MSP430F541xA Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

1

– Low-Frequency Trimmed Internal Reference

• Low Supply Voltage Range:

Source (REFO) 3.6 V Down to 1.8 V

– 32-kHz Crystals

• Ultra-Low Power Consumption

– High-Frequency Crystals up to 32 MHz – Active Mode (AM):

All System Clocks Active • 16-Bit Timer TA0, Timer_A With Five 230 µA/MHz at 8 MHz, 3.0 V, Flash Program Capture/Compare Registers

Execution (Typical) • 16-Bit Timer TA1, Timer_A With Three

110 µA/MHz at 8 MHz, 3.0 V, RAM Program Capture/Compare Registers

Execution (Typical) • 16-Bit Timer TB0, Timer_B With Seven

– Standby Mode (LPM3): Capture/Compare Shadow Registers

Real-Time Clock (RTC) With Crystal, Watchdog, • Up to Four Universal Serial Communication and Supply Supervisor Operational, Full RAM Interfaces

Retention, Fast Wakeup:

– USCI_A0, USCI_A1, USCI_A2, and USCI_A3 1.7 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)

Each Support:

Low-Power Oscillator (VLO), General-Purpose

• Enhanced UART Supports Automatic Baud- Counter, Watchdog, and Supply Supervisor

Rate Detection Operational, Full RAM Retention, Fast Wakeup:

• IrDA Encoder and Decoder 1.2 µA at 3.0 V (Typical)

• Synchronous SPI – Off Mode (LPM4):

– USCI_B0, USCI_B1, USCI_B2, and USCI_B3 Full RAM Retention, Supply Supervisor

Each Support:

Operational, Fast Wakeup:

1.2 µA at 3.0 V (Typical) • I

²

C

– Shutdown Mode (LPM4.5): • Synchronous SPI

0.1 µA at 3.0 V (Typical) • 12-Bit Analog-to-Digital Converter (ADC)

• Wake up From Standby Mode in 3.5 µs (Typical) – Internal Reference

• 16-Bit RISC Architecture – Sample-and-Hold

– Extended Memory – Autoscan Feature

– Up to 25-MHz System Clock – 14 External Channels, 2 Internal Channels

• Flexible Power-Management System • Hardware Multiplier Supports 32-Bit Operations – Fully Integrated LDO With Programmable • Serial Onboard Programming, No External

Regulated Core Supply Voltage Programming Voltage Needed – Supply Voltage Supervision, Monitoring, and • Three-Channel Internal DMA

Brownout • Basic Timer With RTC Feature

• Unified Clock System • Section 3 Summarizes the Available Family – FLL Control Loop for Frequency Stabilization Members

– Low-Power Low-Frequency Internal Clock • For Complete Module Descriptions, See the

Source (VLO) MSP430x5xx and MSP430x6xx Family User's

Guide (SLAU208)

1.2 Applications

• Analog and Digital Sensor Systems • Thermostats

• Digital Motor Controls • Digital Timers

• Remote Controls • Hand-Held Meters

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

SLAS655E – JANUARY 2010 – REVISED JULY 2015 www.ti.com

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low- power modes to active mode in 3.5 µs (typical).

The MSP430F543xA and MSP430F541xA series are microcontroller configurations with three 16-bit timers, a high-performance 12-bit ADC, up to four universal serial communication interfaces (USCIs), a hardware multiplier, DMA, an RTC module with alarm capabilities, and up to 87 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, and hand-held meters.

Device Information

⁽¹⁾

PART NUMBER PACKAGE BODY SIZE⁽²⁾

MSP430F5438AZQW MicroStar Junior™ BGA (113) 7 mm × 7 mm

MSP430F5438APZ LQFP (100) 14 mm × 14 mm

MSP430F5437APN LQFP (80) 12 mm × 12 mm

(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website atwww.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data inSection 8.

Submit Documentation Feedback

Product Folder Links:MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A MSP430F5418A

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Unified Clock System

256KB 192KB 128KB

Flash

16KB

RAM MCLK

ACLK SMCLK

I/O Ports P1/P2 2×8 I/Os Interrupt Capability

PA 1×16 I/Os

CPUXV2 and Working Registers

EEM (L: 8+2) XIN XOUT

JTAG/

Interface SBW

PA PB PC PD

DMA 3 Channel XT2IN

XT OUT2

Power Management

LDO SVM/

Brownout SVS

SYS Watchdog

I/O Ports P3/P4 2×8 I/Os

PB 1×16 I/Os

I/O Ports P5/P6 2×8 I/Os

PC 1×16 I/Os

I/O Ports P7/P8 2×8 I/Os

PD 1×16 I/Os

MPY32

TA0 Timer_A

5 CC Registers

TA1 Timer_A

TB0 Timer_B

RTC_A CRC16

USCI0,1 UCSI_Ax:

UART, IrDA, SPI USCI_Bx:

SPI, I2C DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x RST/NMI

ADC12_A

200 KSPS 16 Channels (14 ext/2 int) Autoscan

12 Bit MAB

MDB

REF Unified

Clock System

256KB 192KB 128KB Flash

16KB

RAM MCLK

ACLK

SMCLK

I/O Ports P1/P2 2×8 I/Os Interrupt Capability PA 1×16 I/Os

CPUXV2 and Working Registers

EEM (L: 8+2) XIN XOUT

JTAG/

Interface SBW

PA PB PC PD

DMA 3 Channel XT2IN

XT OUT2

PE

Power Management

LDO SVM/

Brownout SVS

SYS Watchdog

PF

I/O Ports P3/P4 2×8 I/Os

PB 1×16 I/Os

I/O Ports P5/P6 2×8 I/Os

PC 1×16 I/Os

I/O Ports P7/P8 2×8 I/Os

PD 1×16 I/Os

I/O Ports P9/P10 2×8 I/Os

PE 1×16 I/Os

I/O Ports P11 1×3 I/Os

PF 1×3 I/Os

MPY32 TA0 Timer_A

TA1 Timer_A

TB0 Timer_B

RTC_A CRC16

USCI0,1,2,3 USCI_Ax:

UART, IrDA, SPI UCSI_Bx:

SPI, I2C

ADC12_A

200 KSPS 16 Channels (14 ext/2 int) Autoscan

12 Bit DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x P11.x RST/NMI

MAB

MDB

REF

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

www.ti.com SLAS655E – JANUARY 2010 – REVISED JULY 2015

1.4 Functional Block Diagrams

Figure 1-1 and Figure 1-2 show the functional block diagrams.

Figure 1-1. Functional Block Diagram – MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW

Figure 1-2. Functional Block Diagram – MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN

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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1. Family Members

^{(1) (2)}

USCI

FLASH SRAM CHANNEL A: CHANNEL B: ADC12_A

DEVICE Timer_A⁽³⁾ Timer_B⁽⁴⁾ I/O PACKAGE

(KB) (KB) UART, IrDA, SPI, I²C (Ch)

SPI

100 PZ,

MSP430F5438A 256 16 5, 3 7 4 4 14 ext, 2 int 87

113 ZQW

MSP430F5437A 256 16 5, 3 7 2 2 14 ext, 2 int 67 80 PN

100 PZ,

MSP430F5436A 192 16 5, 3 7 4 4 14 ext, 2 int 87

113 ZQW

MSP430F5435A 192 16 5, 3 7 2 2 14 ext, 2 int 67 80 PN

100 PZ,

MSP430F5419A 128 16 5, 3 7 4 4 14 ext, 2 int 87

113 ZQW

MSP430F5418A 128 16 5, 3 7 2 2 14 ext, 2 int 67 80 PN

(1) For the most current part, package, and ordering information, see the Package Option Addendum inSection 8, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available atwww.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators.

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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

5 Specifications

5.1 Absolute Maximum Ratings

⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at VCCto VSS –0.3 4.1 V

Voltage applied to any pin (excluding VCORE)⁽²⁾ –0.3 VCC+ 0.3 V

Diode current at any device pin ±2 mA

Storage temperature, T_stg⁽³⁾ –55 105 °C

Maximum junction temperature, T_J 95 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾ ±1000

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾ ±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)

MIN NOM MAX UNIT Supply voltage during program execution and flash programming

V_CC 1.8 3.6 V

(AVCC= DVCC1/2/3/4= DVCC)^{(1) (2)}

VSS Supply voltage (AVSS= DVSS1/2/3/4= DVSS) 0 V

T_A Operating free-air temperature –40 85 °C

T_J Operating junction temperature –40 85 °C

CVCORE Recommended capacitor at VCORE⁽³⁾ 470 nF

CDVCC/ Capacitor ratio of DVCC to VCORE 10

C_VCORE

PMMCOREVx = 0, 1.8 V≤ V_CC≤ 3.6 V 0 8

PMMCOREVx = 1, 2.0 V≤ VCC≤ 3.6 V 0 12

Processor frequency (maximum MCLK

fSYSTEM frequency)^{(4) (5)}(seeFigure 5-1) PMMCOREVx = 2, 2.2 V≤ VCC≤ 3.6 V 0 20 MHz

PMMCOREVx = 3, 2.4 V≤ V_CC≤ 3.6 V 0 25

(1) TI recommends powering AV_CCand DV_CCfrom the same source. A maximum difference of 0.3 V between AV_CCand DV_CCcan be tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See theSection 5.23threshold parameters for the exact values and further details.

(3) A capacitor tolerance of ±20% or better is required.

(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.

(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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2.0 1.8

8

0 12 20 25

SystemFrequency-MHz

Supply Voltage - V

The numbers within the fields denote the supported PMMCOREVx settings.

2.2 2.4 3.6

0, 1, 2, 3 0, 1, 2

0, 1 0

1, 2, 3 1, 2

1

2, 3 3

2

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

Figure 5-1. Frequency vs Supply Voltage

5.4 Active Mode Supply Current Into V

_CC

Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)

FREQUENCY (fDCO= fMCLK= fSMCLK) EXECUTION

PARAMETER V_CC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNIT

MEMORY

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

0 0.29 0.33 1.84 2.08

1 0.32 2.08 3.10

IAM, Flash Flash 3.0 V mA

2 0.33 2.24 3.50 6.37

3 0.35 2.36 3.70 6.75 8.90 9.60

0 0.17 0.19 0.88 0.99

1 0.18 1.00 1.47

IAM, RAM RAM 3.0 V mA

2 0.19 1.13 1.68 2.82

3 0.20 1.20 1.78 3.00 4.50 4.90

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing.

f_ACLK= 32768 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

5.5 Low-Power Mode Supply Currents (Into V

_CC

) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

–40°C 25°C 60°C 85°C

PARAMETER V_CC PMMCOREVx UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

2.2 V 0 69 93 69 93 69 93 69 93

Low-power mode 0⁽³⁾

I_LPM0,1MHz (4) µA

3.0 V 3 73 100 73 100 73 100 73 100

2.2 V 0 11 15.5 11 15.5 11 15.5 11 15.5

Low-power mode 2⁽⁵⁾

ILPM2 (4) µA

3.0 V 3 11.7 17.5 11.7 17.5 11.7 17.5 11.7 17.5

0 1.4 1.7 2.6 6.6

2.2 V 1 1.5 1.8 2.9 9.9

2 1.5 2.0 3.3 10.1

Low-power mode 3,

ILPM3,XT1LF 0 1.8 2.1 2.4 2.8 7.1 13.6 µA

crystal mode^{(6) (4)}

1 1.8 2.3 3.1 10.5

3.0 V

2 1.9 2.4 3.5 10.6

3 2.0 2.3 2.6 3.9 11.8 14.8

0 1.0 1.2 1.42 2.0 5.8 12.9

1 1.0 1.3 2.3 6.0

Low-power mode 3,

ILPM3,VLO VLO mode^{(7) (4)} 3.0 V 2 1.1 1.4 2.8 6.2 µA

3 1.2 1.4 1.62 3.0 6.2 13.9

0 1.1 1.2 1.35 1.9 5.7 12.9

1 1.2 1.2 2.2 5.9

ILPM4 Low-power mode 4^{(8) (4)} 3.0 V µA

2 1.3 1.3 2.6 6.1

3 1.3 1.3 1.52 2.9 6.2 13.9

I_LPM4.5 Low-power mode 4.5⁽⁹⁾ 3.0 V 0.10 0.10 0.13 0.20 0.50 1.14 µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low-side supervisor and monitors disabled (SVSL, SVML).

High-side monitor disabled (SVM_H). RAM retention enabled.

(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz, DCO setting = 1 MHz operation, DCO bias generator enabled.

(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK= 32768 Hz, fMCLK= fSMCLK= fDCO= 0 MHz (7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK= fVLO, fMCLK= fSMCLK= fDCO= 0 MHz (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz (9) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(19)

-25.0 -20.0 -15.0 -10.0 -5.0 0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C_A T = 85°CA

V = 3.0 V Px.y

CC

V_OH– High-Level Output Voltage – V I–Typical High-Level Output Current – mAOH

-8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0

0.0 0.5 1.0 1.5 2.0

T = 25°C_A T = 85°C_A V = 1.8 V Px.y

CC

V_OH– High-Level Output Voltage – V I–Typical High-Level Output Current – mAOH

0.0 5.0 10.0 15.0 20.0 25.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C_A

T = 85°CA

V = 3.0 V Px.y

CC

VOL– Low-Level Output Voltage – V I–Typical Low-Level Output Current – mAOL

0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

0.0 0.5 1.0 1.5 2.0

T = 25°C_A

T = 85°C_A V = 1.8 V

Px.y

CC

VOL– Low-Level Output Voltage – V I–Typical Low-Level Output Current – mAOL

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 5-3. Typical Low-Level Output Current vs Low-Level Figure 5-2. Typical Low-Level Output Current vs Low-Level

Output Voltage Output Voltage

Figure 5-5. Typical High-Level Output Current vs High-Level Figure 5-4. Typical High-Level Output Current vs High-Level

Output Voltage Output Voltage

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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

5.36 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

AVCC and DVCC are connected together,

AVCC Analog supply voltage AVSS and DVSS are connected together, 2.2 3.6 V

V_(AVSS)= V_(DVSS)= 0 V

V_(Ax) Analog input voltage range⁽²⁾ All ADC12 analog input pins Ax 0 AV_CC V

2.2 V 125 155

Operating supply current into

IADC12_A fADC12CLK= 5.0 MHz⁽⁴⁾ µA

AVCC terminal⁽³⁾ 3 V 150 220

Only one terminal Ax can be selected at one

C_I Input capacitance 2.2 V 20 25 pF

time

RI Input MUX ON-resistance 0 V≤ VAx≤ AVCC 10 200 1900 Ω

(1) The leakage current is specified by the digital I/O input leakage.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling capacitors are required. SeeSection 5.41andSection 5.42.

(3) The internal reference supply current is not included in current consumption parameter IADC12_A. (4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.

5.37 12-Bit ADC, Timing Parameters

PARAMETER TEST CONDITIONS V_CC MIN TYP MAX UNIT

For specified performance of ADC12 linearity

parameters using an external reference voltage or 0.45 4.8 5.0 AVCC as reference.⁽¹⁾

f_ADC12CLK ADC conversion clock For specified performance of ADC12 linearity 2.2 V, 3 V MHz

0.45 2.4 4.0

parameters using the internal reference.⁽²⁾ For specified performance of ADC12 linearity

0.45 2.4 2.7

parameters using the internal reference.⁽³⁾ Internal ADC12

f_ADC12OSC ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz

oscillator⁽⁴⁾

REFON = 0, Internal oscillator,

2.2 V, 3 V 2.4 3.1

ADC12OSC used for ADC conversion clock

t_CONVERT Conversion time µs

External f_ADC12CLKfrom ACLK, MCLK, or SMCLK, (5)

ADC12SSEL≠ 0

RS= 400Ω, R_I= 1000Ω, C_I= 20 pF,

t_Sample Sampling time 2.2 V, 3 V 1000 ns

τ = [R_S+ R_I] × C_I⁽⁶⁾

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with f_ADC12CLKmaximum of 5.0 MHz.

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC divided by 2.

(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(5) 13 × ADC12DIV × 1/f_ADC12CLK

(6) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) x (R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A

5.38 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage

PARAMETER TEST CONDITIONS V_CC MIN TYP MAX UNIT

1.4 V≤ dVREF ≤ 1.6 V⁽²⁾ ±2.0

EI Integral linearity error⁽¹⁾ 2.2 V, 3 V LSB

1.6 V < dVREF⁽²⁾ ±1.7

E_D Differential linearity error⁽¹⁾ ⁽²⁾ 2.2 V, 3 V ±1.0 LSB

dVREF≤ 2.2 V⁽²⁾ 2.2 V, 3 V ±1.0 ±2.0

E_O Offset error⁽³⁾ LSB

dVREF > 2.2 V⁽²⁾ 2.2 V, 3 V ±1.0 ±2.0

EG Gain error⁽³⁾ ⁽²⁾ 2.2 V, 3 V ±1.0 ±2.0 LSB

dVREF≤ 2.2 V⁽²⁾ 2.2 V, 3 V ±1.4 ±3.5

ET Total unadjusted error LSB

dVREF > 2.2 V⁽²⁾ 2.2 V, 3 V ±1.4 ±3.5

(1) Parameters are derived using the histogram method.

(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+– VR–, VR+< AVCC, VR–> AVSS.

Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100Ω and two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

(3) Parameters are derived using a best fit curve.

5.39 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

PARAMETER TEST CONDITIONS⁽¹⁾ V_CC MIN TYP MAX UNIT

ADC12SR = 0, REFOUT = 1 fADC12CLK≤ 4.0 MHz ±1.7

Integral linearity

EI 2.2 V, 3 V LSB

error⁽²⁾ ADC12SR = 0, REFOUT = 0 fADC12CLK≤ 2.7 MHz ±2.5

ADC12SR = 0, REFOUT = 1 f_ADC12CLK≤ 4.0 MHz –1.0 +1.5

Differential

E_D ADC12SR = 0, REFOUT = 1 f_ADC12CLK≤ 2.7 MHz 2.2 V, 3 V –1.0 +1.0 LSB

linearity error⁽²⁾

ADC12SR = 0, REFOUT = 0 f_ADC12CLK≤ 2.7 MHz –1.0 +2.5

ADC12SR = 0, REFOUT = 1 fADC12CLK≤ 4.0 MHz ±2.0 ±4.0

EO Offset error⁽³⁾ 2.2 V, 3 V LSB

ADC12SR = 0, REFOUT = 0 fADC12CLK≤ 2.7 MHz ±2.0 ±4.0

ADC12SR = 0, REFOUT = 1 f_ADC12CLK≤ 4.0 MHz ±1.0 ±2.5 LSB

E_G Gain error⁽³⁾ 2.2 V, 3 V

ADC12SR = 0, REFOUT = 0 f_ADC12CLK≤ 2.7 MHz ±1.5%⁽⁴⁾ VREF

ADC12SR = 0, REFOUT = 1 f_ADC12CLK≤ 4.0 MHz ±2 ±5 LSB

Total unadjusted

E_T 2.2 V, 3 V

error ADC12SR = 0, REFOUT = 0 fADC12CLK≤ 2.7 MHz ±1.5%⁽⁴⁾ VREF

(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+– VR–. (2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin.

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www.ti.com ADC12_A Introduction

28.1 ADC12_A Introduction

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator (MSP430F54xx (non-A only) – in other devices, separate REF module), and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent analog-to-digital converter (ADC) samples to be converted and stored without any CPU intervention.

ADC12_A features include:

• Greater than 200-ksps maximum conversion rate

• Monotonic 12-bit converter with no missing codes

• Sample-and-hold with programmable sampling periods controlled by software or timers

• Conversion initiation by software or timers

• Software-selectable on-chip reference voltage generation (MSP430F54xx (non-A only): 1.5 V or 2.5 V, all other devices: 1.5 V, 2.0 V, or 2.5 V)

• Software-selectable internal or external reference

• Up to 12 individually configurable external input channels

• Conversion channels for internal temperature sensor, AV

_CC

, and external references

• Independent channel-selectable reference sources for both positive and negative references

• Selectable conversion clock source

• Single-channel, repeat-single-channel, sequence (autoscan), and repeat-sequence (repeated autoscan) conversion modes

• ADC core and reference voltage can be powered down separately

• Interrupt vector register for fast decoding of 18 ADC interrupts

• 16 conversion-result storage registers

The block diagram of ADC12_A is shown in Figure 28-1. In MSP430F54xx (non-A only), the reference generator is located in the ADC12_A module itself. In other devices, the reference generator is located in the reference module, REF. See the REF module chapter and the device-specific data sheet for further details. Figure 28-1 shows the block diagram for devices that have the REF module available. Figure 28-2 shows the block diagram for the MSP430F54xx (non-A only) which does not incorporate the REF module.

733

SLAU208O – June 2008 – Revised May 2015 ADC12_A

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0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 INCHx

4

Sample and Hold

S/H

12-bit ADC Core VR- VR+

Convert 1 0

ADC12SREF2 0

A0 A1 A2 A3 A4 A5 A6 A7 VeREF+

VREF-/VeREF-

VREF+

11 10 01 00 AVCC

ADC12SREF1 ADC12SREF0 ADC12SR ADC12REFBURST

ADC12ON

SAMPCON

Sample Timer /4 ../1024 ADC12BUSY

0 1 ADC12ISSH

SHI

ADC12SHT1x ADC12MSC

Divider /1 .. /8

ADC12CLK ADC12DIVx

Ref_x

on Reference*

AVCC

1

00 01 10 11

ACLK MCLK SMCLK

ADC12OSC (see Note A)

ADC12SSELx

Sync

R

R AVCC

AVSS

Ref_x INCHx = 0Bh

- 16 x 8 Memory Control

- 00 01 10 11

Timer sources (see Note B) ADC12SHSx

ADC12SC

ADC12MCTL0

ADC12MCTL15 -

16 x 12 Memory

Buffer - ADC12MEM0

ADC12MEM15 4

CSTARTADDx

CONSEQx 1 0

ADC12SHP ADC12SHT0x A12 4

A13 A14 A15

:1 :4 0 1 ADC12PDIV REFOUT*

ADC12ENC 1.5/2.0/2.5 V REFMSTR*

ADC12REFOUT

1 0 REFVSELx*

REFMSTR*

ADC12REF2_5V

1 0 REFON*

REFMSTR*

ADC12REFON

1 0 AVSS

Temp.

Sensor* 1 0

REFTCOFF*

REFMSTR*

ADC12TCOFF

EN * Resides in REF module.

ADC12_A Introduction www.ti.com

A ADC12OSC refers to the MODCLK from the UCS. See theUCS chapterfor more information.

B See the device-specific data sheet for timer sources available.

Figure 28-1. ADC12_A Block Diagram (Devices With REF Module)

734 ADC12_A SLAU208O – June 2008 – Revised May 2015

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ESD Protection

R ~ 100 W ADC12MCTLx.0–3

Input Ax

N_ADC= 4095 ×Vin – V

R–

V – V

R+ R–

ADC12_A Operation www.ti.com

28.2 ADC12_A Operation

The ADC12_A module is configured with user software. The setup and operation of the ADC12_A is discussed in the following sections.

28.2.1 12-Bit ADC Core

The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory. The core uses two programmable and selectable voltage levels (V

R+

and V

R–

) to define the upper and lower limits of the conversion. The digital output (N

_ADC

) is full scale (0FFFh) when the input signal is equal to or higher than V

R+

. The digital output (N

ADC

) is zero when the input signal is equal to or lower than V

_R–

. The input channel and the reference voltage levels (V

_R+

and V

_R–

) are defined in the conversion-control memory. The conversion formula for the ADC result N

_ADC

is:

The ADC12_A core is configured by two control registers, ADC12CTL0 and ADC12CTL1. The core is enabled with the ADC12ON bit. The ADC12_A can be turned off when it is not in use to save power. With few exceptions, the ADC12_A control bits can be modified only when ADC12ENC = 0. ADC12ENC must be set to 1 before any conversion can take place.

28.2.1.1 Conversion Clock Selection

The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected. The ADC12_A source clock is selected using the predivider controlled by the ADC12PDIV bit and the divider using the ADC12SSELx bits. The input clock can be divided from 1 to 32 using both the ADC12DIVx bits and the ADC12PDIV bit. Possible ADC12CLK sources are SMCLK, MCLK, ACLK, and the ADC12OSC.

The ADC12OSC in the block diagram (see Figure 28-1) refers to the MODCLK 5-MHz oscillator from the UCS (see the UCS module for more information) which can vary with individual devices, supply voltage, and temperature. See the device-specific data sheet for the ADC12OSC specification.

The user must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation does not complete and the results are invalid.

28.2.2 ADC12_A Inputs and Multiplexer

The 12 external and 4 internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching (see Figure 28-3). The input multiplexer is also a T-switch to minimize the coupling between channels. Channels that are not selected are isolated from the ADC, and the

intermediate node is connected to analog ground (AV

_SS

) so that the stray capacitance is grounded to eliminate crosstalk.

The ADC12_A uses the charge redistribution method. When the inputs are internally switched, the switching action may cause transients on the input signal. These transients decay and settle before causing errant conversion.

Figure 28-3. Analog Multiplexer

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Start Sampling

Stop Sampling

Conversion Complete

SAMPCON SHI

t_sample t_convert

t_sync

13 × ADC12CLK Start

Conversion

ADC12CLK

The internal reference buffer also has selectable speed versus power settings. When the maximum conversion rate is below 50 ksps, setting ADC12SR = 1 reduces the current consumption of the buffer by approximately 50%.

28.2.4 Auto Power Down

The ADC12_A is designed for low-power applications. When the ADC12_A is not actively converting, the core is automatically disabled, and it is automatically reenabled when needed. The MODOSC is also automatically enabled when needed and disabled when not needed.

28.2.5 Sample and Conversion Timing

An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following:

• ADC12SC bit

• Up to three timer outputs (see the device-specific data sheet for available timer sources)

The ADC12_A supports 8-bit, 10-bit, and 12-bit resolution modes selectable by the ADC12RES bits. The analog-to-digital conversion requires 9, 11, and 13 ADC12CLK cycles, respectively. The polarity of the SHI signal source can be inverted with the ADC12ISSH bit. The SAMPCON signal controls the sample period and start of conversion. When SAMPCON is high, sampling is active. The high-to-low SAMPCON

transition starts the analog-to-digital conversion. Two different sample-timing methods are defined by control bit ADC12SHP, extended sample mode and pulse mode. See the device-specific data sheet for available timers for SHI sources.

28.2.5.1 Extended Sample Mode

The extended sample mode is selected when ADC12SHP = 0. The SHI signal directly controls SAMPCON and defines the length of the sample period t

sample

. When SAMPCON is high, sampling is active. The high- to-low SAMPCON transition starts the conversion after synchronization with ADC12CLK (see Figure 28-4).

Figure 28-4. Extended Sample Mode

28.2.5.2 Pulse Sample Mode

Set ADC12SHP = 1 to select the pulse sample mode. The SHI signal is used to trigger the sampling timer.

The ADC12SHT0x and ADC12SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period t

sample

. The sampling timer keeps SAMPCON high after

synchronization with AD12CLK for a programmed interval t

_sample

. The total sampling time is t

_sample

plus t

_sync

(see Figure 28-5).

The ADC12SHTx bits select the sampling time in 4× multiples of ADC12CLK. ADC12SHT0x selects the sampling time for ADC12MCTL0 to ADC12MCTL7. ADC12SHT1x selects the sampling time for

ADC12MCTL8 to ADC12MCTL15.

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28.2.10 ADC12_A Interrupts

The ADC12_A has 18 interrupt sources:

• ADC12IFG0 to ADC12IFG15

• ADC12OV, ADC12MEMx overflow

• ADC12TOV, ADC12_A conversion time overflow

The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set. The ADC12OV condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read. The ADC12TOV condition is generated when another sample-and- conversion is requested before the current conversion is completed. The DMA is triggered after the conversion in single-channel conversion mode or after the completion of a sequence of channel conversions in sequence-of-channels conversion mode.

28.2.10.1 ADC12IV, Interrupt Vector Generator

All ADC12_A interrupt sources are prioritized and combined to source a single interrupt vector. The interrupt vector register ADC12IV is used to determine which enabled ADC12_A interrupt source requested an interrupt.

The highest-priority enabled ADC12_A interrupt generates a number in the ADC12IV register (see register description). This number can be evaluated or added to the program counter (PC) to automatically enter the appropriate software routine. Disabled ADC12_A interrupts do not affect the ADC12IV value.

Any access, read or write, of the ADC12IV register automatically resets the ADC12OV condition or the ADC12TOV condition if either was the highest-pending interrupt. Neither interrupt condition has an

accessible interrupt flag. The ADC12IFGx flags are not reset by an ADC12IV access. ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMx register or may be reset with software.

If another interrupt is pending after servicing of an interrupt, another interrupt is generated. For example, if the ADC12OV and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register, the ADC12OV interrupt condition is reset automatically. After the RETI instruction of the interrupt service routine is executed, the ADC12IFG3 generates another interrupt.

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ADC12_A Registers www.ti.com

28.3.1 ADC12CTL0 Register ADC12_A Control Register 0

Figure 28-13. ADC12CTL0 Register

15 14 13 12 11 10 9 8

ADC12SHT1x ADC12SHT0x

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0

ADC12MSC ADC12REF2_5 ADC12REFON ADC12ON ADC12OVIE ADC12TOVIE ADC12ENC ADC12SC

V

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

Can be modified only when ADC12ENC = 0

Table 28-4. ADC12CTL0 Register Description

Bit Field Type Reset Description

15-12 ADC12SHT1x RW 0h ADC12_A sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15.

11-8 ADC12SHT0x RW 0h ADC12_A sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7.

0000b = 4 ADC12CLK cycles 0001b = 8 ADC12CLK cycles 0010b = 16 ADC12CLK cycles 0011b = 32 ADC12CLK cycles 0100b = 64 ADC12CLK cycles 0101b = 96 ADC12CLK cycles 0110b = 128 ADC12CLK cycles 0111b = 192 ADC12CLK cycles 1000b = 256 ADC12CLK cycles 1001b = 384 ADC12CLK cycles 1010b = 512 ADC12CLK cycles 1011b = 768 ADC12CLK cycles 1100b = 1024 ADC12CLK cycles 1101b = 1024 ADC12CLK cycles 1110b = 1024 ADC12CLK cycles 1111b = 1024 ADC12CLK cycles

7 ADC12MSC RW 0h ADC12_A multiple sample and conversion. Valid only for sequence or repeated modes.

0b = The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert.

1b = The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed.

6 ADC12REF2_5V RW 0h ADC12_A reference generator voltage. ADC12REFON must also be set. In devices with the REF module, this bit is only valid if the REFMSTR bit of the REF module is set to 0. In the F54xx devices (non-A), the REF module is not available.

0b = 1.5 V 1b = 2.5 V

5 ADC12REFON RW 0h ADC12_A reference generator on. In devices with the REF module, this bit is only valid if the REFMSTR bit of the REF module is set to 0. In the F54xx devices (non-A), the REF module is not available.

0b = Reference off 1b = Reference on

4 ADC12ON RW 0h ADC12_A on

0b = ADC12_A off 1b = ADC12_A on