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Bibliografia [1] Donald C.Larson, “High speed direct digital synthesis techniques and applications”

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Bibliografia

[1] Donald C.Larson, “High speed direct digital synthesis techniques and applications” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium,

1998. Technical Digest 1998., 20th Annual, Vol., Iss., 1-4 Nov 1998 Pages:209-212.

[2] Dorin Emil Calbaza, Yvon Savaria, “Jitter model of direct digital synthesis clock generators” Circuits and Systems, 1999. ISCAS '99. Proceedings of

the 1999 IEEE International Symposium on, Vol.1, Iss., Jul 1999 Pages:1-4 vol.1.

[3] H. Nosaka, T. Nakagawa, A. Yamagishi, “A fast frequency switching synthesizer with a digitally controlled delay generator” IEICE Trans

Fundamentals, Vol. E81-A,No. 7 july 1998.

[4] A. Heiskanen, A. Mantyniemi, T. Rahkonen, “A 30 MHZ DDS clock generator with sub-ns time domain interpolator and -50 dBc spurios level”

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, Vol.4, Iss., 6-9 May 2001 Pages:626-629 vol. 4.

[5] A. Calleri, “Progetto di un generatore di ritardo ad alta risoluzione per la sintesi digitale diretta di frequenza” Tesi di laurea, Corso di Laurea in Ing.

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[6] F. Baronti, D. Lunardini, “Non linearità dei TDC: Analisi, Tecniche di correzione e progetto di linea di ritardo a calibrazione digitale”, Tesi di

Laurea, Corso di Laurea in Ing. Elettronica, Università degli Studi di Pisa, A.A 1999/2000.

[7] F: Baronti, L. Lunardini, L. Fanucci, R. Roncella, R. Saletti, “A high-resolution DLL-based digital-to-time converter for DDS applications”

Frequency Control Symposium and PDA Exhibition, 2002. IEEE International, Vol., Iss., 2002 Pages: 649- 653.

[8] A.R. Cooper, “Parallel architecture modified Booth multiplier” Circuits,

Devices and Systems, IEE Proceedings G [see also IEE Proceedings-Circuits, Devices, and Systems], Vol.135, Iss.3, Jun 1988 Pages:125-128.

[9] S.M. Sait, A.A. Farooqui, G.F. Beckhoff, “A novel tecnique for fast multiplication” Computers and Communications, 1995. Conference

Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on, Vol., Iss., 28-31 Mar 1995 Pages:109-114.

[10] M. Roorda, “Method to reduce the sign bit extension in a multiplier that uses the modified Booth algorithm”, Electron. Lett, 19986, 22, (20), pp.

1061-1062.

[11] Luigi Rizzo, “L’aritmetica dei calcolatori”, Sevizio Editoriale

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