In this chapter the behavior of a three-phase converter will briefly discussed. Its circuit is shown in figure 6.1 The multiphasic technique is commonly used in order to increase

(1)

Chapter 6 Three-Phase Converter

In this chapter the behavior of a three-phase converter will briefly discussed. Its circuit is shown in figure 6.1 The multiphasic technique is commonly used in order to increase

V

_in

L

_ind

1 2 3

2 1 3

M

md

M

bu

M

bd

M

mu

2 1

3

2 1 3

2 1

3

C

²

C

1

V

out

Figure 6.1: Topology of a three phases converter

the power density and to reduce the output ripple. By using this method, the effective output ripple frequency can be increased without increasing the switching frequency of the switching device. The progress of the current in each inductance is shown in figure 6.2, where i

ind

is the sum of the currents of every inductance. As depicted, i

ind

ripple is smaller than i

ind1

, i

ind2

, i

ind3

, hence the current ripple through the output capacitor and the current ripple through the load resistance are smaller than the current ripples of the single phase converter. Moreover, the current inductance ripple is depend out on the duty-cycle (d).

Figure 6.3 shows the relation between d and ˜ IL

ind

/V

in

·T for the single phase, the two phase and the three phase converter, where ˜ I is the peak to peak value of i

ind

. Figure 6.3 is

51

(2)

T t t

2 3 T T

3 i

ind1

i

ind2

i

ind3

t t i

ind

Figure 6.2: Progress of the currents through each capacitor and their sum

depicted neglecting all losses, and considering the load current constant.

0 0.2 0.4 0.6 0.8 1

0 0.05 0.1 0.15 0.2 0.25 0.3

L˜ Iind V·Tin

d single phase

two phase

three phase

Figure 6.3: Inductance current ripple as a function of the duty cycle

6.1 Three-Phase Step-down Converter

As in chapter 4 a relationship between V

load

and d is found. First of all, it is easy to recognize

that the converter topology is quite similar to the mono-phase. The way to proceed is equal

to section 4.1.1, considering the resistive model of the switches. Regarding picture 6.4, it is

possible to write the KV E and find the voltage across one of the inductors at the turn −on

and at the turn−off, considering the current flowing in the inductance three times smaller

(3)

than the load current. The results also are similar:

V

_b

L

_ind

C

²

C

1

V

_in

1 2 3

M

₁

M

₂

M

₃

D

1

D

2

D

3

Figure 6.4: Three phase converter step-down mode

V

load

= V

in

·d − V

^{f d}

·(1 − d)

b·d + a·(1 − d) (6.1)

d = V

load

·a + V

^{f d}

V

in

− V

^load

·(b − a) + V

^{f d}

(6.2) but a and b are not the same:

a = R

ond

+ R

ind

+ 3·R

^load

3·R

^load

b = R

onm

+ R

ind

+ 3·R

^load

3·R

^load

The peak-to-peak current of every inductance is:

∆I

ind

= − (V

in

− b·V

^load

)·d·T L

ind

(6.3)

6.2 Three-Phases Step-up Converter

Like the step-down, the relation among V

in

= V

load

is found. Pertaining to section 4.3.1, the equation across one of the inductance is written and the results are:

V

load

= V

in

− V

^{f d}

·(1 − d)

(1 − d)

²

+ (c − e)·d + e ·(1 − d) (6.4) where:

c = R

onm

+ R

ind

3·R

^load

e = R

ond

+ R

ind

3·R

^load

(4)

V

_out

=V

_load

C

²

C

1

V

_in

M

₁

M

₂

M

₃

L

_ind

1 2 3

D

1

D

2

D

₃

Figure 6.5: Three phases converter step-up mode

The reverse formula also is as equations 4.47 and 4.48

∆I

ind

= −

"

V

in

− c· V

load

1 − d

# d·T L

ind

(6.5)

6.3 Simulations

Simulations are run with the following dates:

• Capacitor battery side C

¹

modeled by a capacitance C

1

= 8800µF in series with a resistance R

_c1

= 12.75mΩ

• Main inductance L

^ind1

= L

_ind2

= L

_ind3

modeled by an inductance L

ind

= 30µH in series with a resistance R

ind

= 5.17mΩ

• capacitor motor side C

²

modeled by a capacitance C

2

= 5000µF in series with a resistance R

c1

= 0.6mΩ

• automotive MOSFETS IRF model IRF P 2907

Simplorer was used as simulation software, and only the motoring step-up and the braking

step-down modes of operation were investigated.

(5)

6.3.1 Braking Step-down

The simulations were run only for d = 1/3 and for d = 1/2, which give the minimum and the maximum value of the ripple respectively.

6.3.1.1 d = 1/3

In figure 6.6, 6.7, 6.16 and 6.9 the progress of the output capacitor current, the current through every inductance, their sum, and load voltage and current are depicted. The simulation was run using the following data:

• V

ⁱⁿ

= 39V

• d = 1/3

• R

^load

= 0.12Ω

The figures show that the simulation results are different from theoretic considerations.

Looking at fig. 6.3 for d = 1/3, the peak-to-peak inductance current should be zero, but simulation gives ∆I = 0.25A. The differences may be due to neglecting resistances, and to switching losses.

6.3.1.2 d = 1/2

In figure 6.10, 6.19, 6.12 and 6.13 the progress of the output capacitor current, the current through every inductance, their sum, and load voltage and current are depicted. The simulation was been run using the following data:

• V

ⁱⁿ

= 26V

• d = 1/2

• R

^load

= 0.12Ω

In this case the simulation results are more similar to theoretic considerations. Looking at

fig. 6.3 for d = 1/2, peak-to-peak inductance current should be 0.085·T·V

ⁱⁿ

/L

ind

= 0.74, and

the simulation gives ∆I = 0.7A. In this case the differences may be also due to neglecting

resistances, and the switching losses.

(6)

4.97 4.975 4.98 4.985 4.99 4.995 5 x 10⁻³ 26

28 30 32 34 36 38

t

i iind1

iind2

iind3

Figure 6.6: Progress of the current through every inductance

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³ 105.8

105.9 106 106.1 106.2 106.3 106.4 106.5 106.6 106.7

iload,iind(A)

t

iload

iind

Figure 6.7: Progress of i

ind

and i

load

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³

−0.4

−0.3

−0.2

−0.1 0 0.1 0.2 0.3 0.4

iC2(A)

t (s)

Figure 6.8: Progress of i

C2

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³ 12.748

12.749 12.75 12.751 12.752 12.753 12.754 12.755 12.756 12.757

vload(V)

t (s)

Figure 6.9: Progress of V

load

6.3.2 Motoring Step-up

The simulations were run only for d = 2/3 and for d = 1/2 that give the minimum and the maximum value of the ripple respectively.

6.3.2.1 d = 2/3

In figure 6.14, 6.15, 6.16 and 6.17 the progress of the output capacitor current, the current through every inductance, their sum, and load voltage and current are depicted. The simulation was run using the following data:

• V

ⁱⁿ

= 12V

• d = 2/3

• R

^load

= 0.323Ω

(7)

4.975 4.98 4.985 4.99 4.995 5 x 10⁻³ 30

31 32 33 34 35 36 37 38

t

i

iind1

iind2

iind3

Figure 6.10: Progress of the current through every inductance

4.965 4.97 4.975 4.98 4.985 4.99 4.995 5 x 10⁻³ 103.6

103.7 103.8 103.9 104 104.1 104.2 104.3 104.4 104.5 104.6

iload,iind(A)

t

iload

iind

Figure 6.11: Progress of i

ind

and i

load

4.965 4.97 4.975 4.98 4.985 4.99 4.995 5 x 10⁻³

−0.4

−0.3

−0.2

−0.1 0 0.1 0.2 0.3 0.4

iC2(A)

t (s)

Figure 6.12: Progress of i

C2

4.965 4.97 4.975 4.98 4.985 4.99 4.995 5 x 10⁻³ 12.483

12.484 12.485 12.486 12.487 12.488 12.489 12.49 12.491 12.492 12.493

vload(V)

t (s)

Figure 6.13: progress of V

load

The figure shows that the simulation results are different from theoretic considerations.

Looking at fig. 6.3 in fact for d = 2/3, the peak-to-peak inductance current should be zero, but simulation gives ∆I = 0.18A. The differences of course may be due to neglecting resistances, switching resistance, and furthermore the off-delay time and the current rise also has a large effect. In this case the current flowing through the M

bd

MOSFETS, is equal to zero during the off-delay time, hence the output current capacitor has a peak during this time 6.16 and this makes the output voltage ripple larger.

6.3.2.2 d = 1/2

In figure 6.18, 6.19, 6.20 and 6.21, the progress of the output capacitor current, the current through every inductance, their sum, and load voltage and current are depicted. The simulation was run using the following data:

• V

ⁱⁿ

= 12V

(8)

4.97 4.975 4.98 4.985 4.99 4.995 5 x 10⁻³ 106

107 108 109 110 111 112 113 114

t

i

iind1

iind2

iind3

Figure 6.14: Progress of the current through every inductance

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³ 328.5

328.6 328.7 328.8 328.9 329 329.1 329.2 329.3 329.4 329.5

iind(A)

t

Figure 6.15: Progress of i

ind

and i

load

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³

−0.4

−0.3

−0.2

−0.1 0 0.1 0.2 0.3 0.4

iC2(A)

t (s)

Figure 6.16: Progress of i

C2

4.97 4.975 4.98 4.985 4.99 4.995

x 10⁻³ 33.28

33.3 33.32 33.34 33.36 33.38 33.4 33.42 33.44 33.46

vload(V)

t (s)

Figure 6.17: Progress of V

load

• d = 1/2

• R

^load

= 0.323Ω

In this case the simulation results are more similar to theoretical considerations. Looking at

fig. 6.3 in fact for d = 1/2, the peak-to-peak inductance current should be 0.085·T·V

ⁱⁿ

/L

ind

=

0.34, and the simulation gives ∆I = 0.5A. In this case the differences may also be due to

neglecting resistances and to switching losses.

(9)

4.97 4.975 4.98 4.985 4.99 4.995 5 x 10⁻³ 82

83 84 85 86 87 88 89

t

i

iind1

iind2

iind3

Figure 6.18: Progress of the current through every inductance

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³ 254.5

254.6 254.7 254.8 254.9 255 255.1 255.2 255.3 255.4 255.5

iind(A)

t

Figure 6.19: Progress of i

ind

and i

load

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³

−40

−20 0 20 40 60 80

iC2(A)

t (s)

Figure 6.20: Progress of i

C2

4.97 4.975 4.98 4.985 4.99 4.995 5

x 10⁻³ 26.98

27 27.02 27.04 27.06 27.08

vload(V)

t (s)

Figure 6.21: Progress of V

load