List of Figures viii

Contents

Index vii

List of Figures viii

Abstract viii

Introduction 1

1 Modelling methodologies, description languages and tools 7 1.1 Principles of Complex Mixed-Signal Design . . . . 7 1.1.1 Bottom-Up approach . . . . 7 1.1.2 Top-Down approach . . . . 8 1.2 System-level modelling and verification:

a MATLAB Simulink

approach . . . . 9 1.3 Hardware Description Languages (HDLs) for Analogue and

Mixed-Signals (AMS) . . . 11 1.3.1 VHDL-AMS . . . 12 1.3.2 Verilog-AMS . . . 12 1.4 Merging digital and analogue worlds in a single environment . 13 1.4.1 Analogue sensitivity to digital events . . . 13 1.4.2 Digital sensitivity to analogue events . . . 13 1.4.3 Interface elements . . . 15 1.5 Trading-off abstraction level, accuracy, speed and modelling

effort . . . 16

2 Analysis and Modelling of a Physical Layer 19

2.1 Overview of MIPI M-PHY . . . 20

2.2 Description of the architecture of a PHY . . . 22

2.3 PLL . . . 22

2.3.1 Structure and fundamentals equations . . . 22

2.3.2 Phase Frequency Detector, Charge Pump and the Loop Filter . . . 23

2.3.3 Crystal Reference and Voltage Controlled Oscillator (VCO) . . . 27

2.3.4 Divider . . . 28

2.3.5 Loop Characteristics . . . 30

2.3.6 Noise insertion and response analysis . . . 31

2.4 TRANSMITTER . . . 37

2.4.1 Basic scheme . . . 37

2.4.2 Output Stage . . . 37

2.4.3 Pre-Driver . . . 39

2.4.4 Control signal generators . . . 41

2.5 CHANNEL . . . 42

2.5.1 Load Configurations . . . 43

2.5.2 Mixed-mode Scattering (S) Parameters . . . 44

2.5.3 Time-domain Simulink

model of a 4-ports network . . 50

2.6 RECEIVER . . . 52

2.6.1 Amplifier . . . 53

2.6.2 Samplers and Bit-Estimators . . . 54

3 Performances of a Physical Layer: the models in action 60 3.1 Jitter in High Speed Serial Interfaces . . . 60

3.1.1 Deterministic Jitter . . . 61

3.1.2 Random Jitter . . . 65

3.1.3 Jitter Metrics . . . 66

3.2 Jitter in a PLL . . . 67

3.3 Eye Diagram . . . 70

3.4 Overall Jitter in a Physical Layer . . . 73

3.4.1 Dual-Dirac Jitter Model . . . 74

3.4.2 Tail fitting . . . 75

3.4.3 Bit Error Rate (BER) computation . . . 80

3.4.4 Timing budget . . . 83

3.5 Modelling jitter insertion in communication interfaces . . . 86

4 Improving the performances toward higher data rates 89 4.1 Study of the performances using the Worst-Case Eye Width Analysis . . . 89

4.2 Principle of equalization . . . 91

4.3 Types of equalization . . . 92

4.4 Transmitter Finite Impulse Response (FIR) Equalization . . . 93

Conclusion and future developments 108

Acknowledgements 113

Acknowledgements - italian version 115

Bibliography 119

List of Figures

1 MIPI interfaces in a Mobile Platform [1] . . . . 2

2 Different types of bug in a design flow [3] . . . . 3

1.1 Digital, analogue continuous-time and analogue discrete-event signals [4] . . . 11

1.2 Across and through variables at a HDL-AMS port . . . 12

1.3 Digital-to-analogue synchronization [4] . . . 14

1.4 Analogue-to-digital synchronization [4] . . . 14

1.5 Characteristic of an electrical-to-logic connect module [4] . . . 15

1.6 Conceptual illustration of the trade-off among simulation run- time and accuracy for of each implementation methodology [5] . . . 16

1.7 Conceptual illustration of the trade-off among simulation run- time and the effort required by each implementation method- ology [5] . . . 17

2.1 Architecture of a generic High Speed Serial Interface . . . 19

2.2 Block diagram of a MPHY-based interface . . . 20

2.3 Architecture of the M-PHY LINK [2] . . . 21

2.4 Block diagram of the PLL model . . . 23

2.5 Simulink

top level of the PLL model . . . 24

2.6 Illustration of the working principle of a Phase Detector. . . . 24

2.7 Simulink

model of a Phase Frequency Detector . . . 25

2.8 Simulink

model of a Charge Pump with an Integrated Loop Filter . . . 25

2.9 Simulink

model of a Voltage Controlled Oscillator (VCO) . . 28

iv

2.10 Simulink

model of the frequency divider . . . 29

2.11 Real phase noise of a crystal oscillator in frequency domain [9] 32 2.12 Piece-wise linear approximation of a real phase noise [9] . . . . 32

2.13 Simulink

model of the Phase Noise samples generator . . . . 33

2.14 GUI for the specification of the Phase Noise frequency profile . 33 2.15 PLL Phase noise curves and Transfer Functions: MATLAB simulation . . . 34

2.16 PLL VCO’s input control voltage transient simulation . . . 36

2.17 PLL VCO’s instantaneous frequency . . . 36

2.18 Block diagram of the transmitter . . . 37

2.19 Representation of the topology of the output stage . . . 38

2.20 Examples of control of the output stage . . . 38

2.21 Simulink

implementation of the output stage . . . 39

2.22 Scheme of the behavioural model of the PreDriver block . . . 40

2.23 Simulink

implementation of the PreDriver block . . . 40

2.24 Signalling scheme: PWM bit ‘0’, PWM bit ‘1’, NRZ bit ‘0’, NRZ bit ‘1’ . . . 41

2.25 Generation of PWM signals: Simulink

block . . . 41

2.26 HS-G1B comparison: Simulink

versus transistor-level circuit simulation results . . . 42

2.27 Representation of the real connections among a Transmitter and a Receiver through a Channel . . . 44

2.28 ‘Pi’ load configuration in a differential channel . . . 44

2.29 Touchstone

file example [10] . . . 45

2.30 Representation of the stimuli configuration in a 4-ports network 46 2.31 Superposition principle: only one source acts . . . 47

2.32 Simulink

model of a 4-ports network . . . 51

2.33 Simulink

structure of an auto-generated zero-pole filter cas- cade that represents a custom transfer function . . . 52

2.34 Simulink

linear approximation of a differential-mode inser- tion loss . . . 52

2.35 Time simulation of a square-wave that propagates through a

Simulink

channel model . . . 53

2.36 Sampler sub-block for the PWM mode . . . 55 2.37 Illustration of the behaviour of PWM sampler block and MAT-

LAB simulated waveforms . . . 55 2.38 Basic scheme of the sensing block for the estimation of the bit

value . . . 56 2.39 Working principle of the PWM receiver . . . 56 2.40 Simulink

plots of the PWM receiver in action . . . 57 2.41 Simulink

plots of an error condition in the PWM receiver . . 58 2.42 Simulink

model of the elaboration block of the PWM receiver 58 3.1 Various types of jitter in a clock waveform [20] . . . 61 3.2 MATLAB plots of a single-bit input pulse, channel pulse re-

sponse and output pulse [20] . . . 63 3.3 ‘Cursors’ localization in the pulse at the output of the channel

[20] . . . 63 3.4 Representation of bit-stream as a sum of pulses[20] . . . 63 3.5 MATLAB plots of the bit-stream splitting into sum of pulses[20] 64 3.6 Calculation of the k -th cycle jitter . . . 67 3.7 k-cycle jitter in the output waveform resulting from the sim-

ulation of the Simulink model (Phase noise Mask PN3) . . . . 68 3.8 k -cycle jitter in the output waveform resulting from the sim-

ulation of the Simulink model (Phase noise Mask PN6) . . . . 69 3.9 Example of Eye Diagram for a NRZ High Speed signal . . . . 70 3.10 Toward a 3D Eye Diagram: partitioning of the voltage axis . . 71 3.11 3D Eye Diagram for a NRZ High Speed signal . . . 72 3.12 Zoom on the left crossing points area in a 3D Eye Diagram . . 72 3.13 Histogram of the zero-level crossing points in an Eye diagram 73 3.14 Dual-Dirac Jitter Model . . . 75 3.15 Identification of the best-fit sigma in a generic total jitter his-

togram . . . 76 3.16 Right-side histogram of the zero-level crossing points in an Eye

diagram . . . 76

3.17 Left-side histogram of the zero-level crossing points in an Eye

diagram . . . 77

3.18 Tail-Fitting of the right-side histogram . . . 79

3.19 Tail-Fitting of the left-side histogram . . . 79

3.20 Logarithmic scale BER Bathtub Graph . . . 84

3.21 Values of α(BER) versus variation of the link’s target BER . 85 3.22 Identification of the jitter contribution in the eye histogram . . 86

3.23 Time evolution of the sum of independent random values . . . 87

4.1 Principle of equalization technique [23] . . . 92

4.2 Noise enhancement in a receiver linear equalization [23] . . . . 93

4.3 Structure of a finite impulse response FIR filter [23] . . . 94

4.4 Scheme of the Transmitter with a FFE Current Steering Stage 97 4.5 Adjustment of ideal FIR taps on the target current-DAC res- olution . . . 97

4.6 Study of the trade-off between percentage improvement in Eye Aperture, resolution of the current DAC and number of taps for a NRZ stream @ 5 GHz . . . 99

4.7 Study of the trade-off between percentage improvement in Eye Aperture, resolution of the current DAC and number of taps for a NRZ stream @ 6 GHz . . . 100

4.8 Study of the trade-off between percentage improvement in Eye Aperture, resolution of the current DAC and number of taps for a NRZ stream @ 7 GHz . . . 100

4.9 Study of the trade-off between percentage improvement in Eye Aperture, resolution of the current DAC and number of taps for a NRZ stream @ 8 GHz . . . 101

4.10 Comparison of an equalized Eye diagram versus the non-equalized version @ 5 GHz (best trade-off parameters) . . . 101

4.11 Comparison of an equalized Eye diagram versus the non-equalized @ 8 GHz (best trade-off parameters) . . . 102

4.12 Screenshot of the waveform at the output of the VHDL-AMS

model of an equalized transmitter . . . 102