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Class-E current-driven center-tapped low dv/dt rectifierIAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting

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CLASS-E

CURRENT-DRIVEN

CENTER-TAPPED

LOW dv/dt

RECTIFIER

M. Bartoli, A. Reatti, Member, IEEE University of Florence, Department of Electronic Engineering Via di S. Marta, 3, 50139 Florence, Italy Phone: (39)(55)4796-389 and Fax: (39)(55)494569 E

-

Mail:

[email protected]

M. K. Kazimierczuk, Senior Member, IEEE Wright State University,

Department of Electrical Engineering Dayton, Ohio 45435

Phone: ( 5 13)873-5059 and Fax: (5 13)873-5009 E

-

Mail: MKAZIM@VAL,HALLA.CS.WGHT.EDU

Abstract - An analysis for a Class E current-driven center-tapped low dddt rectifier taking into account the transfornier leakage inductances is given along with experimental verifications. The rectifier diodes turn on and off at low ddtlt. This results in low switching noise and low switching losses. Diode parasitic capacitances do not adversely affect the circuit operation. The absolute value of &+It is limited at diode turn-off, reducing the reverse recovery current. The circuit is operated a t a low output voltage ripple and, therefore, at a low power loss in the equivalent series resistance (ESR) of the filter capacitor. Experimental tests were performed for a rectifier circuit operated a t a n output power of Po = 60 W, an minimum frequency o f f = 500 kHz, and a n output voltage of Vo = 3.3 V.

The theoretical and the experimental results are in good agreement. Experimental measurements demonstrate that the rectifier is suitable for high-power density, high-frequency applications that requires low-output voltages and high-currents.

I. INTRODUCTION

The increasing demand for small-volume light-weight power supplies has necessitated the development of high-frequency high-efiiciency power converter circuits. This can be achieved if switching losses are eliminated. In class E rectifiers [ 11-[7], zero-voltage turn on of the diode is achieved. Morcover, the diodcs turn on and off at low dv/dr resulting in low switching noise. Therefore, tlicsc rcctificrs can be operated at high switcliing frequencies with a nearly constant efficiency over a wide load range [4]-[6]. In the class E current-driven center-tappcd rectifier, the output voltage ripple is drastically reduced, the average current through each diode is one-half of the output current, and a lowcr volume transformer than in the class E full-wave rectifier [7] can be used. As a result, the class E current-driven center-tapped rectifier is suitable for high power-density applications at high-output currents, e.g., higher than 10 A and low-output voltages, e.g., 3.3 V or 5 V,

which are the standard supply voltages of advanced VLSI circuits. Moreover, Class E reclifiers can be used in combination with class D and class E resonant inverters to build high-frequency dc-dc convcrters [8] - [2 I].

The purpose of this paper is to present an analysis and experimental results for a class E current-driven center-tapped low d d d f rectifier. The rectifier was tested on a 60 W power supply operated at a line ac voltage ranging from 75 to 275 VrjjiS, an output current varying from 1.8 to 18 A, and an output voltage J'o = 3.3 V regulated over the entire line voltage

and load current ranges. The nominal operating frequency of the converter circuit was

f

= 500 kHz. A maximum elliciency

11 = 80 % was achieved for the entire power supply at the maximum load and an ac input voltage VI,.,,,, = 220 V.

11. CIRCUIT DESCRIPTION

A schematic circuit of the class E current-driven center-tapped low dv/dt rectifier and its model are shown in Figs. l(a) and (b), respectively.

C I .

Ah

I = 1, sin

" 4 t l

wwl

Y + V 0 ' I

+

h

' 0 9 4 V 0 c2

@I

Fig. 1. Class E current-driven center-tapped low dv/dr rectifier. a) Scheinatic circuit. b) Model of the rectifier.

The rectifier consists of two diodes D, and D,, two capacitors C, and C,, a single-pole low-pass output filter C R , and a center-tapped transformer with a turns ratio n.

Resistor R, is the dc load resistance. The diode parasitic

capacitances are absorbed into Capacitances C, and C,

connected in parallel with the diodes. The entire leakage flux

of the transformer has been t'aken into account by means of two

(2)

leakage inductances L , and

L ,

on the secondary side. L,,, is the tiiagnetizing inductance placed

on

the primary side of the transformer.

The transformer primary side is supplied by sinusoidal current source # l w t <

4

+ 2nD ON

# +

2 7 r D S w t

#

+

7r ON 1-t 7rS w t

1 +

7 r + 27rD OFF i = I,,, sin w t (1) OFF ON ON where I,,, and w = 2 j are the amplitude and the angular

frequency of the current, respectively.

111. PRINCIPLE OF OPERATION

The rectifier circuit can be operated at an on duty cycle of each diode D ranging from 0 to 1 and goes through four

topological configurations during one switching period T = I / J : These topological modes are defined by the diode states as given in Table I.

TABLE I.

RECTIFIER DIODE STATES.

I

4

+ 7r+ 2 d S w t

#

-t 27r

I

q5+ 7 r + 2 7 r D S o t

#

+ 27r

I

ON

I

ON

]I

The current and voltage waveforms for tlie rectifier operated at 0 < D

<

0.5 and 0.5 < D I 1 are shown in Figs. 2(a) and (b), respectively.

A. Operation for 0 < D 10.5

The first topological mode begins at wt =

#,

when voltage

VD] across diode D, reaches zero turning diode D,

on.

Actually, D, turns on when vD, reaches the threshold voltage

Vr, e.g., Vr = 0.4 V for Schottky diodes. During this time interval, current i , of the upper secondary winding flows through D,. Diode D, is off and its voltage waveform is shaped by the shunt capacitor C,, according to i,, = C, dv,/dt. The first mode ends at wt = q5 + 2rD, when current io, reaches zero, turning D l off.

During the second topological mode both D, and

D,

are OFF. Current i, flows through capacitor C,, voltage vDl = vcl

is shaped according to icl

7

C, dvcl / dt. Since the capacitor current is zero at the beginning of tlie second topological mode, the derivative of vD, is also zero at w t =

4

+ 2 d . After diode D , turn-off, voltage vDl slowly decreases because icI is negative. Since i,, is positive, voltage vD2 increases and reaches the diode threshold voltage at w t =

4

+ G turning diode D, on. This ends the second mode.

The third topological mode begins at w t =

#

+ 7r, when

diode

D,

turns

on

and ends at

w

t =

4

+

7r

+

2 d , when it turns off. During tliis time interval, the lower secondary winding current iz flows through diode D,. The waveform of

the voltage across diode D, and capacitor C, is still shaped by tlie current through C,. Therefore, it decreases, reaches its

minimum value VDhf when tcl is zero, and tllcil increases wlien icI is positive.

The fourth mode begins, when current iD2 reaches zero and diode D, turns off. As in the first topological mode, C, shapes the voltage w,aveform of D,. Therefore, voltage vD2 slowly decreases from zero because ic2 is zero at w t =

4

+

7r + 27rD. The current tlhrough capacitor C, is positive and, therefore,

voltage vD, increases. Diode D , turns on at U t =

#

+ 27r, when

vD, reaches the threshold voltage. This ends the fourth topological mode and the switching period.

B. Operatioiijor 0.5 D 1 1

Tlie first and the third topological modes arc idelltical for the first and tlie third topological modes of the rectifier operated at 0 <

D

5 0.5. The second topological mode begins at

ot =

#

+

d

when diode D, turns on and ends at wt =

4

+ 2nB when current i , decreases to zero turning off diode D,. The fourth topological modes begins at

wt =

4

+ 7 r + 2nD when diode D, turn on and ends at

wt =

#

+ 2n with tlie turn-off of diode

D,.

During these two

intervals both diodes are ON, terminals bV and Z of the two secondary windings are shorted, and currents through these windings are i I =

-

f2. The amplitudes of these current do not rise to dangerous values because the transformer primary sidc is driven by a current source.

111. RECTIFIER CIRCUIT ANALYSIS

Tlie analysis of tlie Class E rectifier of Fig. l(a) begins with the following assumptions.

1) The rectifier circuit is symmetrical. Therefore, C, = C, = C , and L , = Lq = L.

2) T i e parasitiic resistances of the core and the windings, and the transfornier stray capacitances are neglected.

3) The diodes are ideal and identical, i.e., they have zero threshold voltage, zero on-resistance, iifinitc

OK-

resistance, and zero minority carrier charge lifetime in tlie case of the pi7 junction diode.

4) Filter capacitor Cf is large enough to neglect the output voltage ripple. For this reason, the parallel combination of C p n d R, can be replaced by a dc voltage source.

5) The sinusoidal current source driving the primary side of tlie rectifier transformer is ideal.

6) The transformer has a turns ratio of I? for each secondary.

Moreover, tlie winding and core resistances and the stray capacitance of the transformer are ignored. The magnetizing, inductance L,,, is assumed to be large enough to carry only a dc current. Therefore, it can be considered as an open circuit for the ac compoiient of the current.

(3)

I i , ' 2

'

DI I D2 c2

"

DI D2

f

Fig. 2. Current and voltage waveforms in a class E current-driven center-tapped low dv/dt rectifier. a) Operation at 0 < D 5 0.5. b) Operation at 0.5 < D S 1.

The equivalent circuits of the rectifier are linear during each interval given in Table I. Therefore, the Laplace transform can be used to analyze the rectifier circuit. Moreover, the relationship between the currents through the three transformer windings is given by

of currents i, and i 2 and voltages vD, = vC, and vDz= vc2 for each topological mode of a rectifier operated at 0 < D

s

0.5 are given below.

Combinations of (1) and (2) with equations resulting from the analysis of the four equivalent circuits of the rectifiers during

one

switching period allows for the derivation of the current and voltage expressions. As an examples, the equations

(4)

A . First Topological Mode:

#

<

wt

I#

+ 2zD

i , = iiI,sin a,$ NI,,, vc2 =

-I",

i , = n - s i i m t 2

+

-![il (q5+ 2 n D ) + i 2

( 4 +

2 n D ) ] 2 x c o s [ ~ o ( t -

--&-

4

--)I

2 n D x s l n [ w o ( t

-

U--

#

--)I

2 n D I l l , i z = - n -- sirmt 2

+

i [ i l ( @ + 2 n D ) + i 2 ( $ + 2 n D ) ] 2 $ 2 n D xcos[alo( 1 - - - o

-)I

w 1 -

- -

o

--)I

w

[vel

( # + 2 n D ) + v c 2 ( $ + 2 r D ) + 2 V o ]

- -

2w0 L

4

2 x 0 C O S W l - 1 2 w c vc1 = I d ,

--

i, ( 4 + 2 n D ) + i 2 ( @ + 2 a D ) .

-.(

t - - 4

-

-)I

2 a D

VCI,

t @ +

2aD) @ 2aD

vci ( # + 2aD)+2V0

4

27rD

+ -

2 w w

+ -

2

+ -

2 vc1, ( # + 2 7 r D ) + v c * ( # + 2 & ) + 2 V o + " C l

( I +

2 & ) (9)

- -

2

(5)

C. Third Topological Mode:

4

+

n

<

wt

54

t-

n

+ 2rrD Ill I 1 = -

'*;

- 2 w 2

-

cos($+ n ) A W O .in[%( t -

4

-

5)]+

Ji-

+ s i r i (d+ z ) [ w 2 c o s ( w t

-

4 -

n)

x{- wcos(#+ n ) c o s ( w t

-

4 -

n) +mos($h+ n)cos

[x

-

t -

-

:

-

-

31

+sir7(4+ z ) [ w s i i 7 ( w t - $ - z)]

D.

Fourth Topological Mode:

4 +

T + 2nD<wt

I4

+ 271.

1 . 2

+

- [ i l ( + + 2 z D + z)]cos 1 . 2

+

- [ i 2 ( + + 2 z D + I S ) ] C O S vc1 ( + + 2 z D + I S ) - ( 2 @ , L ) - v C ~ ( + + 2 z D + z)+2V0 sin[

I

w,

]

( t

-

-

:

4 - 2 1 ~ 0 - I S 2 w , L (14) I i2 =

-

ti 3 siti(wt) 2 1 . 2

+

- [ i i ( $ + 2 z D + Z ) ] C O S

w

+

- [ i 2 1 .

( 4 +

2 n D + n)]cos[m,(t

-

2 v C ~ ( + + 2 x 0 4 - Z) - 2 w , L v C ~ ( + + 2 z D + I S ) + ~ V O , 2 w , L w

(6)

i , ( q 5 + 2 n D + n)

+

2

i2(4+

2zD+ n) ,

+

2 w

+

vc.($b+ 2 2ZD+ Is) c o s [ u ) o [ l -

4-

2 - ) ] w v c Z ( # + Z T D + n)

+

2 w

+

Y o ,

[

W O

(

I -

'-

2r-X)]+

vc-(b+ 2 z D + Z)

vci

(#+

2 & + w)+ V C Z ( 4 . t 2 & + n)+2Vo - 2 (16) c o s c ~ t - 1 2wc vc2 = I l l " /

-

i 1 ( 4 + 2 n D + T ) s , l l [ m o ( . t -

#-

2 A D - r)] 2 w

+

i z ( 4 + 2 r D + I C ) 2

+

{cos[wo( t -

4-

2 n D -

7]-1}

VCI ( 4 + 2zD+ X) 2 0

+

+ vo{cos[u)o(

t - 2 1 C D - w .)]-I} where wo = I/-.

Combination of (1)

to

(17) allows for the calculation of paranieters such as

4,

D, the dc output current I,, the maxiniuni current through each diode ID,,,,, and the maximum reverse voltage across each diode VDhf Unfortunately, the

expressions

of

these quantities cannot be derived in a closed form. For this reason, a coiiiputcr program has been developed to calculate these parameters.

Fig. 3 shows a plot of

D

as a function of load resistance RL for f, = 4.9 MHz (resulting from L = 15 nH and C, = 70 I$) and a cotistant output voltage normalized with respect to the transformer turns ratio Vdiz = 0.275 (it has been assumed that Vo = 3.3 V and n = 12). The dIode duty cycle decreases as the output current decreases. Therefore, the current through the diodes beconles more impulsive at light loads. Moreover, a sinal1 variation of D is needed to regulate the output voltage over a wide load range, e.g., duty cycle D decreases from 0.6 to

0.45 for a load resistance increasing from 0.14 R to 1.4 Q.

Figs. 4 depicts a plot of the maximum current through the

transformer primary winding I,,, of at

fo

= 4.9 MHz and V& = 0.27. Current I,,, iiicreascs from 0.5 A to 5 A as the de output current I, increases from 2.3 A to 23 A. Therefore, both the dc output current and the primary current rangc in the same relative interval, e.g., 1 to 10 or 10Y0 to 100%.

Both Z,,, and D depend on wo aiid V d h while tlie diode maximuin current aiid voltage are independ of these parameters.

( a )

K L

Fig. 3. Duty cycle D versus load resistance HL.

O L J

0 .2 .4 .6 .8 1 1.2 1.4

(0 R L

Fig. 4. Amplitude of primary current Znr as a fuiictioii ofRL at fo = 4.9 MHz and VJti = 0.27.

Fig. 5. Normalized maximum current ID,,/"o as a function or duly cycle D.

Fig, 5

shows

JDM iiormalized

with respect to

,Z

as

a

hnction of 0. The maximum nornialized current through tlie diodes decreases from 1.5 to 1.1 as D increases from 0.4 to 0.6.

Since D is in the range of 0.45-0.6 for a load resistance decreasing from 1.4 to 0.14, tlie niaxiinuni current through the diodes increases from 3.45 lo 25 A for a dc output current

(7)

ranging from 2.3 to 23 A. This shows that the current through the diodes does not significantly exceeds tlie dc output current when the rectifier is operated at full load.

A plot of VDy normalized with rcspect to Vo as a function of D is shown 111 Fig. 6. The maximum normalized reverse voltage

across

the rectifier diodes increases froin 3.5 to 4.3 for

D increasing from 0.45 to 0.6. For a rectifier operated at an output voltage Vo = 3.3 V and a load resistance in the range to 0.14 to 14 W, the niaxiniuiii voltage across the diodes increases from i 1.5 V at full load to 14.2 V at light load. Bccause of the low values of VDM, Schottky diodes can be used in the rectifier circuits. This allows for a high-Frequency operation of the

2.5 rectifier. 6.5 VDM Po6 5.5 5 4.5 4 3.5 3

/

.2 .25 .3 .35 .4 .45 .5 .55 .6 .65 D

Fig. 5. Nonnalized maximuin diode reverse voltage VD&V0 as a

function of duty cycle D.

IV. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS A a full-range off-line power supply based on class DE dc-dc converter with a class D series resonant inverter and a class E current-driven center-tapped low &/dt rectifier was built to operate at an input dc voltage VI = 120 to 370 V,,, a regulated output voltage Yo = 3.3 V, an output power

Po = 60 W, and a nominal operating frequency

f

= 500 kHz. The maximum output current ofvtlie converter was lob, = 18 A, which corresponds to a minimum load resistance

I$,,,!,, = 0.18

R.

The converter circuit was designed for the minimuni input voltage and maximum load operation. The dc-to-dc voltage transfer function of the entire converter was

hl,,,, = Vo I VI

,,,]

,,

= 3.3 I 120 = 0.0275. A class D series

resonant inverter operated at a voltage transfer function

M,,,, = 0.383 was used as a sinusoidal current source.

Therefore, the rectifier voltage transfer function was AdR = Ad,,,, / ~ l l , l , a x = 0.0275 10.383 = 0.072. AS a result, the amplitude of the fundamental component of tlie primary winding voltage in phase with the primary current was calculated as VR,,l =

f i

V0lMR = 64.8 V and the transformer turns ratio was I? = 12.

The center-tapped transformer was built on a EFD30 Siemens N49 ferrite core. The primary was wound with 24

turns of AWG22 solid copper wire and llic two sccondary windings with 2 turns of copper strips 15 x 0.15 nini each. The measured transformer magnetizing inductance was L,, = 1.23 nlH, the equivalent series resistance (ESR) of the three windings seen across tlie terminals of the primary winding was R, = 0.63 Q,

f

= 500 kHz and each secondary

leakage inductance was L = 18 nH. Two International Rcclifier 32CTQ30 Schottky diodes were used in tlie rectifier. An

external capacitance C, = 66 nF was connected in parallel with each diode. Two electrolytic Oscori 100 pF / 20 V capacitors connected in parallel were used as filter capacitors. Fig. 6 shows experimental voltage and currcnt waveloriiis of the transformer primary winding at VI = 110 V and

f=

465 kHz. Fig. 7 shows the experimental waveforms of the vollagcs across diodes D , and D,. The measured efficiency of the ac-dc converter iiicluding the front-end full-bridge transfromerless rectifier is plotted in Fig. 8 as a function of lo. The measured eEiciency at the full load operation at a low line voltage Vi,,,,, = 120 V was q = 81 YO and was 1.5% higher than the

eficiency measured at V,,.,f,, = 220 V over the eiitirc load range.

"P

1

Fig. 6. Wavefomis of vollage and current for the primary windiiig for

the transfonner at an opcrating frequencyf= 465 HIZ, ac input

voltage VI,,,, = 110 V, output voltage Vo = 3 . 3 V, and liL = 0.18 R. Vertical: 100 V/div. for vp and 2 Ndiv. for i: horizontal 500 iddiv.

Fig. 7. Wavefoniis of the reverse voltage on each diode at an

operatiiig frequencyf= 465 kHz, ac itiput voltage Vl,.fl,s = 1 I O V, output voltage Yo = 3 . 3 V, and RL = 0.18 R. Vertical: 10 V/div.:

horizontal 500 nddiv.

5 5 t

1

-1

(A) Io

Fig. 8. Eficiericy of the enire power supply versus output current at an ac input voltage VI,.,,,, = 220 V and V, = 3.3 V.

(8)

V. CONCLUSIONS

The analysis, design procedure, and experimental verification of a class E current-driven center-tapped low dv/dt

rectifier have been presented. The leakage inductances of the transformer have been taken into account. In the class E rectifier, each diode turns on and of at zero voltage with a limited dwdt at tlie turn-off and dv/dt = 0 at the turn-on. Moreover, di/dt is limited at the diode turn-off and

a

soft-reverse recovery of diodes is achieved. The class E current-driven center-tapped low dddt rectifier has been used to build a 60 W power supply operated at a line voltage varying from 85 to 260 V,,,, and a regulated output voltage Vo = 3.3 V. A maximum efficiency 17= 80 % has been achieved for the whole power supply at tlie niasiniuni output current I, = 18 A and input ac voltage VI,.,,,, = 220 V.

Since zero-voltage turn-on of the switches is achieved, the rectifier eff'iciency

can

be increased if diodes

are

replaced by low on-resistance power MOSFETs. Theoretical analysis and experimental verifications of tlie class E current-driven center-tapped synchronous rectifier are recommended for future work.

REFERENCES

[I] M. K. Kaziniierczuk, "Class E dvddt rectifier," Proc.

Inst. Elec. Eiig., Part B, Electric Power Appl., vol. 136, pp.

[2] M. K. Kaziniierczuk, and X.T. Bui, "A family of class E resonant dc-dc power converters," Proc. 16th Intern. PCI '88 Cor$ (SATECH '88), Dearborn, MI, pp.383-394, Oct. 3-6,

1988.

[3] J. Jozwik and M.K. Kaziniierczuk, "Analysis and design of Class E2 dc-dc converter," IEEE Trans. Ind. Electroii., vol

IE-37, pp.173-183, April 1990.

[4] A. Reatti, M. K. Kazimiewzuk, "Efficiency of the class E half-wave low dvddt rectifier," Proccediiigs of ISCAS'93,

Chicago, USA, Vol. 4, pp. 2331-2334, May 3-6, 1993. [5] A. Reatti, M. K. Kaziniierczuk, "Comparison of the efficiencies of class D and class E rectifiers," Proceeding o j

36th Midwest Syitiposiuni on Circuits and Systeiiis, Detroit,

[6]

M.

Bartoli, A. Reatti, M. K. Kazimierczuk, "Efficiency of a class E dc-dc converter with

a

center tapped rectifier at any loaded quality factor," Proceedings of 3 7th Midwest Syiiiposiuiii 011 Circuits Systems, Lafayette, LA, August 3-5,

[7] A. Reatti, M. K. Kaziniierczuk, and R. Redl, "Class E full-wave low dv/dt rectifier," IEEE. Traiisactroiis oii Circuits

aiidSyslenis, Part I, 40, 73-85, February 1993.

[8] Kaziniierczuk, M. K. and K. Puczko, "Power-output capability of class E amplifier at any loaded Q and switch duty cycle," IEEE Trans. Circuits Syst., vol CAS-36, pp. 1142-

1144, August 1989.

[9] K. Schniidtner, "A new high frequency resonant converter topology," Proc. High Fueq. Power Conversion Cor$, pp.390-

403, San Diego, CA, May 1988.

[IO] S.L. Smith and S. Robinson, "An off-line, one MHz 350- Watt parallel resonant converter (PRC) utilizing an RF 257-262, NOV. 1989.

USA, Vol. 2, pp. 872-874, August 16-18, 1993.

1994, pp. 678-681.

transformer," High Frequency Power Conversion Conference,

San Diego, CA, pp. 446-466, May 1988.

I l l ] R. Myers and R.D. Peck, "200-KHz Power FET Technology in New Modular Power Supplies,"

Hewlett-Packai-d Jouriial, pp. 3-10, August 1981.

[12] V. Vorpdrian and S. Cuk, "A complete dc analysis of the series resonant converter," in IEEE Power Eletron. Specialists Col$ Rec., Cambridge, MA, pp. 85-100, June 14-17, 1982. [ 131 R. L. Steigenvald, "High-frequency resonant transistor dc-dc converter," IEEE Traits. Power Electron., pp. 18 1- 19 1, May 1984.

[ 141 R. L. Steigenvald, "A comparison of half-bridge resonant converter topologies," IEEE Trans. Power Electron., vol. PE-3, pp. 174-182, April 1988.

[15] R. J. King and T. A. Stuart, "A nornialized model for the half-bridge series resonant converter," IEEE Trans. Aerospace Eleclroii. Syst., vol. AES-17, pp. 190-198, Mar.

1981.

[ 161 M. K. Kazimierczuk, and S. Wang, "Frequcncy domain analysis of series converter for continuous conduction mode,"

IEEE Trans. Power Electron., Vol. 7, No. 2, pp. 270-279, Apr. 1992.

[17] M. K. Kazimierczuk, N. Thirunarayan, and S. Wang, "Analysis of series parallel resonant converters," IEEE Truiis.

Aerospace Electron. Syst., Vol. 29, No. 1, pp. 88-99, January 1993.

[18] M. K. Kazimierczuk, and W. Szaraniec, "Class D zero-voltage-switching inverter with only one shunt capacitor," Proc. Inst. Elect. Eiig., Pt. B, Elec. Power Appl.,

vol. 139, Nov. 1992.

[ 191 M. K. Kaziniierczuk, and W. Szaraniec, "Electronic ballast for fluorescent lamps," IEEE Trans. Power Electron.,

[20] M. K. Kaziniierczuk, W. Szaraniec, and S . Wang, "Analysis and design of parallel resonant converter at high Q,"

IEEE Trans. Aerospace Electron. Syst., Vol. 28, No. 1, pp.

35-50, January 1992.

[2 I] M. K. Kazimierczuk and D. Czarcowski, "Resonant power converters," New York: John Wiley & Sons, 1995. Vol. PE-8, ~yp. 386-395, Oct. 1993.

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