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The existing C-simulator used for the GFSK Bluetooth standard has been modified in order to simulate the Baseband Enhanced Data Rate Modulator and Demodulator, taking care to insert all the non-ideal effects. Firstly, with regards of the modulation part, tests have been performed checking the output values of both the filtering implementations through Look-up Table and Polyphase Filter decomposition. Both the symbol streams result exactly the same and may be therefore considered approximately equal to the ideal case obtained with a digital convolution.
Although some parts of the Polyphase filtering architecture work at a twice higher frequency in comparison to the LUT case, on equal switching activity conditions both achieve the identical power consumptions. Moreover, within both these filtering architectures, the ROM block occupies at least the 90% of silicon area. Consequently, an implementation through Polyphase network is preferred, obtaining a gain in terms of ROM size occupation approximately of 45% in comparison with the Look-up Table implementation.
Moreover, simulation results show that the ISI and the BER value can be reduced further by increasing the length of the SRRC filter impulse response. As known, higher filter orders cost more in terms of chip area employed, therefore a costs/performance trade-off is required. As shown in the last chapter, using a filter length equal to
[
−2T ,2T[
, the achieved BER value is at most 1dB more degradedthan the best case of
[
−3T ,3T[
filter. Finally, the transmission filterimplementation through Polyphase network with a filter length of 4T results the best trade-off costs/performance solution.
Conclusions & Future works
92 In this way, Modulator architecture related to π/4-DQPSK and 8DPSK requires in all fourteen ROMs with a total size of 1.75 Kbytes (14⋅128x8 bits). Furthermore,
using a 1.3µm technology, the resulting silicon area is about 0.010 mm2.
For the Demodulator part, a FIR filter implementation of the SRRC filter is first required, even if this solution may result very expensive in terms of silicon area employed and power consumption. Unfortunately the filters already implemented with Bluetooth standard 1.0 cannot be re-used. As known, the cost of a FIR filter implementation is influenced by the number of taps. For both the new DPSK modulations a single FIR SRRC filter is needed and the simulation results show that also in this case a filter length of 4T (53 taps) can be implemented. Besides, referring to the internal structure of the Demodulator, only 4 multipliers and 2 full-adders are required for the Vector Product block, adding a small ROM of 16 bytes size for the 8DPSK Phase Evaluation block.
The Timing Recovery algorithm provides a direct estimation of the timing information and can be implemented with a digital circuit. During this work, a simple algorithm based on the direct demodulation of the Synchronous Sequence has been implemented and may be used for both π/4-DQPSK and 8DPSK cases in order to avoid a simple doubling of the chip area.
With regards of the demodulator part, in parallel to the 13MHz block a complete architecture working at 6.5 MHz has also been implemented in C-simulator. Simulation results show that the achieved performance are almost the same (within a 0.5 dB gap) in comparison of the best case using a sampling frequency equal to 13MHz. In this way, a 6.5MHz architecture may be implemented taking care to use a preliminary digital elaboration block in order to obtain a smaller power consumption, up to ½ compared with the 13MHz case.
At the end, although for the implementation of the new EDR Modem standard it has not been possible to reuse all the parts of the existing architecture, the basic blocks proposed in this thesis have a complexity which clearly implies a feasible realisation of the chip.
Conclusions & Future works
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In the meantime that the C-simulator was modified in order to implement the new Bluetooth standard, inside STMicroelectronics Labs was developed a VHDL code. This further step has been possible thanks to the several investigations and the know-how acquired during this thesis work. This VHDL program has been synthesised in a FPGA board and now this product is under testing inside the ST-laboratories. However, for the moment the C-simulator remains the best tool to investigated the new Enhanced Data Rate chip functionality.
As simulation results show, the C program and consequently the related VHDL implementation need surely optimisations specially respects to the 8DPSK Phase Evaluation block. The proposed 8DPSK demodulator architecture results almost redundant, therefore an investigation on other DPSK phase evaluation algorithms is needed. While, for the new Timing Recovery module, several SIG members suggest to use a Semicoherent demodulation scheme [11] in order to achieve better demodulation performance, taking care to respect the complexity of the implementation.
Finally, if the Lab-measures performed on the board will confirm the C-simulator results achieved during this work, the consequent chip implementation will be in line with the performance of the other competitors. Or rather, if the specifications required will be confirmed with the same interesting margins, STMicroelectronics will own a good performance chip in order to take the advantage as regards to the other companies.
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[1] Specification of the Bluetooth System, Volume 1, Core, version 1.1; https://www.bluetooth.org/spec/Bluetooth_Core_1.1_vol_1.zip
[2] Specification of the Bluetooth System, Core Specifications, version 1.2; https://www.bluetooth.org/spec//Bluetooth_Core_Specification_v1.2.zip
[3] M.Kim, D.Kim, J.Chung and M.Lim,
“1:N interpolation FIR filter design for SSB/BPSK-DS/CDMA”,
Signal Processing Systems, SiPS 2000; pp. 407 – 415.
[4] E. Obetti, Laboratorio di Segnali, Ed.Libreria Progetto, Padova 1997.
[5] N.A. D’Andrea, Teoria dei Segnali Passa Banda, Ed. ETS, Pisa 1998.
[6] G. Cariolaro, Modulazione Analogica, Discreta e Numerica,
Ed.Libreria Progetto, Padova 1997.
[7] L.E. Franks, “Carrier and Bit synchronization in Data Communications – A Tutorial Review”, IEEE – Transactions on Communications ,
Vol. 28, Issue: 8, pp. 1107 – 1121; Aug 1980.
[8] P. Capretta, “Equalizzatori per sistemi GSM”, Tesi di Laurea , Università di Padova, a.a. 1997/98.
References
95 [9] E. Obetti, “Architetture Digitali per Modulatori GSM”, Tesi di Laurea ,
Università di Padova, a.a. 1997/98.
[10] A.V. Oppenheim, and R.W. Schafer, Discrete-Time Signal Processing , Prentice Hall, Englewood Cliffs, New Jearsey, 1989.
[11] G.W. Lank, I.S. Reed, G.E. Pollon,
“ A Semicoherent Detection and Doppler Estimation Statistic ”
IEEE – Transactions on Aerospace and Electronics Systems ,
Vol. AES-9, No.2 , pp.151 – 165; March 1973.
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:
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BT Bluetooh
BER Bit Error Ratio
GFSK Differential Phase Shift Keying
π/4-DQPSK π/4 rotated differential encoded quaternary phase shift keying
8DPSK Differential encoded 8-ary phase shift keying
2 Mbps 2 megabits per second Payload data rate using π/4-DQPSK
3 Mbps 3 megabits per second Payload data rate using 8DPSK
RF Radio Frequency
ISM Industrial, Scientific and Medical LMP Link Manager Protocol
MED Medium Rate
