SOFTWARE PROGRAMMABLE I2C/SPI interface for APB

UNIVERSITÀ DI PISA

FACOLTÀ DI INGEGNERIA

C

ORSO DI

L

AUREA SPECIALISTICA IN

I

NGEGNERIA

E

LETTRONICA

Tesi di laurea

SOFTWARE PROGRAMMABLE

I

2

C/SPI interface for APB

Relatori:

Prof. Luca Fanucci

______________________

Prof. Pierangelo Terreni

______________________

Candidato

Luca Bacciarelli

___________________

Index

I

Index

1

Introduction

... 1

1.1 Aim of this work ...1

1.2 Serial interfaces...2

1.2.1 Advantage of serial interfaces...3

1.2.2 RS-232 ...4 1.2.3 RS-422 and RS-485 ...5 1.2.4 I2C ...6 1.2.5 SPI ...8 1.2.6 Microwire...9 1.2.7 1-Wire ...10 1.2.8 Bit banging ...10

1.2.9 Choosing the right bus ...11

1.3 AMBA Bus ...12

1.3.1 A typical AMBA-based microcontroller...14

1.3.2 Overview on the AMBA AHB...15

1.3.3 Overview on the AMBA ASB ...17

1.3.4 Overview on the AMBA APB ...18

1.3.5 Choice of system bus ...19

1.4 APB Bus...20

1.4.1 AMBA APB signal list ...21

1.4.2 State diagram...22

1.4.3 Write transfer ...24

1.4.4 Read transfer ...25

1.4.5 Typical APB slave...25

1.4.6 Timing diagrams ...26

2

SPI protocol

... 29

2.1 Introduction ...29

2.2 SPI Transfer Formats ...29

2.2.1 SPI Clock Phase and Polarity Controls...30

2.2.2 CPHA Equals Zero Transfer Format...30

2.2.3 CPHA Equals One Transfer Format ...31

2.3 SPI Block Diagram ...32

2.4 SPI Pin Signals...34

Index

II

2.4.2 MISO and MOSI pins ...35

2.4.3 CS pin...36

2.5 Beginning and Ending SPI Transfers...36

2.5.1 Transfer Beginning Period (Initiation Delay) ...37

2.5.2 Transfer Ending Period ...39

2.6 Transfers to Peripherals with Odd Word Lengths ...41

2.7 Example of SPI network ...42

3

I

2

C protocol

... 43

3.1 Introduction ...43

3.2 I2C benefits...44

3.3 I2C Bus introduction...45

3.4 The I2C-Bus concept ...46

3.5 General Characteristics ...48

3.6 Bit transfer...48

3.6.1 Data validity ...49

3.6.2 Start and stop condition...49

3.7 Transferring data ...50 3.7.1 Byte format ...50 3.7.2 Acknowledge ...51 3.8 Arbitration procedure ...53 3.8.1 Synchronization ...53 3.8.2 Arbitration ...54

3.8.3 Use of the clock synchronizing mechanism as a handshake...56

3.9 Formats with 7-bit addresses...57

3.10 7-bit addressing ...60

3.10.1 Definition of bits in the first byte...60

3.10.2 General Call address ...62

3.10.3 Start byte ...65

3.10.4 CBUS Compatibility ...67

3.11 Extensions to the standard-mode I2C-bus specification...68

3.12 Fast mode ...69

3.13 Hs-mode ...71

3.14 10-bit addressing ...72

3.14.1 Definition of bits in the first two bytes ...72

Index

III

3.14.3 General call address and start byte with 10-bit addressing ...77

3.15 Electrical and timing specifications ...77

4

Software programmable I

2

C/SPI interface for APB

... 82

4.1 Overview ...82

4.2 Block diagram and connections ...83

4.3 Interface parameters and signal lists ...87

4.4 I2C/SPI Interface Top Level Registers Description ...88

4.4.1 Selection Register (sel_reg) ...89

4.5 I2C/SPI Interface SPI module Registers Description ...90

4.5.1 Configuration and Control Register (CCR) ...90

4.5.2 Clock Divider Register (CDR)...92

4.5.3 Interrupt and Status Register (ISR) ...93

4.5.4 Interrupt Enable Register (IER) ...94

4.5.5 Reception Buffer Register (RBR) ...95

4.5.6 Transmission Buffer Register (TBR) ...96

4.5.7 SPI Buffer Control Register (BCR) ...96

4.5.8 SPI Number of Selected Slave Register (NSR) ...97

4.6 I2C/SPI Interface I2C module Registers Description ...98

4.6.1 Control Register (CTR)...99

4.6.2 Prescaler Register (PRER) ...100

4.6.3 Status Register (SR) ...101

4.6.4 Command Register (CR)...102

4.6.5 Reception Register (RXR) ...103

4.6.6 Transmission Register (TXR) ...104

4.6.7 Buffer Control Register (BCR) ...104

4.6.8 Slave Address Register (Slave_Addr)...105

4.7 I2C/SPI Interface Application Notes ...107

4.7.1 SPI Application Notes...107

4.7.1.1 CASE A: MSSL=1 – CSAG=0 – CONT_CSN=0 ...109

4.7.1.2 CASE B: MSSL=1 – CSAG=0 – CONT_CSN=1 ...110

4.7.1.3 CASE C: MSSL=1 – CSAG=1 – CONT_CSN=0 ...111

4.7.1.4 CASE D: MSSL=0 – CONT_CSN=0...112

4.7.1.5 CASE E: MSSL=0 – CONT_CSN=1 ...113

4.7.2 I2C Application Notes ...114

4.7.2.1 CASE A: MASTER TRANSMITTER ...116

4.7.2.2 CASE B: MASTER RECEIVER ...117

4.7.2.3 CASE C: SLAVE TRANSMITTER...118

4.7.2.4 CASE D: SLAVE RECEIVER ...119

Index

IV

4.8.1 Test environment for I2C module...120

4.8.2 Test environment for SPI module ...123

4.9 Main structure of the test environment ...125

4.9.1 Test functions of I2C mode ...127

4.9.2 Test functions of SPI mode ...134

4.10 Bus Implementation ...136

4.11 Summary of the tests executed by I2C test bench ...128

4.11.1 Addressing 10 BIT, Mode: MASTER-RX ...139

4.11.2 RX 1 byte and NACK of the data received and STOP ...140

4.11.3 TX 1 bytes and ACK of the data received by slave and STOP..140

5

Synthesis on FPGA

... 142

5.1 Macro statistics ...142

5.2 SPI Module reports ...145

5.3 I2C Module report ...146

5.4 I2C/SPI interface module report ...147

5.5 Systems comparisons ...148

5.6 Power consumption on FPGA...150

6

Synthesis on CMOS

... 151 6.1 Synopsis structure ...151 6.2 Synthesis ...152 6.3 Power estimation...156 6.4 Synthesis reports ...159 6.4.1 Macro statistics ...160

6.4.2 SPI Module reports ...161

6.4.3 I2C Module report ...162

6.4.4 I2C/SPI Module report ...164

6.4.5 Dependence of synthesis results on capacitive loads...165

6.5 Power analysis and optimization...167

7

Conclusions

... 170