C/SPI interface on APB AMBA Bus Design and FPGA prototyping of an embedded system featuring a programmable I Facoltà di Ingegneria UNIVERSITÀ DEGLI STUDI DI PISA

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UNIVERSITÀ DEGLI STUDI DI PISA

Facoltà di Ingegneria

Corso di Laurea in Ingegneria Elettronica

Tesi di Laurea

Design and FPGA prototyping of an embedded system

featuring a programmable I

2 _{C/SPI interface}

on APB AMBA Bus

Relatori:

Prof. Luca Fanucci

___________________

Prof. Pierangelo Terreni

_______________

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I

INDEX

1 ...

Introduction

...1

1.1 Design Driven by Differentiation, Cost and Time to Market... 1

1.2 Technology Pressure ... 3

1.3 Design Productivity Gap ... 4

1.4 Aim of this work... 5

1.5 The choice of the Processor ... 7

1.6 Verification methodology and approach ... 8

1.7 Thesis outlines ... 11

2 Software programmable I

2 _{C/SPI interface for APB}

... 12

2.1 Introduction ... 12 2.2 I2C protocol ... 12 2.2.1 Overview... 12 2.2.2 I2C Bus Terminology ... 13 2.2.3 I2C Bus Communication ... 14

2.2.3.1 START and STOP conditions ... 16

2.2.3.2 10 bit Addressing... 17

2.2.3.3 Transmitting a byte to a slave device ... 18

2.2.3.4 Receiving a byte from a slave device ... 18

2.2.3.5 Getting Acknowledge from a slave device ... 19

2.2.3.6 Giving Acknowledge to a slave device ... 20

2.2.3.7 No acknowledge condition ... 21

2.2.3.8 Bus Arbitration ... 22

2.2.3.9 Clock Synchronization ... 24

2.2.4 The I2C Bus Hardware Structure... 25

2.3 SPI Protocol Overview ... 28

2.4 AMBA Buses_{... 29}

2.4.1 Overview on the AMBA AHB... 30

2.4.2 Overview on the AMBA ASB ... 30

2.4.3 Overview on the AMBA APB ... 30

2.4.3.1 AMBA APB signal list ... 32

2.4.3.2 State diagram... 33

2.4.3.3 Write transfer... 34

2.4.3.4 Read transfer... 35

2.4.3.5 APB Bridge ... 35

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II

2.5 Software programmable I2C/SPI interface for APB_{... 38}

2.5.1 Overview... 38

2.5.2 I2C/SPI Block Diagram and Connections ... 39

2.5.3 I2C/SPI Interface Parameters... 40

2.5.4 I2C/SPI Interface Signals List ... 40

2.5.5 I2C/SPI Interface Top Level Registers Description ... 41

2.5.6 I2C/SPI Interface SPI module Registers Description ... 42

2.5.7 I2C/SPI Interface I2C module Registers Description... 43

2.5.8 I2C configuration... 44

2.5.8.1 CASE A: MASTER TRANSMITTER... 46

2.5.8.2 CASE B: MASTER RECEIVER ... 47

2.5.8.3 CASE C: SLAVE TRANSMITTER ... 48

2.5.8.4 CASE D: SLAVE RECEIVER... 49

3 ...

LEON processor

...59

3.1 Introduction ... 59

3.2 AMBA on-chip buses ... 62

3.2.1 Overview... 62 3.2.2 AHB Bus... 63 3.2.3 APB Bus ... 63 3.3 On-chip peripherals... 63 3.3.1 On-chip registers ... 63 3.3.2 Interrupt controller ... 65 3.3.2.1 Interrupt assignment ... 66 3.4 Model configuration... 66 3.4.1 Boot Configuration ... 67 3.4.1.1 PMON: ... 68

3.4.1.2 Booting from the debug support unit... 69

4 ...

Verification and Validation of the interface

...70

4.1 Verification road map ... 70

4.1.1 Step 1: I2C slave mode validation vs. an external I2C master module ... 70

4.1.2 Step 2: I2C master mode validation vs. I2C slave validated at step 1 ... 71

4.1.3 Step 3: I2C master and slave mode validation post synthesis... 71

4.1.4 Step 4: I2C system validation within Leon CVS environment ... 72

4.1.5 I2C standard conformance matrix... 73

4.2 Main structure of the Test environment_{... 73}

4.2.1 Overview... 73

4.2.2 Block- and Bus-Level Verification ... 74

4.2.2.1 Functional Verification... 75

4.2.2.2 VHDL structure of the I2C/SPI module and Test suite... 75

4.2.2.3 Amba APB emulation... 76

4.2.2.3.1 Read and check cycle... 77

4.2.2.3.2 Customizable Test functions... 79

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III

4.2.2.3.4 Some Case example ... 86

4.2.2.4 Timing Verification ... 88

4.2.2.4.1 Synthesis on CMOS of the I2C/SPI interface... 88

4.2.2.4.2 Summary of the tests executed by I2C test bench ... 91

4.2.3 System-level verification ... 92

4.2.3.1 Data base structure within Branca-Leon CVS environment... 92

4.2.3.2 Mounting of the new IP on AMBA on-chip APB bus... 93

4.2.3.3 Executed tests ... 95

4.2.3.3.1 Arbitration lost test validation model ... 97

4.2.3.4 Some case examples ... 98

5 ...

Firmware development

... 101

5.1 Overview ... 101

5.1.1 Reasons to choice Assembly as programming language... 101

5.2 SPARC V8 ISA_{... 101}

5.2.1 Assembly ... 103

5.2.2 Integer registers... 104

5.2.3 Instructions... 104

5.2.3.1 The set operation ... 104

5.2.3.2 The load and store operations... 105

5.2.3.3 The addition and subtraction operations... 105

5.2.3.4 The mov operation... 106

5.2.3.5 The condition code register ... 106

5.2.3.6 Branching operations... 107

5.2.4 Addressing ... 109

5.2.5 Register windows and procedure calls ... 110

5.2.5.1 Save and Restore ... 112

5.2.5.2 Stack management... 113

5.2.5.3 Procedure calling conventions... 113

5.2.5.4 Leaf procedures on the SPARC... 114

5.2.5.5 Interrupt handling in the SPARC... 116

5.3 Driver and test creation for the I2C/SPI interface_{... 117}

5.3.1.5 Interrupt handler ... 125

6 ...

Prototyping on FPGA

... 128

6.1 Overview ... 128

6.2 Virtex-II™ V2MB1000 Development Board ... 128

6.3 P160 expansion module ... 130

6.3.1 RS232 Port ... 131

6.3.2 I2C Port ... 131

6.3.3 FLASH and SRAM... 131

6.3.4 Design download ... 132

6.4 The design flow... 133

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IV

6.6 Synthesis results... 135

6.7 Leon mapping_{... 136}

6.8 Debug session_{... 138}

6.8.1 The GRMON program ... 138

6.8.2 Grmon debug session ... 141

6.9 Executed Tests ... 145

6.9.1 Some case examples ... 145

7 ...

CONCLUSION

... 148

APPENDIX A: LEON VHDL FILES ... 152

GLOSSARY ... 154

8 ...

BIBLIOGRAPHY

... 155

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V

INDEX OF TABLES

Table 2-1: Characteristics of the SDA and SCL I/O stages...26

Table 2-2: Characteristics of the SDA and SCL bus lines...27

Table 3-1: Default address allocation ...63

Table 3-2: On chip registers mapping...64

Table 3-3: Interrupt assignment ...66

Table 4-1: Standard conformance matrix ...73

Table 4-2: I

2

C module features...74

Table 4-3: Macro statistics...90

Table 4-4: Timing information for HS library...91

Table 5-1: Aliases for the integer registers...104

Table 5-2: The set operation ...105

Table 5-3: The load and store operations...105

Table 5-4: The addiction and subtraction operations...106

Table 5-5: The mov operation ...106

Table 5-6: Operations that update the CCR...107

Table 5-7: Branching operations...107

Table 5-8: Bitwise operations ...109

Table 5-9: Bitwise operations conditional code version...109

Table 5-10: Addressing modes ...110

Table 5-11: Load and store addressing ...110

Table 5-12: Aliases for the general registers ...110

Table 5-13: Save and Restore operations ...113

Table 5-14: Procedure calling instructions ...114

Table 5-15: Register uses for optimized leaf procedures ...114

Table 5-16: The call and retl operations ...115

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VI

INDEX OF FIGURES

Figure 1-1: Moore’s law ...3

Figure 1-2: Design Productivity gap...4

Figure 1-3: Leon Processor Architecture...7

Figure 1-4: Verification methodology ...8

Figure 1-5: Testbench block diagram ...9

Figure 1-6: Self-checking Testbench block diagram ...9

Figure 1-7: Soc block diagram...10

Figure 2-1: Master-Slave connection on the I

2

C BUS...12

Figure 2-2: Addressing and data transfer on the I2C bus ...16

Figure 2-3: Start condition ...16

Figure 2-4: Stop condition ...17

Figure 2-5: Transmitting bytes to a slave ...18

Figure 2-6: SCL clock cycle ...19

Figure 2-7: Receiving bytes from a slave ...19

Figure 2-8: Getting acknowledged from a slave device ...20

Figure 2-9: Giving acknowledge to a slave ...20

Figure 2-10: Multi master I

2

C...22

Figure 2-11: Bus arbitration...23

Figure 2-12: Clock synchronization ...24

Figure 2-13: Bus interface ...26

Figure 2-14: Definition of timing for F/S-mode devices on the I2C-bus. ...26

Figure 2-15: Main parameters of a signal on SCL (SDA) BUS ...27

Figure 2-16: Master-Slave connection on the I

2

C BUS...28

Figure 2-17: Typical Amba-based microcontroller ...29

Figure 2-18: State diagram of the activity of the peripheral bus ...33

Figure 2-19: Write transfer timing...34

Figure 2-20: Read transfer timing...35

Figure 2-21: The APB Bridge...36

Figure 2-22: Typical APB slave interface ...36

Figure 2-23: I

2

C/SPI Interface block diagram. ...39

Figure 2-24: I

2

C/SPI Interface connections ...39

Figure 3-1: Block diagram of the LEON-2...59

Figure 3-2: Interrupt controller ...65

Figure 4-1: Slave mode validation model...71

Figure 4-2: Master mode validation model...71

Figure 4-3: Master and Slave post-syntheses validation model ...72

Figure 4-4: Leon environment validation model ...72

Figure 4-5: VHDL structure of the I

2

C/SPI interface ...75

Figure 4-6: Typical flow for timing verification ...88

Figure 4-7: Directory structure in Synopsis...89

Figure 4-8: Data base structure ...92

Figure 4-9: Registers mapping on the AMBA APB BUS ...94

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VII

Figure 5-1: Load, store, add, and subtract operations...102

Figure 5-2: Register windows...111

Figure 5-3: Interrupt controller block diagram ...126

Figure 6-1: V2MB1000 board ...129

Figure 6-2: V2MB100 board block diagram ...129

Figure 6-3: P160 Expansion module ...130

Figure 6-4: P160 expansion module block diagram ...130

Figure 6-5: RS232 port ...131

Figure 6-6: I

2