6. Layout, LVS, post-layout simulations
The final layout is illustrated in Fig. 6.1.
Figure 6.1 Layout of the LNA
6.1. Layout description
We used a 0.12 µm CMOS process with seven metal layers.
The transistor are made by arrays of elementary MOSFET in parallel, each of them has a width of 6.52 µm. The main advantage of this solution is that such a transistor was already completely tested and measured by the factory and that we have a functioning model of it at our disposal. We can so predict its behavior in a more exact way. Moreover, every single elementary transistor is surrounded by a guard ring, made of Metal 1, that contacts the substrate with several vias (Fig. 6.2).
Figure 6.2 Elementary transistor with guard-ring
This means that, using an array structure, we can maximize the overall number of substrate contacts, so reducing the resistance between the bulk of the MOSFET and the ground metal. Grounding the substrate through a low ohmic path, we prevent substrate noise and other possible disturbances to have an influence on the transistors. For the same reason we covered a large part of the chip with the metal layer 1 (in green in the layout figure) and connected it to four VSS pads.
Thanks to its very large surface, any parasitic resistances and inductances are reduced to minimal values. The same effect was obtained for the supply voltage wires, by using a stack of four metal layers (M3-M4-M5-M6) of a consistent width (see the upper part of Fig. 5.46). To keep VDD as
much constant as possible and to reject any high frequency disturbance we put a block capacitor of 36 pF between the supply voltage and ground pads (Fig. 6.3).
Figure 6.3 Capacitor between VDD and VSS, ESD protection
It is a sandwich of n-diffusion and polysilicon and has a very high capacity per unity area. It could happen that an unwanted oscillation takes place between VDD and VSS, involving the above
mentioned capacitor and the residual parasitic inductances of the VDD and ground wires. To avoid
this eventuality we put a resistor of 4 Ω in series with the capacitor whose function is to damp any possible high frequency oscillation.
The capacitors used in the circuit are MIM type and make use of two extra metal layers, used exclusively for this purpose. These layers are located between the sixth and the seventh metal layer. For symmetry reason we realized the load capacitor with the parallel of two identical, half-sized, capacitors, mounted in a mirrored way, as depicted in Fig. 6.4.
Figure 6.4 Load capacitors
The resistors are realized with polysilicon and consist of a series of elementary resistances, connected together with Metal 1 and laid out in a particular form in order to save room on the chip. This arrangement allows us to better predict any border effect and to make their influence (in relative terms) independent on the size of the resistor.
Concerning the signal HF pads, they are made by the upper metal layers (the three lower metal layers are not used), so minimizing the parasitic capacitance, thanks to the increased distance to the substrate. Moreover, they have a smaller surface, namely 60 µm x 60 µm, while the DC pads have a size of 60 x 84 µm, that further reduces the unwanted capacitances. Finally, on the center-upper part of Fig. 5.46 the integrated inductor is well visible.
We paid attention to the reduction of the resistance of the input paths, since they have a strong influence on the Noise Figure. The capacitance must be kept also low to avoid a Gain drop. These problems were resolved by using the three upper metal layers shorted together with several vias. The same procedure was applied in the Vdd path at the top of the chip, this time to minimize the
parasitic resistance and inductance. The following figure shows the integrated control logic with two inverters, two NOR and one NAND port.
Figure 6.5 Integrated logic
6.2. Post-layout simulations
For the post-layout simulations we used an improved model for the MOS transistor, that was available only during the last part of this work. For this reason and because of the unavoidable parasitic capacitances and resistances of the Metals on the chip, the input impedance of the circuit was different than expected. Moreover, parasitic capacitances lowered the gain of about 3-dB and reduced the resonating frequencies of each mode of about 10% with respect to pre-layout simulation results. We solved this problem in two ways: modifying on-chip components and redesigning the external matching network. Specifically, the capacitor size was reduced of about 10% to compensate the parasitic capacitances. For more details see Tab. 6.1, where the names correspond to the elements depicted in Fig. 5.35. Some other secondary modifications were applied to further reduce the length of the metal interconnections. Subsequently, we changed the values of the external network as follows (see also Fig. 5.7): CB = 1.2 pF and LX = 10 nH. With these
Capacitor Schematic Layout Cload 300 fF 200 fF Cf 1 pF 1 pF CLF 400 fF 500 fF CLMF 600 fF 550 fF CHG 650 fF 650 fF CLG 6 pF 5 pF C1 800 fF 800 fF
Table 6.1 Comparison between schematic and layout values of the capacitors
In Tab. 6.1 we can see that the size of CLF was actually increased. This was done because in LF
mode all the capacitors are switched on (except the low gain ones). Since all the other capacitors were decreased, the resonating frequency would result too high in this operating mode. This effect was compensated just with a larger CLF.
The graphs related to the post-layout simulations, for each working mode are reported in Appendix B.
The gain curves reported in fig. B.15 and B.18 show that the maximum gain is obtained for about 2-2.05 GHz in HF mode, i.e., somewhat less than the expected frequency. This issue can be overcome by simply reducing either Lload oder Cload. The latter has already a very small size of 200 fF: that
means that a further reduction would imply a strong dependence of the load resonating frequency on the parasitic capacitances at the output nodes. A more feasible solution could be represented by the use of a smaller load inductance that would allow larger capacitors.
