Bibliografia finale

Bibliografia finale

Bernardi J., "Biografia di Giovanni Poleni", in: E. Tipaldo, "Biografie degli italiani illustri nelle scienze, lettere ed arti del sec.XVIII e de' contemporanei (Tomo X)", Venezia, Alvisopoli 1834. Verrua P., "Macchina Calcolatrice di Giovanni Poleni", Bollettino Accademia Italiana di Stenografia, n° speciale, anno VII, Aprile, 1931, pp. 69-76.

Soresini F. "La storia del calcolo automatico", Roma, Confindustria, 1971, Vol. I. Williams M. R., "A History of Computing Technology", IEEE Conputer Society, 2000. Morelli M., "Dalle calcolatrici ai computer degli anni cinquanta", FrancoAngeli, 2001. http://www.giovannipastore.it/

http://www.museoscienza.org/dipartimenti/catalogo_collezioni/scheda_oggetto.asp?idk_in=ST120-00179&arg=Calcolo

http://www.charlesbabbage.net/

http://www.mhs.ox.ac.uk/staff/saj/arithmometer/figure2.htm Pier Giorgio Perotto - Programma 101 Sperling & Kupfer Editori Passarella - Storia memoria magnetostrittiva P101

http://www.cep.cnr.it/

http://www.dif.unige.it/epi/hp/frixione/appunti_MT.pdf

Sulla architettura della Zuse Z1: https://arxiv.org/ftp/arxiv/papers/1406/1406.1886.pdf

http://www.colossus-computer.com/colossus1.html

http://www.horst-zuse.homepage.t-online.de/Konrad_Zuse_index_english_html/konrad_zuse.html Computer Science - The First Computers History and Architectures - Rojas (MIT 2000)

https://cctld.it/storia/doc/lettera_fermi.html

M. Goto, Y. Komamiya, R. Suekane, M. Takagi and S. Kuwabara, "Theory and Structure of the Automatic Relay Computer ETL-Mark-2," Research of the Electrotechnical Laboratory, No. 556, Sep. 1956.

H. Takahasi, "Parametron Computers," Iwanami-shoten, 1968

H. Takahasi, "The Birth of Electronic Computers," Chuuou-kouronsha, 1972

S. Takahashi, "Early Transistor Computers in Japan," Annals of the History of Computing, 8:2 (1986), 144–154.

http://www.museoaica.it/index.php?id=644

Rapporto del CNUCE del 1998 B4 dal titolo "First computers in Italy" http://hmr.di.unipi.it/HMR/HMR-AppStInf.pdf http://hmr.di.unipi.it/Archivio.html http://www.bletchleypark.org.uk/ http://www.storiaolivetti.it/percorso.asp?idPercorso=628 http://www.elea9003.it/ http://www.aisdesign.org/aisd/ettore-sottsass-jr-e-il-design-dei-primi-computer-olivetti Alan Turing, il genio che inventò il computer di Simone Buttazzi

http://areeweb.polito.it/didattica/polymath/htmlS/Interventi/Articoli/Enigma/Enigma.htm

http://curation.cs.manchester.ac.uk/digital60/www.digital60.org/birth/manchestercomputers/mark1/f erranti.html

http://elearn.cs.man.ac.uk/~atlas/

T. Kilburn, D.J. Howarth, R.B. Payne and F.H. Sumner, "The Manchester University Atlas Operating System," The Computer Journal, The British Computer Society, October 1961. Manuale operativo del calcolatore Mark I - Oxford University Press Massachussets USA 1946

La ricostruzione del calcolatore ENIAC su singolo circuito integrato:

http://www.seas.upenn.edu/~jan/eniacproj.html

Massimo Bozzo "La grande storia del computer"

Filmato video "Elea classe 9000" di Nelo Risi https://www.youtube.com/watch?v=lUhSYR68PqQ

http://www.core77.com/posts/52367/The-Rocky-Road-for-the-Curta-the-First-Mass-Market-Pocket-Calculator

http://www.hpmuseum.org/

B.E. Deal, A.S. Grove, E.H. Snow and C.T. Sah, "Observation of Impurity Redistribution During Thermal Oxidation of Silicon Using the MOS Structure", J. Electrochem. Soc. 112, 3 (1965)

O. Leistiko, Jr. and A.S. Grove, "Breakdown Voltage of Planar Silicon Junctions", Sol. - St. Elec. 9, 847 (1966)

Andrew S. Grove, "Mass Transfer in Semiconductor Technology", I & EC 48, July 1966 B.E. Deal, M. Sklar, A.S. Grove and E.H. Snow, "Characteristics of the Surface - State Charge (Qss) of Thermally Oxidized Silicon", J. Electrochem. Soc. 114, 3, 266 (1967)

A.S. Grove , O. Leistiko, Jr. and W.W. Hooper, "Effect of Surface Fields on the Breakdown Voltage of Planar Silicon p - n Junctions", IEEE Trans. Elec. Dev. ED - 14, 3, 157 (1967)

E.H. Snow, A.S. Grove, D.J. Fitzgerald, "Effects of Ionizing Radiation on Oxidized Silicon Surfaces and Planar Devices", Proc. of IEEE, 55, 7, 1168 (1967)

D.J. Fitzgerald and A.S. Grove, "Surface Recombination in Semiconductors", Surface Science 9, 2, 347 (1968)

L.L. Vadasz, A.S. Grove, T.A. Rowe and G.E. Moore, "Silicon - Gate Technology", IEEE Spectrum, October 1969

A.S. Grove, C.T. Sa h, "Simple Analytical Approximations to the Switching Times in Narrow Base Diodes", Sol. St. Elec. 7, 107 (1964)

A.S. Grove, P. Lamond, et al, "Stable MOS Transistors", Electro - Technology, Dec. 1965

Andrew S. Grove, "Integrated Circuits", McGraw - Hill Encyclopedia of Science and Technology (1969)

L.L. Vadasz, H.T. Chua and A.S. Grove, "Semiconductor Random - Access Memories", IEEE Spectrum, May 1971

A.S. Grove, A. Roder and C.T. Sah, "Impurity Distribution in Epitaxial Growth", J. Appl. Phys. 36, 3, 802 (1965)

B.E. Deal, A.S. Grove, E.H. Snow and C.T. Sah, "Observation of Impurity Redistribution During Thermal Oxidation of Silicon Using the MOS Structure", J. Electrochem. Soc.112 , 3 (1965)

E.H. Snow, A.S. Grove, B.E. Deal and C.T. Sah, "Ion Transport Phenomena in Insulating Films", J. Appl. Phys. 36, 5, 1664 (1965)

O. Leistiko, Jr., A.S. Grove, and C.T. Sah, "Electron and Hole Mobilities in Inversion Layers on Thermally Oxidized S ilicon Surfaces", IEEE Trans. On Elec. Dev. ED - 12, 5, 248 (1965) Tim Jackson (1998). Inside Intel: Andy Grove and the Rise of the World's Most Powerful Chip Company. Plume.

Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, pp. 114– 117, April 19, 1965.

Advancing Moore’s Law on 2014!, presentazione Intel® dell'agosto 2014

Challenges and Innovations in Nano -CMOS Transistor Scaling presentazione Intel® del 2009 di Tahir Ghani

Sito web della "Semiconductor Industry Association" http://www.itrs2.net/

MOS Scaling: Transistor Challenges for the 21st Century - Intel® Technology Journal Q3’ 98 http://www.nature.com/ncomms/2016/160825/ncomms12585/full/ncomms12585.html

ENEA - "Il grafene_ proprietà, tecniche di preparazione ed applicazioni" 72015 International Technology Roadmap for Semiconductors

A spin metal–oxide–semiconductor field-effect transistor using half-metallic-ferromagnet contacts for the source and drain - Satoshi Sugahara e Masaaki Tanaka del dipartimento di ingegneria elettronica presso l'Università di Tokyo, Giappone sulla rivista "APPLIED PHYSICS LETTERS" del 29 marzo 2004

"Pathway to the PiezoElectronic Transduction Logic Device", P.M. Solomon , B.A. Bryce , M.A. Kuroda 

11Interlayer Dielectrics for Semiconductor Technologies, ELSEVIER Academic Press

Prof. Krishna Saraswat, low-k dielectrics Stanford University, dipartimento di ingegneria elettronica Towards a Thermal Moore’s Law - Purdue University Purdue e-Pubs, Gregory M. Chrysler - Ravi V. Mahajan Intel Corporation 2007

The Lives and the Death of Moore’s Law - Ilkka Tuomi Visiting Scientist Joint Research Centre Institute for Prospective Technological Studies, 1 October 2002

Challenges of 22 nm and beyond CMOS technology - HUANG Ru, Department of Microelectronics, Peking University, Beijing 1000871, China

Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices, International Journal of Computer Applications Volume 84 – N° 10, Dicembre 2013

EUV Lithography—The Successor to Optical Lithography? , John E. Bjorkholm Advanced Lithography Department, Technology and Manufacturing Group, Santa Clara, CA. Intel Corporation

https://www.nature.com/articles/ncomms12585 The Quantum Limit to Moore’s Law, James R. Powell

Assessing Trends In The Electrical Efficiency Of Computation Over Time, Jonathan G. Koomey, Stephen Berard, Marla Sanchez, Henry Wong

Two Centuries of Productivity Growth in Computing, William D. Nordhaus http://www.intel4004.com/

F. Faggin and F. Capocaccia, “A new integrated MOS shift register,” in Proc. 25th Int. Scientific Congr. Electronics, Rome, 1968, pp. 143–152.

F. Faggin, T. Klein, and L. Vadasz, “Insulated gate field effect transistor integrated circuits with silicon gates,” in Int. Electron Devices Meeting Tech. Dig., Washington, DC, 1968, p. 22.

F. Faggin and T. Klein, “A faster generation of MOS devices with low threshold is riding the crest of the new wave, silicon gate IC’s,” Electronics, Sept. 29, 1969.

F. Faggin and T. Klein, “Silicon gate technology,” Solid-State Electronics, vol. 13, pp. 1125–1144, 1970.

F. Faggin and M.E. Hoff Jr., “Standard parts and custom design merge in four-chip processor kit,” Electronics, pp. 112–116, Apr. 24, 1972.

F. Faggin, et al., “The MCS-4-An LSI micro computer system,” Proc. IEEE Region 6 Conf., 1972. F. Faggin, “Power supply settable bi-stable circuit,” U.S. Patent 3753011, Aug. 14, 1973.

M. Hoff, S. Mazor, and F. Faggin, “Memory system for multi-chip digital computer,” U.S. Patent 3821715, June 28, 1974.

http://appunti.studentville.it/appunti/scienze-17/federico_faggin-2404.htm 10Intel® MCS-40 User Manual 1974.

Intel® MCS80_85 Users Manual January 1983 Datasheets Intel® sull'8231A/8232

http://www.cpu-world.com/CPUs/8085/

Intel Corporation i8080/i8085 Assembly Language Programming Manual http://www.cpu-world.com/CPUs/8080/

Datasheet Intel® dell'82C55 – 23125604 1981_iAPX_86_88_Users_Manual.pdf 210200_iAPX88_Book_1981 https://ia800301.us.archive.org/33/items/The8086Primer/Morse-The8086Primer.pdf http://www.cpu-world.com/CPUs/8088/ http://bitsavers.informatik.uni-stuttgart.de/pdf/intel/ISIS_II/9800938-01_8089_Assembler_Users_Guide_Aug79.pdf http://sandpile.org/ http://cpumuseum.jimdo.com/cpu-die-photography/ 80186, 80188, 80C186, 80C188 Hardware_Reference_Manual rev. 1990

210973-001_AP-186_Introduction_to_the_80186_Microprocessor_Mar83 http://www.cpu-world.com/Arch/80188.html

Intel_80C187_Datasheet

A PROGRAMMER'S VIEW OF THE INTEL 432 SYSTEM, Elliott I. Organick Mc Graw-Hill Performance Effects of Architectural Complexity in the Intel 432, ROBERT P. COLWELL Multiflow Computer, Inc. EDWARD F. GEHRINGER North Carolina State University and E. DOUGLAS JENSEN Kendall Square Research Corp.

Introduction to the iAPX 432 Architecture, Intel®

iAPX 43201 iAPX 43202 VLSI GENERAL DATA PROCESSOR, Intel® iAPX acronimo di Intel® Advanced Processor Architecture

The Multibus® Design Guidebook - Structures, Architectures and Applications, James B. Johnson, Steve Kassel. McGraw-Hili Book Company

Intel® iAPX 43203VLSI Interface_Processor datasheet Intel® Reference Manual for the Intel 432 Extensions to Ada

https://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/cs460/

http://homes.cs.washington.edu/~lazowska/cra/risc.html

http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf Intel® i860 64-Bit Microprocessor Hardware Reference Dec89 http://ed-thelen.org/comp-hist/intel-paragon.html

http://www.csm.ornl.gov/SC98/timetab.html http://www.netlib.org/benchmark/hpl/ 80960MC_Advance_Information_Jan91

http://smithsonianchips.si.edu/intel/i860.htm

"Il microprocessore 80286/287" Stephen P. Morse, Douglas J. Albert 210308-001_Introduction_to_the_iAPX_286_1982 210498-001_iAPX_286_Programmers_Reference_1983 210760-002_80286_Hardware_Reference_Manual_1987 http://www.intel.com/design/archives/periphrl/docs/7203.htm 231732-001_80386_Hardware_Reference_Manual_1986 290143-001_82385_32-Bit_Cache_Controller_Advance_Information_Jul87 http://wiki.osdev.org/System_Management_Mode

J. Coonen, W. Kahan, J. Palmer, T. Pittman, D. Stevenson, “A Proposed Standard for Binary Floating Point Arithmetic,” ACM SIGNUM Newsletter, October 1979.

Datasheet Intel® NPX 8087

Datasheet Intel® NPX 80287/80387/80387DX

Sull'algoritmo di calcolo CORDIC: "A survey of CORDIC algorithms for FPGA based computers" -Ray Andraka

"The CORDIC Computing Technique" - JACK VOLDER 1959 PROCEEDINGS OF THE WESTERN JOINT COMPUTER CONFERENCE

http://web.fis.unico.it/local/SunDocs/common-tools/numerical_comp_guide/sparc.doc.html

"Il microprocessore 80386/80387" - edito da Tecniche Nuove - Stephen P. Morse, Eric J. Isaacson, Douglas J. Albert (per la parte sui coprocessori Weitek vedi il capitolo 7)

http://wiretap.area.com/Gopher/Library/Techdoc/Cpu/coproc.txt Datasheet Weitek 1167/3167/4167

Intel® datasheet 240440-006_486DX

Intel® Embedded Write-Back Enhanced IntelDX4™ Processor - 27277101_Embedded Write-Back Enhanced

Intel® i486_Processor_Programmers_Reference_Manual_1990

SRT Division Architectures and Implementations - David L. Harris, Stuart F. Oberman, and Mark A. Horowitz

Pentium® PROCESSOR WITH MMX™ TECHNOLOGY – Intel®

Intel Reveals Pentium® Implementation Details, Architectural Enhancements Remain Shrouded by NDA - Brian Case, Microprocessor Report

Intel® Pentium® Processor User's Manual Volume 1 Intel® Statistical Analysis of Floating Flaw – 1994

242691-001_Pentium_Pro_Family_Developers_Manual_Volume_2_Jan96 242692-001_Pentium_Pro_Family_Developers_Manual_Volume_3_Jan96 MindShare_Pentium_Pro_and_Pentium_II_System_Architecture

Microprocessor Report - Volume 9, numero 15 del 13 novembre 1995

Microprocessor Report - 15 settembre 1997 (aggiornamento del microcodice del processore Pentium Pro)

http://www.tomshardware.com/reviews/intel,65-4.html

http://smithsonianchips.si.edu/ice/s4.htm sito web con analisi della costruzione di circuiti integrati e microprocessori

Application note Intel® 24508601 sul sistema di bus segnali AGTL+ Datasheet Intel® 82443BX

Datasheet Intel® 450KX/GX PCIset

Pentium III Processor Implementation Tradeoffs, Intel® Technology Journal Q2, 1999 Mobile Intel® Pentium III Processor-M Datasheet 298340-006

Mobile Intel® Pentium III Processor in BGA2 and MicroPGA2 Packages Datasheet 283653-002

A 0.18 μ m CMOS IA-32 Processor With a 4-GHz Integer Execution Unit, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001

Pentium 4 (PARTIALLY) PREVIEWED - Microprocessor Report, agosto 2000

The microarchitecture of the Intel® Pentium 4 Processor on 90 nm technology, Intel® technology journal volume 8, febbraio 2004

http://www.anandtech.com/show/1621 Pentium 4M datasheet 250686-007

Intel® Pentium D Processor 800 Sequence Datasheet 307506-003

Intel® Pentium 4 Processor 6xx Sequence and Intel® Pentium 4 Processor Extreme Edition Datasheet 306382-003

Intel® Pentium 4 Processor 6x1 Sequence Datasheet 310308-002 INTEL CANCELS 4 GHz P4 - Microprocessor Report, novembre 2004

A High Performance180nm Generation Logic Technology, Portland Technology Development, TCAD, QRE, Intel Corporation, Hillsboro,OR

A 130 nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 layers of Cu Interconnects - PortlandTechnologyDevelopment, TCAD, QRE,Intel

Corporation,Hillsboro, OR

A 90-nm Logic Technology Featuring Strained-Silicon, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004

Validating the Intel® Pentium 4 microprocessor, Bob Bentley, Intel Corporation Oregon, USA http://www.anandtech.com/show/1083/2 La cpu mobile Banias ed il Pentium M

Datasheet Intel® 82855PM, 8255GM/GME

Inside Intel® Core™ Microarchitecture, Ofri Wechsler Intel Fellow, Mobility Group Director, Mobility Microprocessor Architecture Intel Corporation

1Intel® Core™2 Extreme Processor X6800? and Intel® Core™2 Duo Desktop Processor E6000? and E4000? Sequences datasheet

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning - Logic Technology Development, Components Research, QRE, OOTCAD, Intel Corp., Hillsboro, OR, U.S.A.

https://it.wikipedia.org/wiki/Core_2_Extreme

Presentazione "Leading at the edge - TECHNOLOGY AND MANUFACTURING DAY" di Kaizad Mistry, Intel®.

https://benchlife.info/intel-z370-q370-b350-h310-pch-for-coffe-lake-04162017/ Cannon Lake PCH H.