4. Different MOS topologies
4.1. Stability
4.1.1. Cascode (unilateralization)
As stated in (2.23), a useful method to increase stability is to improve the reverse isolation. If we consider a single MOS common-source amplifier (CS), it is clear that because of the parasitic capacitance Cgd there is a signal path between output and input, as shown in Fig. 4.1-a. This
capacity stems from the unavoidable diffusion of the drain dopant under the gate oxide, thus realizing an unwanted capacitor with the polysilicon gate. One efficient way to decouple input and output is through the use of a second transistor mounted as common-gate (CG) stacked on the common-source input transistor (Fig 4.1-b). The upper MOS acts as a (current) buffer between the output node and the drain of the input transistor, thus separating them. From another point of view the Miller effect, that “magnifies” the equivalent capacity seen from the input according to the formula: ) 1 ( V gd gs IN C C A C = + + (4.1)
where AV is the voltage gain of the CS, is attenuated. This is done providing a low impedance point
(the source of the CG) to the output of the first transistor (CS) then reducing its voltage gain. This configuration is known as Cascode and is very common in RF input circuits. This technique is known as unilateralization because is intended to force the signal path in only one direction, that is from input to output, reducing s12. A drawback is the presence of the stack that requires supply
voltages relative high. A possible way to solve this problem is making use of folded cascode. In Fig. 4.1-c we propose a folded cascode with a common source NMOS followed by a common gate PMOS. The ideal current source can be replaced by a LC tank resonating at the working frequency in order to diminish the supply voltage.
IN OUT gd C (a) IN OUT gd C (b) bias V gd C (c) bias V IN OUT dd V bias I
Figure 4.1 (a) common source, (b) cascode, (c) folded cascode.
A negative feedback improves the stability as well. Two possible way of doing that is by placing a resistor between drain and gate of the MOS (parallel feedback) or between source and ground (series feedback). The first one works as following: if the gate voltage increases than the drain current will increase as well, so reducing the drain voltage because of the larger drop on the load; since drain and gate are connected by the resistor the gate voltage will be reduced. This behavior makes the system more stable. Similar is the way the source degeneration resistor RS works: if VG is
raised than more current will flow in the transistor, the drop through RS will increase and so VS. As a
result the difference VGS becomes smaller and the initial increase is contrasted. These two
techniques are useful to improve the linearity of the system: they force the system to maintain the same operating conditions, independently from external effects. Consequently circuit parameters such as the gm will remain almost constant.
4.1.2. Neutralization techniques
To cope with the issue of high supply voltage requirements some alternative techniques have been developed. All these avoid the use of stacked transistor. Their common characteristic is that they all neutralize the effect of Cgd (Miller capacitance) by summing two signal path opposite in sign, thus
canceling each other. A first method is applicable only in a differential architecture. It is depicted in Fig 4.2-a. Two additional capacitors are linked as shown, making a positive feedback between output and input. If their size equals that of Cgd than we have canceled any signal return. This
happens only if our positive feedback exactly equals the negative feedback due to Cgd. In case of
mismatch errors between CN and Cgd we can experience an overall positive feedback. This
eventuality is very dangerous because it can cause circuit instability. The same result can be achieved making use of nullifying inductors, as depicted in Fig 4.2-b. The value of the inductor is
chosen in order to resonate with Cgd at the operating frequency. The Cbias capacitor is needed to
separate gate and drain DC voltages. The problem here is a usually very large inductor size, unsuitable for integration. We have found reports of another neutralization technique1 which makes use of a Transformer-Feedback. A feedback between drain and source cancel that of the gate-drain capacitance. The problems arise when we want to integrate the transformer, caused by the great room requirements and the low Q of the inductors. This technique is illustrated in Fig. 4.2-c.
IN1 OUT1 g d C (a) gd C (c) IN OUT dd V g d C IN2 OUT2 N C CN OUT gd C (b) N L bias C IN 1 L 2 L M
Figure 4.2 (a) differential neutralization, (b) tuned inductor, (c) transformer feedback
4.2. Input Matching
When designing a low noise amplifier we should consider many factors. First of all the added noise must be minimized, then we should have acceptable gain, good linearity and input adaptation. The last aspect is very important in order to avoid that part of the incoming signal is reflected back to the antenna and so reducing the signal gain. Another aspect about impedance adaptation is the possible presence of a preselect filter preceding the LNA. In such a case it is very important that the input impedance of the amplifier falls inside the filter specification, otherwise the behavior of the filter can result unpredictable and many detrimental effects may manifest like ripple in the transfer function of the filter. Thus, our task is to obtain the minimum noise figure while having a good impedance adaptation with source (typically 50 O). Unfortunately the impedance value for minimum noise generally differs from that for maximum power transfer. For example, when dealing with MOS Transistors the input impedance of a MOS is inherently capacitive, without real part and generally an inductive source is required to achieve optimal noise performance.2
1 D. J. Cassan, “A 1-V Transformer-Feedback Low-Noise Amplifier for 5-GHz Wireless LAN in 0.18-µm CMOS”
IEEE J. Solid-State circuits, vol. 38, pp. 427-435, March 2003
2
Many possible architectures help us in solving the issue of the input adaptation and low noise. Some of these are represented in Fig. 4.3.
s R p R g L s L
Figure 4.3 Different input topologies
The first one is a very rude approach. Given that the Zin of the MOS is capacitive we could put a
shunt resistor Rshunt of 50 O as shown in figure 4.3-a. However this choice will affect seriously the
noise performance of the amplifier. The reason is the noisy nature of the resistor and its critical position. Using the formula (2.4) we realize that the NF of a component that is at the beginning of an amplifying chain has a great impact on the overall NF. In practice, the minimum achievable noise figure is:
dB R R NF S shunt 3 2 1 min = + = = (4.2)
when the circuit is matched with the source resistance Rs. Moreover we have a signal attenuation of two due to the voltage divider made of source resistance and input resistance. Consequently we will discard this method.
Another technique is that of the “1/gm termination” (Fig. 4.3-b). Here the input is the source of a
MOS, mounted as a Common Gate. As known the impedance seen between its source and ground is
1/gm meaning that we can get the wanted 50 O just selecting the appropriated size and bias current
of the transistor. This approach gives not a significantly low noise figure. The reason is that we have a resistance in the signal path because of the MOS channel, hence we have a NF that is just a little better than the simple termination. In details we have, considering the thermal noise of the MOSFET channel:
dB KTR g KT NF S m 2.2 3 2 1 4 3 8 1 min = + = + = (4.3)
where K is Boltzmann’s constant and Rs the source resistance. The minimum value of 2.2 dB is
reached when the circuit is adapted, i.e. when 1/gm = Rs.
A third way to make adaptation possible is the use of resistive feedbacks, series or parallel (Fig. 4.3-c). This solution affects the noise figure as well because of the noisy resistors. Therefore the feedback enables wideband capabilities for the amplifier. We can limit the negative effect on the NF by using resistor of larger (smaller) value in the case of parallel (series) feedback. Finally, an inductive degeneration technique is proposed (Fig. 4.3-d); this choice is the best one in order to minimize noise thanks to the noiseless nature of (ideal) inductors. With an easy calculation we can show that the input approximated impedance of this configuration is about:
gs s m gs g s in C L g sC L L s Z = ( + )+ 1 + (4.4)
where Ls is the inductance at the source, Lg is the inductance at the gate, Cgs is the gate-source
capacitance of the transistor and gm its transconductance. Once we have chosen the size and the bias
current of the MOS we can set Ls in (4.4) such that the real part of Zin equals 50 O. Than we set the
value of Lg such that the reactive terms resonate (at the operating frequency) thus canceling any
imaginary part. We must observe that the gate inductor will be needed in all the cases so far examined since the input impedance will present always a negative reactance because of the inherent capacitive nature of the MOSFET. On the other hand this possibility has some drawbacks: the real inductors have finite Q, thus they have a parasitic series resistance that affect the NF; it is difficult to integrate inductors because of their huge space requirements and they are far from ideality. From (4.4) we can see that because of the very low value for Cgs (in particular for short
channel MOS) and since Ls is fixed (and very small too) we usually need so large Lg (typically more
than 10 nH) that it becomes difficult to integrate on chip, so raising the costs. As we said, an integrated inductor suffers of a unavoidable internal resistance, whose value is about 1 O for each nH of the inductor. A resistor of a few ohms, placed between the signal generator and the gate of the input transistor has a strong impact on the overall noise and must be minimized.. These inductors can be however off-chip SMD components: this is the best solution, thanks to the good Q
of external components, that means very low series resistances. A smaller die surface will result if we make use of such inductors.
4.3. Noise optimization
4.3.1. Theoretical considerations for MOSFETs
We have seen in 2.1.2 that a generic noisy two-port can be schematized in a very simple way with two equivalent noise generators followed by a noiseless ideal two-port. This model enables us to neglect the real internal noise sources giving us a simplified description of the overall noise of the quadrupole, valid for an analysis of its input-output behavior. Starting with this model we found an useful description with four parameters that can be related to electrical and technological quantities. Since we use MOS transistors for our amplifier we must deduce them considering the typical noise sources of a MOSFET: drain current noise and gate noise. Following the same reasoning as in 2.1.2 we start from the model with these two noise current generators with their correlation coefficient, we calculate the equivalent input noise generators, according to the two-port noise model and hence we finally get the four noise parameters Gc, Bc, Rn, Gu as demonstrated in [3]. The whole
demonstration was omitted because not useful for our purposes. The final results are shown in the table below: Parameter Expression Gc ~0 Bc gs d m C c g g ω γ δ + 5 1 0 Rn 2 0 1 m d g g γ Gu 2 2 0 2 5 ) 1 ( gs d C g c ω δ −
Table 4.1 MOS noise two -port modeling: parameters’ expressions
+ + + = c c n u n G G R G R Fmin 1 2 2 (4.5)
Replacing the parameters according to Tab. 4.1 we realize how we can reduce the noise factor of the MOS. The new expression is now:
) 1 ( 5 2 1 2 min c g C F m gs − + = ω γδ (4.6)
where the terms under the square root are all technological parameters that we cannot modify. We explain their meaning below. Their value is intended for long channel devices, that is for device working with relative low electric fields:
Parameter Expression
0
d
g Drain-source conductance at zero VDS; gd0 ≅ gm
γ Drain current noise coefficient: 1 at zero
DS
V , 2/3 in saturation
δ Gate current no ise coefficient: 4/3 in saturation
C Correlation coefficient between gate and drain noise. Typically j0.395
Table 4.2 Meaning of the technological parameters
In (4.6) we note that the ratio Cgs/gm is approximately 1/?T,3 showing that deeper submicron
technology improve the minimum achievable F. ? is the working frequency (in the range of 2GHz for this work) multiplied by 2p. We can now consider how to reduce the minimum noise factor:
• Increasing the gm. For a MOS in saturation region we have:
D ox m I L W C g = 2µ (4.7)
where µ is the mobility of the charge carrier, Cox is the oxide capacity per unit area, W is the
channel width, L is the channel length and ID the drain current. It is clear that gm raises for
larger W, larger ID and smaller L. We should bias the transistor with the maximum current
3
available according to the specification. The channel length should be the smallest possible (in our design kit 0.12µm).
• Reducing Cgs we improve F as well. A smaller Cgs will diminish gm (through W) too but we
have in (4.6) a proportional dependence in the numerator and a square root dependence in the denominator, as a consequence the net result is a smaller F with a smaller gate-source capacity. We can reduce this capacity by choosing trans istors with small W.
• Decreasing ? . Unfortunately this parameter is bound to the operating frequency given by the specifications, hence it is not modifiable. However it is clear that we can reach best results when working at relative low frequencies.
4.4. Single ended and differential
We have seen that a typical response of a circuit to a signal can be described by the polynomial formula (2.9). A system with an odd symmetry has a response with all the even coefficients (a2, a4,
…) equal to zero, hence only odd harmonics are found at the output when it is driven with
differential inputs. In this case we have that the output to the signal x(t) is the negative of the output of –x(t). A circuit with such symmetry with two inputs is called differential because it amplifies the difference of the inp ut signals. A typical example of differential amplifier is the source coupled pair: two input MOS transistors have the sources connected together and the inputs are their gates (Fig. 4.4-b). L R DD V IN V OUT V L R D D V 2 IN V L R 2 IN V − DD V OUT V (a) (b)
Figure 4.4 Common source: single ended (a) and differential (b)
The great advantage of this architecture is the common mode rejection. The circuit amplifies only the difference of the two inputs; if a common mode signal is present at both gates it will be rejected because the difference between the inputs equal zero. An example of common mode unwanted
signal is the substrate noise of the chip: thanks to the symmetrical layout this noise is present at both inputs in the same quantity, being not amplified. Normally, every unwanted interferer is present in both input terminal with the same phase and will be so theoretically blocked, unless mismatches between the components are present, altering the symmetry. The useful signal is applied so that the phase of one input is shifted of 180° compared with the other. Moreover we have a beneficial effect on the linearity, suppressing all the even order harmonics. The voltage maximum swing of the output signal is doubled in a differential amplifier. For example in Fig 4.4-a the maximum peak-to-peak swing is limited to VDD-(VGS-VT), while in Fig. 4.4-b this quantity is two
times larger, being the difference of the two drain voltages. Major drawbacks of this solution are: greater complexity of the circuit (we must double the amplifying transistors, the load and many other components) meaning a fast doubled area of the chip; the need for a “balun”, a circuit made up with reactive components, whose role is to transform the signal at its input in a couple of signals of opposite sign at its outputs; a doubled current consumption. To understand the last point, look at Fig. 4.4. The CS single-ended architecture (Fig. 4.4-a) gives the voltage gain:
L m IN OUT V g R V V A = = (4.8)
while the differential circuit (Fig. 4.4-b) gives
m L L m L m IN OUT V g R R g R g V V A = − − = = 2 2 2 1 (4.9)
assuming that both transistors are identical and thus having the same transconductance. We see that the gains are the same in both implementations but the second one requires two times more current in order to bias both transistors with that gm.
Some further problems of the basic differential pair we saw so far can be solved with a simple modification. These problems take place in the presence of great variations in the Input Common Mode voltage. If such a variation happen, we experience the following: the bias voltage of the input transistors varies, hence the gm and the bias current of both transistors. As a consequence of the
transconductance variation, the small signal voltage gain changes. The changes in the bias currents cause a variation in the Output Common Mode VDD-RLID, reducing or increasing the output voltage
swing. A new topology, known as “differential pair” avoid these problems (Fig. 4.5). Now the sources are not grounded but connected together with a current generator ISS : this can be easily
realized with a single MOS biased in saturation. Of course this transistor will present a finite output resistance that must be taken into account.
L R 2 IN V L R 2 IN V − OUT V DD V VDD SS I
Figure 4.5 Differential pair with current generator.
If the input voltages are the same (that is without input signal) a current equal to ISS/2 will flow into
each transistor. Consequently: 1. the output common mode level is fixed at VDD-RLISS/2 and 2. The
transconductances do not vary with the input CMs because they are determined by the current generator. Even if this last topology has its advantages we will not use it since it needs a higher supply voltage to bias correctly the added current source MOS.
