17. JTAG Test and Programming Port
17.3. Boundary scan register
All signal pins of the TDC are passed through JTAG boundary scan registers. All JTAG test modes related to the boundary scan registers are supported (EXTEST, INTEST, SAMPLE).
BSR # Pin name Description
[0] token_out LVTTL or LVDS outputs depending on setup
[1] strobe_out LVTTL or LVDS outputs depending on setup
[2] serial_out LVTTL or LVDS outputs depending on setup
[3] test
[4] error
[5] data_ready
[6] parallel_enable enable of parallel_data_out (not direct pin) [38:7] parallel_data_out[31:0]
[39] encoded_control LVTTL or LVDS mode depending on setup
[40] trigger LVTTL or LVDS mode depending on setup
[41] event_reset LVTTL or LVDS mode depending on setup
[42] bunch_reset LVTTL or LVDS mode depending on setup
[43] get_data
[44] serial_bypass_in LVTTL or LVDS mode depending on setup
[45] serial_in LVTTL or LVDS mode depending on setup
[46] token_bypass_in LVTTL or LVDS mode depending on setup
[47] token_in LVTTL or LVDS mode depending on setup
[48] reset LVTTL or LVDS mode depending on setup
[49] aux_clock LVTTL or LVDS mode depending on setup
[50] clk LVTTL or LVDS mode depending on setup
[82:51] hit LVTTL or LVDS mode depending on setup
17.4. ID code
A 32 bit chip identification code can be shifted out when selecting the ID shift chain.
ID[31:0] 10000100011100001101101011001110 Version 1.3 of HPTDC 17.5. Setup registers
The JTAG setup scan path is used to load programming data that can not be changed while the TDC is actively running. No separate update register is implemented on this scan path so reading the information is "destructive". Proposed default values are given in parenthesis when applicable.
[3:0] test_select[3:0] Selection of test output signal (for testing) normal use = 1110
0000 clock_40 0001 pll_clock_40
0010 pll_clock_80
[4] enable_error_mark Mark events with error if global error signal set (1) [5] enable_error_bypass Bypass TDC chip if global error signal set (0)
(overrides enable_error_mark)
[16:6] enable_error[10:0] Enable of internal error types for generation of global error signal (all set)
bit #
0: vernier error (DLL unlocked or excessive jitter) 1: coarse error (parity error on coarse count) 2: channel select error (synchronisation error) 3: l1 buffer parity error
4: trigger fifo parity error
5: trigger matching error (state error) 6: read-out fifo parity error
7: read-out state error 8: setup parity error 9: control parity error
10: jtag instruction parity error
[19:17] readout_single_cycle_speed[2:0] Serial transmission speed in single cycle mode (0) 000: 40 Mbits/s
[23:20] serial_delay[3:0] Programmable delay of serial input (0) Time unit ~ 1ns
[25:24] strobe_select[1:0] Selection of serial strobe type (0):
00: no strobe 01: DS strobe
10: leading and trailing edge (edge) 11: leading edge (clock)
[26] readout_speed_select Selection of serial read-out speed (0) 0: single cycle
(as defined by setup[19:17]) 1: 80 Mbits/s (PLL lock required) [30:27] token_delay[3:0] Programmable delay of token input (0)
Time unit ~ 1ns
[31] enable_local_trailer Enable of local trailers in read-out (1) [32] enable_local_header Enable of local headers in read-out (1) [33] enable_global_trailer Enable of global trailers in read-out (0)
(only valid for master TDC)
[34] enable_global_header Enable of global headers in read-out (0) (only valid for master TDC)
[35] keep_token Keep token until end of event or no more data (1) otherwise pass token after each word read.
Must be enabled when using trigger matching.
[36] master Master chip in token ring (0)
[37] enable_bytewise Enable of byte-wise readout (0) (setup[38] must be 0)
[38] enable_serial Enable of serial read-out (otherwise parallel read-out) (0)
[39] enable_jtag_readout Enable of readout via JTAG (0) (overrides other readout modes) [43:40] tdc_id[3:0] TDC identifier in readout
[44] select_bypass_inputs Select serial in and token in from bypass inputs (0) [47:45] readout_fifo_size[2:0] Effective size of readout fifo (111)
000: 2
[59:48] reject_count_offset[11:0] Reject counter offset
defines reject latency together with coarse count offset [71:60] search_window[11:0] Search window in number of clock cycles
[83:72] match_window[11:0] Matching window in number of clock cycles ( 0 = 25ns, 1 = 50ns, 2 = 75ns , , )
[86:84] leading_resolution[2:0] Resolution of leading/trailing edge (001) used to select bits read out.
000: 100ps (coarse count[11] lost in readout) 001: 200ps
010: 400ps (only useful in pair mode) 011: 800ps (only useful in pair mode) 100: 1.6ns (only useful in pair mode) 101: 3.12ns (only useful in pair mode) 110: 6.25ns (only useful in pair mode) 111: 12.5ns (only useful in pair mode) [114:87] fixed_pattern[27:0] Fixed readout pattern (for debugging)
[27:24] readout_data[31:28]
illegal pattern = 0010
illegal pattern = 0011 [23:0] readout data [23:0]
readout data[27:24] taken from tdc_id
[115] enable_fixed_pattern Enable readout of fixed pattern (for debugging) [119:116] max_event_size[3:0] Maximum number of hits per event (1001)
only valid when using trigger matching 0000: 0
[120] reject_readout_fifo_full Reject hits when read-out fifo full. (1) otherwise back propagate to L1 buffers [121] enable_readout_occupancy Enable readout of buffer occupancies (0)
for each event (debugging).
Only allowed when using trigger matching.
[122] enable_readout_separator Enable read-out of separators (debugging) (0) only valid if generation of separators enabled [123] enable_overflow_detect Enable overflow detect of L1 buffers (1)
(should always be enabled)
[124] enable_relative Enable read-out of relative time to trigger time tag only valid when using trigger matching
[125] enable_automatic_reject Enable of automatic rejection (1)
(should always be enabled if trigger matching) [137:126] event_count_offset[11:0] Event number offset (0)
[149:138] trigger_count_offset[11:0] Trigger time tag counter offset used to set effective trigger latency [150] enable_set_counters_on_bunch_reset
Enable all counters to be set on bunch count reset (1) [151] enable_master_reset_code Enable master reset code on encoded_control (0) [152] enable_master_reset_on_event_reset
Enable master reset of whole TDC on event reset (0) [153] enable_reset_channel_buffer_when_separator
Enable reset channel buffers when separator (0) [154] enable_separator_on_event_reset
Enable generation of separator on event reset (0) [155] enable_separator_on_bunch_reset
Enable generation of separator on bunch reset (0) [156] enable_direct_event_reset Enable of direct event reset input pin (1)
otherwise taken from encoded control [157] enable_direct_bunch_reset Enable of direct bunch reset input pin (1)
otherwise taken from encoded control [158] enable_direct_trigger Enable of direct trigger input pin (1)
otherwise taken from encoded control [167:159] offset31[8:0] Offset adjust for channel 31
[176:168] offset30[8:0] Offset adjust for channel 30 [185:177] offset29[8:0] Offset adjust for channel 29 [194:186] offset28[8:0] Offset adjust for channel 28 [203:195] offset27[8:0] Offset adjust for channel 27 [212:204] offset26[8:0] Offset adjust for channel 26 [221:213] offset25[8:0] Offset adjust for channel 25 [230:222] offset24[8:0] Offset adjust for channel 24 [239:231] offset23[8:0] Offset adjust for channel 23 [248:240] offset22[8:0] Offset adjust for channel 22 [257:249] offset21[8:0] Offset adjust for channel 21 [266:258] offset20[8:0] Offset adjust for channel 20 [275:267] offset19[8:0] Offset adjust for channel 19 [284:276] offset18[8:0] Offset adjust for channel 18 [293:285] offset17[8:0] Offset adjust for channel 17 [302:294] offset16[8:0] Offset adjust for channel 16 [311:303] offset15[8:0] Offset adjust for channel 15 [320:312] offset14[8:0] Offset adjust for channel 14 [329:321] offset13[8:0] Offset adjust for channel 13 [338:330] offset12[8:0] Offset adjust for channel 12 [347:339] offset11[8:0] Offset adjust for channel 11 [356:348] offset10[8:0] Offset adjust for channel 10 [365:357] offset9[8:0] Offset adjust for channel 9 [374:366] offset8[8:0] Offset adjust for channel 8 [383:375] offset7[8:0] Offset adjust for channel 7 [392:384] offset6[8:0] Offset adjust for channel 6 [401:393] offset5[8:0] Offset adjust for channel 5 [410:402] offset4[8:0] Offset adjust for channel 4 [419:411] offset3[8:0] Offset adjust for channel 3 [428:420 offset2[8:0] Offset adjust for channel 2 [437:429] offset1[8:0] Offset adjust for channel 1 [446:438] offset0[8:0] Offset adjust for channel 0 [458:447] coarse_count_offset[11:0] Offset for coarse time counter [554:459] dll_tap_adjust[95:0] Adjustment of DLL taps (0)
resolution: ~10ps [2:0]: tap 0 [5:3]: tap1 -[95:93]: tap 31
normal use: all adjustments can be set to zero [566:555] rc_adjust[11:0] Adjustment of R-C delay line..
rc_adjust[2:0] = tap1 (7) rc_adjust[5:3] = tap2 (7) rc_adjust[8:6] = tap3 (4) rc_adjust[11:9] = tap4 (2)
only needed in very high resolution RC mode
[569:567] not used (rc_adjust 14:12)
[570] low_power_mode Low power mode of channel buffers (1)
(rc_adjust[15])
[574:571] width_select[3:0] Pulse width resolution when paired measurements 0000: 100ps
[579:575] vernier_offset[4:0] Offset in vernier decoding (0) fixed value = 00000
[583:580] dll_control[3:0] Control of dll (update)
DLL charge pump levels (0001) [585:584] dead_time[1:0] Channel dead time between hits (0)
00: ~5ns 01: ~10ns 10: ~30ns 11: ~100ns
[586] test_invert Automatic inversion of test pattern (0) only used during production testing normal use = 0
[587] test_mode Test mode where hit data taken from coretest. (0) Only used during production testing
normal use = 0
[588] enable_trailing Enable of trailing edges [589] enable_leading Enable of leading edges
[590] mode_rc_compression Perform RC interpolation on-chip.
only valid in very high resolution mode
[591] mode_rc Enable of R-C delay line mode (very high res. mode) only channel 0,4,8,12,16,20,24,28 active
[593:592] dll_mode[1:0] Selection of DLL speed mode (update) 00: 40MHz
01: 160MHz 10: 320MHz 11: illegal
must match selected clock speed for DLL [601:594] pll_control[7:0] Control of PLL (update)
[4:0]: charge pump current (00100) [5]: power down mode (0)
[6]: enable test outputs (0)
[7]: invert connection to status[61]
[605:602] serial_clock_delay[3:0] Delay of internal serial clock (update) (0) [3]: 0 direct clock
1 delayed clock
[2:0]: delay in step of typical 0.13 ns normal use: fixed pattern = 000 [609:606] io_clock_delay[3:0] Delay of internal io clock (update) (0)
[3]: 0 direct clock 1 delayed clock
[2:0]: delay in step of typical 0.13 ns normal use: fixed pattern = 000
[613:610] core_clock_delay[3:0] Delay of internal core clock (update) (0) [3]: 0 direct clock
1 delayed clock
[2:0]: delay in step of typical 0.13 ns normal use: fixed pattern = 000
[617:614] dll_clock_delay[3:0] Delay of internal dll clock (update) (0) [3]: 0 direct clock
1 delayed clock
[2:0]: delay in step of typical 0.13 ns normal use: fixed pattern = 000
[619:618] serial_clock_source[1:0] selection of source for serial clock (update) (0) 00: pll_clock_80
01: (pll_clock_160), not valid 10: (pll_clock_40), not valid 11: aux_clock (only for testing) normal use: fixed pattern = 00
[621:620] io_clock_source[1:0] Selection of clock source for IO signals (update) (0) 00: clock_40
01: (pll_clock_80), not valid 10: (pll_clock_160), not valid 11: aux_clock (only for testing) normal use: fixed pattern = 00
[623:622] core_clock_source[1:0] Selection of clock source for internal logic (update) 00: clock_40
01: pll_clock_80
10: pll_clock_160 (only valid for speed graded ICs) 11: aux_clock (only for testing)
normal use: fixed pattern = 00
[626:624] dll_clock_source[2:0] Selection of clock source for DLL (update)
000: clock_40 (low resolution mode with direct clock) 001: pll_clock_40 (low resolution with PLL clock) 010: pll_clock_160 (medium resolution)
011: pll_clock_320 (high resolution) 100: aux_clock (only for testing) [638:627] roll_over[11:0] Counter roll over value. ( FFF hex)
defines max count value from where counters will go to zero.
[639] enable_matching Enable of trigger matching
[640] enable_pair Enable pairing of leading and trailing edges
(overrides individual enable of leading/trailing edges) not allowed in very high resolution RC mode
[641] enable_ttl_serial Enable LV TTL input on:
serial_in
serial_bypass_in token_in
token_bypass_in Otherwise uses LVDS input levels Disables LVDS drivers on:
serial_out strobe_out token_out [642] enable_ttl_control Enable LV TTL input on:
trigger bunch_reset event_reset encoded_control otherwise uses LVDS input levels [643] enable_ttl_reset Enable LV TTL input on: reset
otherwise uses LVDS input levels [644] enable_ttl_clock Enable LV TTL inputs on: (update)
clk
aux_clock
otherwise uses LVDS input levels [645] enable_ttl_hit Enable LV TTL input on: hit[31:0]
otherwise uses LVDS input levels [646] setup_parity Parity of setup data (even parity) 17.6. Control registers
The JTAG control scan path is used to enable/disable channels which can be done while the TDC is actively running. The control scan path is also use to initialize the PLL and DLL after power up. A global reset (equivalent to asserting the reset pin) can be issued to initialize the global state of the TDC after power up and reconfiguring.
[3:0] enable_pattern[3:0] Specific pattern = 0101 required to enable drivers on parallel readout bus.
Specific pattern = 010x required to get out of power-down mode.
JTAG trst sets enable_pattern[3] to 1.
see Power up mode on page 26
[4] Global_reset Global reset of TDC via JTAG.
(must be set to one and returned to zero) [36:5] enable_channel[31:0] Enable/disable of individual channels
[37] dll_reset Reset of DLL
(must be set to one and returned to zero)
[38] pll_reset Reset of PLL
(must be set to one and returned to zero) [39] control_parity Parity of control data (even parity)
17.6.1.Reset of PLL and DLL.
The PLL and the DLL is not initialized when a global reset of the TDC chip is performed.
The lock tracing of the PLL/DLL is a rather slow process (few ms) and is only required to be performed once power and a stable clock have been applied.
A reset of the PLL and DLL must be performed via the JTAG control scan path after power up. The PLL must first be initialized and obtain lock before the DLL can be initialized. Their correct parameters in the setup scan path must have been loaded before they can be initialized via their respective reset bits in the control scan path. Reloading new setup data may result in the DLL and PLL losing lock.