TAG
2.3. Design goals and strategies 19
1. Quiet: a quiet time interval where no backscatter occurs.
2. Preamble: A known start-of-transmission bits packet.
3. Data: Data fields, according to the previous reader request. Typ-ically contains the tag unique identification code.
4. CRC-16: Control sequence.
2.3 Design goals and strategies
The proposed tag should be ready to enter the supply chain man-agement RFID market. Since, as described in Chapter 1, the best transponder tipology to be employed in such a field is the passive electromagnetic one, it should exhibit performances comparable to the ones of the tags of the same category already present on the mar-ket, at a lower cost.
In order to perform a comparison with the already available — or announced — products, the main parameter taken into account is the reading range. Obviously, such a comparative test must be done in the same operating conditions for every device. Many results found in literature have therefore to be reported to the adopted standard regulations: although this procedure may experience a certain ap-proximation, the comparison is still fair enough.
Besides the free-space propagation hypotesis and the ISO18000-6B and ETSI regulations described in the previous sections, the only operating condition to be set is the working temperature range. The supply chain applications that the tags are designed for do not require extreme values, especially for the food industry where rarely temper-atures exceed some dozens degrees. A quite expanded range has been considered, spanning from 0 to 85 ˚ .
In order to reduce the production costs, in the tag design the fol-lowing guidelines have been considered:
• Reducing the number of components. Manufacturing costs expe-rience a noticeable dependency on the number of discrete ob-jects to be included on-board: although the price of common devices like SMD capacitors or inductors is extremely low, the PCB mounting and testing procedures exhibit a non-negligible impact on the product cost. Therefore, specific techniques must be employed in order to reduce the tag components to the small-est possible amount, that is 2: the antenna and the chip.
• Cutting the chip production costs.
The price-per-tag can be highly reduced by adopting a low-cost, general purpose and relatively old technology for the chip fabrication, although the design of the analog blocks may suffer from the devices non-optimal performances and the absence of specific process options: such limitations must be overcomed with a smart design.
It is preferrable to employ the chip-on-board strategy: the die is directly attached to the antenna. Besides the advantages com-ing from reduced parasitics effect and small size and thickness, the expenses due to the package are utterly removed. Bonding is still present, although in this case the pads are immediately connected to the PCB surface.
The chip area must be minimized.
Special care in the circuit design must be taken in order to avoid any unnecessary post-fabrication operation, like wafer sort trimming to compensate the process variations.
The reading range can be maximized by designing an efficient power rectification network and cutting the current consumption of the main circuits, i.e. the design is driven by low-power constraints, with the limitations due to the abovementioned low-cost policies. The following chapters will describe in detail the adopted design tech-niques.
2.4. Tag structure and components 21
2.4 Tag structure and components
According to the guidelines exposed in Section 2.3, the designed tag is made up of a planar antenna and the chip (object of this work). Since there are no other components, the only connections to be made are between the antenna terminals and two I/O pads on the die.
2.4.1 Antenna properties
Although the physical design of the printed antenna (and thus its size, type and material) is a part of the project not covered by this work, the design provides its electrical characterization.
In fact, in order to transfer the maximum power that can be har-vested from the RF field to the tag, the condition of impedance match-ing must be met between antenna and chip. Such a constraint means that the antenna has to be realized in a way that its impedance value is equal to the complex conjugate of the chip one [10]. The latter is basically determined by the devices present between the two chip in-puts, as better explained in Section 3.4, and is typically composed of a real (resistive) and a negative imaginary (capacitive) part, allowing hence to model the chip with aRIN− CIN equivalent series circuit.
Therefore, the power matching can be achieved by setting the an-tenna equivalent resistance RAN T to be equal to RIN, while CIN has to be balanced with an equivalent inductor L, as shown in Fig. 2.6.
Since an accurate design allows to keep the inductance value as low as few dozens nH, there is no need to place an inductor as exter-nal component, that would basically add an undesired extra cost. As a matter of fact, an inductive antenna can be designed by setting its resonance frequency fAN T slightly above the one of the RF car-rier used in the communication (i.e. f =869.5MHz): a careful antenna design can thus grant the power matching condition without adding extra components.
If the matching condition is met (RAN T = RIN andωL = (ωCIN)−1), the Friis equation in (2.6) can be used without introducing any