Implementations

The described requirements were implemented starting to analyze the timing constraints on the acquisition of the phase currents because more critical with respect to other groups of signals from the control point of view. In Fig. 3.7, their timing constraints are reported graphically. As is shown in the figure, the center of

the T_ON period is a constraint about the time instant when to start the conversion due to the available hardware features. Since the switching frequency was set equal to 16kHz to simplify the implementation, these time instants were chosen to acquire the signals. This time instant corresponds to the event of reaching the highest value of the carrier waveform used as timebase for the PWM generation. For this reason, this event is utilized to signal to the BCTU when to start the conversion of the first elements of the conversion list which are constituted by the 3 phase currents.

0 Ts/2 Ts 3Ts/2 2Ts 5Ts/2 3Ts

Time [s]

0 1 2 3 4 5 0 1 2 3 4 5

Voltage [V]

T₁ T₁

T_sw

Figure 3.7: Timing constraints of the phase currents acquisition.

In order to acquire the three phase currents simultaneously, all the 3 SAR-ADCs hardware instances were used - one ADC for each signal. The SAR-ADCs were configured to be triggered by the BCTU, and the BCTU was configured to trigger the ADCs using a conversion list. The use of a conversion list allows multiple parallel conversions which are required for simultaneous acquisitions. The list was implemented using specific configuration registers that set which channels and ADCs has to be triggered for the conversion. The ADC selection is done by means of the register TRGCFG that contains 1 for each ADC to be set or cleared depending on the need to trigger on not the corresponding ADC. As is shown in Fig. 3.8, channels in the conversion list are grouped together in 2 or 3 elements if more than one ADC are selected. The registers LISTCHR_i allow the definition of the elements in the conversion list - each register can contain two elements and provides two bits per element to set if the element is the last in the list and to insert a waiting for another trigger source event to continue the conversions. Therefore, all analog signals of the groups of Table 3.3 were listed according to their priorities and requirements.

Figure 3.8: Logic diagram of the multiple parallel conversions list operations implemented by the BCTU.

The raw converted data are read by means of interrupts. More precisely, an interrupt, associated to the BCTU peripheral, is set in correspondence of the end of conversion of the last element in the conversion list. The corresponding interrupt handler is responsible to read the raw converted data and scale them from uint16_T (16 bit unsigned integers) to real32_T (float) variables with the correct measurement unit. Since the BCTU trigger event the instant T₁ in Fig.

3.7, the conversion of the elements in the list is performed every time the signals with the highest sample rate have to be acquired. This causes that all signals are converted with a sampling frequency of 16kHz which is higher than the required for the system temperatures signals. For this reason, even if their real sample rate is 16kHz, they are read in the BCTU interrupt handler in such a way to guarantee their nominal sampling rate and reduce the computational effort of the BCTU interrupt handler.

The reading of the raw converted results in the BCTU interrupt handler in-troduces a delay between the moment when the analog signals are converted and the moment when they are effectively read. Since the control algorithm in the application software needs these data to be executed, they shall be read before the beginning of each PWM switching period. Therefore, the maximum possible delay for the selected example frequency is a switching period that is equal to

d^max = 1

f_sw = 1

16kHz = 62.5µs . (3.1)

For this reason, to verify the feasibility of this approach, the introduced delay was

analyzed and estimated according to the expressions reported in the MCU reference manual. The conversion time of the i-th triple of channels (three signals at time are converted due to the multiple parallel conversions feature) is given by the following expressions:

t⁽ⁱ⁾_conv=

C

1ST + PST + CT + DP²+ TPT

D

× TAD_clk, (3.2) where the terms in the expression are:

• ADC Clock Cycles (TAD_clk)

The TAD_clk is the time period of an AD_clk cycle and corresponds to the inverse of the clock frequency provided to the ADC peripherals. Since the clock signal provided to ADC peripherals has a frequency of 80Mhz, the value of TAD_clk is 12.5ns.

• Sample Phase Time (ST)

The sample time is controlled by writing the the bit field of the configuration register INPSAMP[7:0] with an 8 bits value which represents units of AD_clk cycles. The minimum value of sample time is eight. If the value programmed is less than 8 then it has no effect on sample time duration and in this case sample time will be 8 AD_clk cycles. In this context, the ST was chosen by trial and error procedure and set to 100.

• Pre-Sample Phase Time (PST)

The pre-sample phase time is equal to sample time with one AD_clk cycle delay for phase transition from pre-sample phase to sample phase.

• Compare Phase Time (CT)

The compare phase time is affected by the evaluation time of a single bit and number of bits to be converted. For N bit conversions the value of CT will be N multiplied by the evaluation time of a single bit in terms of AD_clk cycles. The evaluation time of a single bit is estimated to 4 AD_clk in the MCU datasheet. Since the resolution of the SAR-ADCs is 15 bits, the CT was estimated to be equal to 60 ADC_clk cycles.

• Data Processing Time (DP)

The data processing time is 2 cycles of AD_clk which are necessary to correct raw converted data from offset, gain, capacitor mismatch, etc.

• Trigger Processing Time (TPT)

The trigger processing time consists in preparing the channel and calculating the initial gain value, and BCTU triggering time. It corresponds to about 1 AD_clk cycle and depends on the BCTU configuration.

t⁽ⁱ⁾_conv =

C

1100 + 101 + 60 + 2²+ 1

D

× 12.5ns = 3.3µs . (3.3) To compute the total conversion time, the structure of the conversion list has to be analyzed. As described before, the BCTU triggers the start of conversion of the channels in the conversion list. Since ADC0, ADC1, and ADC2 are used, the list elements are grouped by 3, assigning one element for each converter. Same spare channels were inserted in the conversion list because some signals (mainly not critical ones) were assigned to be converted by ADC0 even if ADC1 and ADC2 were free and available to be used. In those cases, a spare channel was inserted to maintain the alignment of the multiple parallel conversions of 3 channels at time.

Of course, converted values of these channels aren’t read in the dedicated interrupt handler because meaningless. This isn’t the best solution for the project, but it was necessary to avoid the on-run reconfiguration of the BCTU peripheral. Since conversion list is structured to perform 9 multiple parallel conversions, the total conversion time was estimated to be equal to:

t_conv = n_list× t⁽ⁱ⁾_conv= 9 × 3.3µs = 29.7µs , (3.4) with n_list the number of the multiple parallel conversions.

The acquired values shall be provided to the application software. For this reason, the interrupt handler, that is run at the end of the conversion of the last list element, is responsible to move the results of the conversions in well-organized and global accessible data structures which field are mapped from uint16_T to real32_T data when read by the application software. These data structures represents the data exchange interface between the AdcMgm software component and the application software and they are described in the following section.