OFF-State Reliability of pGaN Power HEMTs

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Alma Mater Studiorum - Universit`a di Bologna campus di cesena

DIPARTIMENTO DI INGEGNERIA DELL’ENERGIA ELETTRICA E DELL’INFORMAZIONE “GUGLIELMO MARCONI”

CORSO DI LAUREA MAGISTRALE IN

INGEGNERIA ELETTRONICA E TELECOMUNICAZIONI PER L’ENERGIA

TITOLO DELLA TESI:

OFF-STATE RELIABILITY OF pGaN

POWER HEMTs

Tesi di Laurea Magistrale in

TECNOLOGIE ELETTRONICHE PER L’INFORMAZIONE E L’ENERGIA LM

Relatore:

Dr. ANDREA N. TALLARICO

Correlatore:

Dr. Ir. NIELS POSTHUMA

Presentata da: MAURIZIO MILLESIMO

III Sessione - II Appello

Anno Accademico 2018/2019

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Acknowledgements

First of all, I would like to express my gratitude to my supervisor, Dr. A.N. Tallarico. I appreciate his guidance in the GaN devices world and, in partic-ular, in the reliability field. I would like to thank him especially to gave me the opportunity to do an internship at imec (Leuven, Belgium).

Special thanks to my daily supervisor at imec, Dr. Niels Posthuma for the interest in my work and for the support given during my stay at imec.

Il pi`u grande ringraziamento va ai miei genitori. Grazie per aver creduto sempre in me e per aver appoggiato ogni mia scelta.

Thank you all, Maurizio

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Abstract

The concern for climate changes and the increase in the electricity demand turned the attention towards the production, sorting and use of electric en-ergy through zero emission (CO2) and highly efficient solutions (e.g. for

electric vehicle), respectively. In such a scenario, power converters and/or inverters play a fundamental role, since they represent the main core of power applications. As a consequence, the need for high performance, reliable and low cost power transistors is increasing as well. The most used semiconductor materials for power transistors are three: silicon (Si), silicon carbide (SiC) and gallium nitride (GaN). Among all of them, gallium nitride, seems to be the most promising candidate for the next generation of devices for power electronics, thanks to its excellent properties and comparable cost with re-spect to Si counterpart. The main and most adopted GaN-based device is the high electron mobility transistor (HEMT). In particular, in the case of switching power applications, HEMTs are repeatedly switched between high current on-state and high voltage off-state operation. For both operating modes a good reliability must be guaranteed.

This thesis is focused on the reliability issues related to the off-state oper-ation. The results have been obtained during a six months research period at imec (Leuven, BE) on 200V p-GaN gate AlGaN/GaN HEMTS. Differ-ent devices have been investigated, differing for gate-to-drain distance, field plates lengths, AlGaN and GaN layers properties. Time-dependent dielectric breakdown and hard breakdown tests have been performed in combination with TCAD simulations. It has been demonstrated that the gate-to-drain distance (L_GD) impacts the breakdown voltage and the kind of failure mech-anism. If LGD ≤ 3µm the breakdown occurs through the GaN channel layer

due to short channel effects. In this case, by reducing the thickness of the GaN channel layer such behaviour can be attenuated, eventually leading to longer time-to-failure. If LGD ≥ 4µm the breakdown occurs between the

2DEG and the source field plates, where the properties of the AlGaN barrier layer (i.e. thickness and Al concentration) and the field plates configuration play the main role on the time-to-failure.

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Chapter 1 Introduction

With increasing world population and the request for higher living standard, the demand for electricity is increasing as well. The worldwide electricity can be produced by the adoption of different sources as shown in figure 1.1, with fossil fuels representing the most adopted ones.

Figure 1.1: Worldwide electricity production by various sources [1].

The earth has large reserves of fossil fuels, however, their adoption re-sults in waste products, which added to those produced for transport, do-mestic heating, etc. represent the main source of pollution that contribute

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to climate change problem. To this purpose zero-emission solutions are be-ing implemented to protect the environment (e.g. electricity production by means of renewable sources and replacement of powered fuels vehicles with electric/hybrid engines).

In this scenario, power electronics plays an important role since most of the electricity is controlled by semiconductor power devices. Today, with the advancement of technology, the size and the price of semiconductor power devices are decreasing, leading power electronics to cover a wide range of application fields such as aerospace, automotive, energy saving, industrial, commercial, smart houses, etc..

1.1 Semiconductor Power Devices

Technolo-gies

Until a few years ago, the semiconductor power devices market was com-pletely dominated by the mature silicon (Si) technology because of the low cost and good reliability.However, with the increasing demand for lightweight, compact and evermore efficient power applications, the intrinsic limits of Si (i.e. limited switching frequency, blocking voltage and temperature capabil-ity [2]) arise the need to move towards wide bandgap semiconductors, like gallium nitride (GaN) and silicon carbide (SiC), that exhibit superior mate-rials properties compared to silicon counterpart.

Figure 1.2: Application fields of the different technologies (Si, SiC and GaN) as a function of operating frequency and power [3].

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In figure 1.2 the application fields of Si, SiC and GaN power devices are shown as function of the operating power and switching frequency. In partic-ular,SiC and GaN are the best candidates for high voltage and high frequency operation, respectively, while silicon still preferred for low voltage and low frequency operation.The reason of this division will be further supported in the section 1.1.1.

1.1.1 Material Properties

The application field of Si, SiC and GaN strongly depend on their intrinsic material properties which are useful for switching power applications. In particular the most important characteristics are [4], [2]:

• bandgap: wider bandgap implies lower intrinsic carrier concentration (ni), which is strongly dependent on the temperature and correlated to

leakage current [2]. As a consequence, wider bandgap allows devices to operate at higher temperatures;

• critical electric field: higher critical field means that the impact ion-ization, hence the avalanche-induced breakdown, occurs at higher volt-ages;

• thermal conductivity: larger thermal conductivity implies that the de-vice can withstand a higher power density;

• carrier velocity saturation: higher carrier saturation velocity implies a higher frequency of switching at higher voltages (Jhonson’s FOM [4]). • electron mobility: higher electron mobility leads to lower resistivity and

conduction losses;

Table 1.1 shows the various key material parameters for power electronics of the different materials for power electronics. GaN and SiC feature a bandgap

∼_{3 times higher than Si which lead to have higher electric breakdown field}

(EC) and lower intrinsic carrier concentration useful to have negligible leakage

currents at high operation temperature. Among all the materials, SiC has the highest thermal conductivity making it the best choice for high voltage and power operation, while, GaN is the best candidate for high frequency and high current operations since it has the highest electron mobility (µ) and velocity saturation (vsat). Finally, for low voltage and frequency applications

silicon is the best choice thanks to its low cost and reliability, even though it has less attractive features for power electronics compared to GaN and SiC.

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Parameter Units Si GaAs 4H-SiC GaN Bandgap (EG) eV 1.12 1.42 3.26 3.49 Intrinsic carrier concentration (ni) /cm3 _1.4x1010 _2.1x10−6 _8.2x10−9 _1.9x10−10 Electric break-down field (EC) MV/cm 0.23 0.4 2.2 3.3 Saturated elec-tron velocity (vsat) cm/s 1x107 1x107 2x107 2.5x107 Thermal con-ductivity (k) W/cm-k 1.5 0.5 3.8 1.53 Electron mobil-ity (µ) cm2_/V-sec ₁₄₀₀ ₈₅₀₀ ₉₅₀ ₁₈₀₀ Relative dielec-tric constant(r) - 11.8 12.8 9.7 9

Table 1.1: Comparison of material properties among different semiconductors [4].

1.1.2 Figure Of Merit (FOM)

The choice of a semiconductor for the realization of a power device is made considering several figures of merit [5], which are related to the material prop-erties discussed in the section 1.1.1. The Johnson’s figure of merit (JFOM) [6] defines a value for the high frequency handling capability of a semiconductor being proportional to the saturation velocity and critical electric field:

J F OM = EC · vsat

2π (1.1)

The high power handling capability is described by Baliga’s figure of merit (BFOM) [7] that quantifies the conduction losses in DC operation, which is calculated based on the relative electric permittivity (r), electron mobility

(µ) and bandgap (EG):

BF OM = r· µ · EG3 (1.2)

Instead, to quantify the conduction losses in high frequency operation, and therefore, to evaluate the high power and frequency performance the Baliga’s High Frequency FOM (BHFFOM) is used [5]:

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Considering these three FOMs, among the semiconductors taken into con-sideration, gallium nitride has the best performance although silicon carbide features similar FOMs, while, silicon and gallium arsenide have too low FOM for power applications.

SiC is the semiconductor that has the best Keyes FOM (KFOM) [5] because takes into account the thermal conductivity (k) and it describes the thermal performance of the devices during switching operation:

KF OM = k ·r c · vsat 4πr

(1.4)

1.1.3 Breakdown Voltage and On Resistance

For power applications the most important parameters are the breakdown voltage (VBD) and the on resistance (RON) to have high blocking voltage

capability and low conduction losses, respectively. In fact, their adoption is useful to compare the performance of different power device technologies and architectures by using the relationship VBD2/RON [8]. Power devices must

be able to support high voltages across a depletion region formed, in most case, at a P-N junction. Therefore, to analyze the relationship between VBD

and RON a simple PN junction (figure 1.3 (a)) can be considered.

Figure 1.3: Electric field distribution in a reverse biased P+ /N junction [8] (a) and specific ON-Resistance versus breakdown voltage (theoretical limits) of different semiconductor (b) [9] .

When the junction is reverse biased (positive voltage applied to the N side) the depletion region expands mainly in the N side (since the P region

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is strongly doped) with the consequently generation of a strong electric field. As shown in figure 1.3 (a) the peak of the electric field occurs in the proximity of the PN junction and, according to Poisson’s equation, it can be computed as follow [8]:

Emax=

qNDWD

0r

(1.5) where ND and WD are the doping concentration and the maximum extension

of the depletion region, while,0 andrare the dielectric vacuum constant and

the dielectric constant relative to the material, respectively.

Any electrons or holes that enter the depletion region are swept out by the electric field and as the electric field increase the mobile carriers are pushed out with a higher velocity. If the electric fields is sufficiently high, electrons and holes acquire sufficient kinetic energy to create new electron-hole pairs due to energy loss caused by interaction with the lattice. This phenomenon, namely, impact ionization is a multiplicative mechanism which produces an increasing amount of mobile charges with a consequent increase in the current through the depletion region. This latter leads to the avalanche breakdown that strongly depends on the applied electric field and it occurs when the Emax approaches to the critical electric field (EC). The occurrence of the

latter condition defines the breakdown voltage, defined as: VBD = 1 2ECWD = 1 2 qNDWD2 0r (1.6) The specific ON resistance, which is mainly dominated by the resistive com-ponent of the N-drift region in ON-State operation is equal to:

RON,sp = ρWD =

WD

qµnND

(1.7) Replacing WD and ND from Eq. 1.5 and Eq. 1.6 into Eq. 1.7 it is

pos-sible notice the mutual dependence between ON-resistance and breakdown voltage::

RON,sp =

4V_BD2 0rµnEC3

(1.8) Being RON and VBD dependent from the intrinsic properties of the

ma-terials, it is possible to analytically calculate the theoretical limits for each semiconductor-based technology, as shown in figure 1.3 (b). By observing Fig. 1.3(b), it is worth noting that the theoretical limits are computed con-sidering only the ON resistance of the drift region, which dominant but not the only one, devices are far away from their theoretical limits. Moreover, in

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the case of GaN-devices this difference can be even larger since the break-down voltage during OFF-state operation can be caused by additional failure mechanisms (detailed in the next chapter), anticipating the breakdown in-duced by impact ionization.

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Chapter 2 III-N materials and devices

Gallium nitride and its related alloys (e.g. AlxGa1−xN) are promising

candi-dates for the next generation of high power and high frequency devices due to their excellent material properties. As already mentioned, the wide band gap of these materials leads to have a low intrinsic concentration and, conse-quently, a low leakage current that allows high temperature operation. An-other important feature of GaN is the high breakdown voltage which results in the possibility to fabricate smaller devices, hence characterized by lower on resistance and lower parasitics (mainly capacitances) which can be detrimen-tal for both static and dynamic operation operation mode. Compared to their silicon counterparts, GaN-based devices have a higher switching frequency due to combined effect of higher carriers velocity saturation and smaller area, and a lower resistance due to the high mobility of the two dimension electron gas (2DEG) that appears in the AlGaN/GaN heterostructure [10],[11]. The AlGaN/GaN heterostructure is the main core of the GaN transistors, namely high electron mobility transistor (HEMT), where the electron current flows through the 2DEG from source to drain contacts.

Producing an emerging micro-scaled semiconductor device, the control and mastering of thin film techniques are essential. This includes metallization, dielectric layers, passivation layers or high quality crystalline functional lay-ers. The crystalline layers are deposited by epitaxy starting from the sub-strate. Usually, the substrate and the crystalline layer are made of different materials characterized by different lattice constants and thermal expansion coefficients. This situation is usually called heteroepitaxy that leads to con-sequences like the formation of threading dislocation, buildup of strain, and reliability issues. These physical consequences, that involve reliability prob-lems for the devices, could be reduced using homoepitaxy (epitaxy with same materials) but, unfortunately, nature does not provide GaN bulk crystal. Although some GaN wafers grown with HVPE [12] showed extremely low

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residual impurity concentration , the challenges of high cost and small wafer diameter remain open. Moreover, homoepitaxy has a lot of mismatch issues due to the different growth processes of the GaN layer. The only alternative is to look for foreign materials for substrates that have lattice parameters and crystal structures and orientation close to GaN material. Native substrates are mandatory only for some specific applications who claim high reliability (like in the case of blue and ultraviolet semiconductor lasers) since optimiz-ing the design of the devices it is possible to achieve a good reliability [13]. Despite its incredible characteristics, gallium nitride has many issues as the presence of nitrogen or the lack of a native substrate that will be discussed in along this chapter.

2.1 Substrates for III-N Epitaxy

The choice of substrate and material for GaN-based devices strongly depends on the field of application. Today, GaN wafers can be manufactured, but, have high costs and are only avaiable with limited wafer diameters, maximum 2 inch. GaN is very difficult to growth as a single crystal since it is strongly covalent bonded and contain nitrogen (N) that cannot be melted due to its high melting point above 2000◦C and high equilibrium pressure around 60 kbar; moreover, the solubility of nitrogen in a pure gallium melt is very low [14]. This makes it impossible to grow a GaN crystal with classical melt-based methods like Czochralski pulling, vertical gradient freeze technique, etc. Today, the GaN wafers (expensive and size-limited) are manufactured with solution growth methods (addition of solvent to improve the solubility) and the GaN is crystalized from the vapor phase with two main methods: HVPE (hydride vapor phase epitaxy) and OVPE (oxide vapor phase epi-taxy).

To overcome these limitations and to reduce the overall device costs, GaN devices are currently and mainly grown on foreign substrates.

For optoelectronics, sapphire is the best choice since it has a good match to GaN in terms of lattice constants and thermal expansion coefficient. Fur-thermore, sapphire substrates are transparent, cheap and they have the same threading dislocation densities as the Si and SiC substrates (2.1). As disad-vantages, sapphire has low thermal conductivity and insulating properties, making it less attractive for power electronic applications in order to prevent overheating and premature device failure [15]. Sapphire wafers exist in large diameters, but layers growth on large area is challenging due to the wafer bowing and/or cracking after cooling because of tensile stress for between epitaxial layers.

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Sapphire SiC Si GaN Lattice mismatch

(percent-age)

16 3.1 -17 0

Linear thermal expansion coefficient (x10−6 K−1)

7.5 4.4 2.6 5.6

Thermal conductivity (W cm−1 K−1 )

0.25 4.9 1.6 2.3

Cost Low High Very

Low

Very High

Table 2.1: Properties for different substrates for GaN epitaxy [14], [16]. Among the three foreign substrates reported in table 2.1, SiC is the one with the best matched mechanical properties with GaN. It is available both as n-type and semi-insulating material and it has high thermal conductivity which makes it the best candidate for electronic applications with high power densities. As drawbacks, it has very high costs of fabrication and and the largest available wafer diameters are 6 inch.

For GaN heteroepitaxy, the most used material for the substrates is silicon because of its lowe cost and compatibility with CMOS technology. Epitax-ial growth of GaN directly on Si substrates is more challenging than het-eroepitaxy on sapphire or silicon carbide due to large lattice and thermal mismatches that results in large strain accumulation in the upper III-N epi-layers. This problem, if not properly monitored, leads to wafer deformation, cracking up to breakage, threading dislocations, etc. However, the advan-tages of a low substrate cost, large substrate diameter availability (up to 12 inches), reasonable thermal conductivity and the possibilities of the co-integration with Si-CMOS electronics, make Si substrate the preferred choice for a large set of power electronics (mostly medium range voltage) [17].

2.2 III-N Crystal Structures and Polarization

Effects

Group III nitrides compound (III-N) exist in different crystal forms like zincblende, rocksalt and wurtzite structures [11]. Among these forms the wurtzite crystal structure features the highest thermo-dynamical stability. Wurtzite-type GaN is composed of two hexagonal lattices of N and Ga as shown in figure 2.1, where c-axis is the most preferred growth direction. GaN

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can be grown with two different polarities, i.e. Ga-face and N-face shown in Fig. 2.1.

Figure 2.1: Crystal structure of wurtzite Ga-face and N-face GaN [11] . In the case of Ga-face, the bonds along the [0001] direction are directed from Ga to N atoms, while, for N-face GaN the bonds along the [0001] direc-tion are from N to Ga atoms. The growth of Ga-face GaN is usually carried out using Metal Organic Chemical Vapor Deposition, while N-face GaN can be grown by Molecular Beam Epitaxy [13]. Both N-face GaN and Ga-face GaN possess spontaneous polarization (PS P) properties along c-axis due to

charge transfer between atoms with different electronegativity, as in the case of Ga (lower) and N (higher) [10], [11].

The III-nitride materials cover a very large range of bandgap energies, start-ing from infrared (InN with a bandgap of 0.7 eV) up to the extreme ultravi-olet (with AlN having a bandgap of 6.2 eV), as shown in figure 2.2. This is possible by varying the concentrations of the group-III elements (Al, Ga, In) in the crystal alloy with a composition AlxInyGa1−x−yN with x,y and x+y

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Figure 2.2: Bandgap versus lattice constant of III-N materials [18]. In GaN-based devices is common to find heterostructures with different lattice constant, for instance AlGaN/GaN heterojunction in HEMTs. When the AlGaN is grown on the GaN layer the different lattice constant leads to a mechanical stress causing a new type of polarization along c-axis, namely piezoelectric polarization. The latter is due to the lattice constant adjustment of the thinner material (AlGaN in this case). The amount of piezoelectric polarization is given by [10], [11]: PP E = 2 a − a0 a0 (e31 − e33 C13 C33 ) (2.1)

where e31 and e33 are piezoelectric constants, C13 and C33 are the elastic

deformation constants, a0 and a are the horizontal lattice constant before and

after the mechanical stress, respectively. The orientation of the spontaneous polarization is defined positive from Ga (cation) to nearest nitrogen atom (anion) along the c-axis, whereas the piezoelectric polarization is assumed negative for tensile and positive for compressed strained AlGaN barriers. Therefore, both polarizations are parallel in the case of tensile strain, while antiparallel in the case of compress strain of the AlGaN barrier. In the case of the AlGaN/GaN heterostructures, where the AlGaN barrier is grown on GaN layer, both polarizations point in the same direction and the value of total polarization is the sum of the piezoelectric and spontaneous polarization.

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The presence of these polarizations lead to creation of a channel of electrons at the AlGaN/GaN interface, namely two dimensional electron gas (2DEG), without the application of external biases. Further details on the 2DEG formation are reported in the subsection 2.3.3.

2.3 Metal-Organic Vapor Phase Deposition

for III-Nitride Epilayer Deposition on Si

The most suited technique for III-N epilayer deposition is the metal-organic chemical vapor deposition (MOCVD), also called metal-organic vapor phase epitaxy (MOVPE). By using this technique, the elements of the growing ma-terial are introduced in a reactor chamber in gaseous form, transported by a carrier gas like nitrogen (N2) or hydrogen (H2) or a mixture of both. Indeed,

the atoms of a given material are introduced in the chamber as precursor, that, for the III elements are a combination of the III group metals with organic elements. The source compounds for gallium are typically trimethyl-gallium (CH3)3Ga and triethylgallium (C2H5)3Ga, while, the precursor for

nitrogen is ammonia (NH3) where the nitrogen atom is directly bonded to

hydrogen atoms. These molecules are first thermally decomposed and then they react, in the gas phase, on the substrate’s surface or on another III-N semiconductor layer. The epitaxial growth process is monitored thermody-namically, i.e., by setting temperature and pressure of both the substrate and ambient for the gas in the reactor. The difference between the two energies can provide etching of the below layer or growth of the semiconductor on the surface. Usually, for GaN growth the temperature of the process is around 1000o_{C and the reactor pressure between 10 mbar and 200 mbar. It is}

im-portant that there is always equilibrium between the gas phase composition and the vapor pressure of the molecules of the solid phase to avoid contam-ination, since any contamination in the gas phase induces contamination of the solid semiconductor material. The contaminants atoms, such as carbon and hydrogen, could come from the metal-organic precursor themselves and it requires a good control of the vapor pressure to reduce inclusion of this atoms in the solid phase. [19]

The residual impurities, formed during the MOCVD processes, can play an important role in the layer’s conductivity since they can have donor or accep-tor dopant behavior. Through MOCVD, a further intentional doping can be obtained by introducing other precursor in the initial gas mixture. The best choice for the p-type doping in GaN is the magnesium and, it is provided by the precursor biscyclopentadienyl magnesium (Cp2Mg) [20]. While, the

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n-type doping is obtained by silicon via addition of silane (SiH4) or disilane

in the chamber(Si2H6) [21]. In the GaN based HEMTs the active part of

the devices don’t need any doping, but, doping can be used for increase the resistivity of a given layer (e.g. buffer), to decrease the gate ohmic contact resistance (n-type doping) or to compensate the intrinsic n-type behavior of III-nitrides (p-type doping).

Figure 2.3: General structure for an AlGaN/GaN HEMT device on Si.

In the following subsections will be described, layer-by-layer, the structure of the GaN based later HEMTs on Si substrate, as shown in figure 2.3. The main parts are the following:

1. A nucleation layer to initiate the epitaxial growth on the foreign Si substrate.

2. A buffer stack to compensate mechanical differences between Si and GaN.

3. The AlGaN/GaN heterostructure with the final capping to protect the surface, also called passivation layer.

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2.3.1 The Nucleation Layer

As discussed in the previous sections, there are many issues related to grow-ing a high quality GaN crystal on Si substrate due to thermal and lattice mismatch. Monocrystalline silicon and GaN have a cubic and hexagonal crys-tal structure, respectively. This difference may lead to a roughness GaN/Si interface and consequent lower quality of the buffer microstructure [22]. Fur-thermore, at high temperature gallium easily diffuse into silicon substrate leading to gallium silicide formation. This phenomenon is called gallium melt-back etching and, to prevent it, the best solution is to deposit an AlN layer on the substrate [19].

The growth conditions and properties of the nucleation layer can influence the final GaN film quality and the breakdown voltage in HEMTs. Many studies reported that the electrical breakdown does not occur laterally but vertically [23]. This effect is attributed to vertical path for electron from ohmic drain contact to substrate due to multiple threading dislocations, a lateral conduction along the AlN/Si interface followed by another vertical conduction between substrate and source trough dislocations/defects. AlN layer thickness is the most important key parameter to improve the break-down voltage and the crack densities into the upper III-N layers [24].

2.3.2 The Buffer Layer for Mechanical Stress

Manage-ment

The nucleation layer is not sufficient to prevent cracking in the GaN channel layer or wafer bow during cool down of the wafer and, for this reason, it is necessary a buffer stack between AlN layer and the GaN channel for strain management. The growth of GaN directly on AlN showed some circular de-fects, probably due to silicon outdiffusion from substrate, that could act as stress concentrators and initiate the cracking [22]. One of the first adopted solutions was based on the interposition of a single AlGaN layer with a grad-ual decrease of Al concentration from the top to the bottom, as shown in figure 2.4 (a). This latter shows some circular defects close to the edge of the wafer very similar to those seen growing GaN directly on relatively thick AlN layer.

Another approach consists in the fabrication of a multiple layer buffer with a gradual relaxing of the strain due to the differences in lattice constants of the materials. One of the best method is called step-graded buffer [25] and consist in growing AlGaN layers with different Al concentrations, gradually lower from AlN to GaN , shown in figure 2.4 (b). This procedure is repeated from two to five times until finally a smooth and free-crack GaN layer can be

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grown. This procedure leads to a gradually increase in the lattice constant and the quality of the final GaN layer improves by increasing the number of the AlGaN layers.

Figure 2.4: Structure of HEMTs with different buffer stack on Si sub-strate: (a) graded AlGaN layer, (b) multiple step-graded AlGaN layers where x<y<z<k, (c) AlN/GaN superlattice buffer.

Besides the step-graded buffer, the most commonly used approach is the superlattice buffer, as shown in figure 2.4 (c). The superlattice stack is man-ufactured alternating dozens of relative thin GaN and AlN layers [26]. Also in this case, by increasing the number of interlayers the final GaN crystal quality increases as well, meaning that there is a higher probability that ver-tically propagating threading dislocation eventually annihilate at the surfaces between the multiple layers.

Finally, after the buffer for strain management a final layer of carbon doped GaN is added (not showed in figure 2.4). The latter serves to increase the vertical breakdown voltage, to suppress punch-through in the off-state op-eration and to improve the normally-off opop-eration without changes in the ON-resistance. More details can be found in [27] and [28].

2.3.3 AlGaN/GaN Heterostructure and 2DEG

Forma-tion

GaN electronics are mostly based on the HEMT structure, with the active part is composed by an AlGaN/GaN heterostructure. After nucleation layer and strain management buffer a GaN channel layer followed by a thinner

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AlGaN barrier layer are deposited. Since there is lattice mismatch between the two materials, it is necessary to reduce the thickness of the AlGaN layer with increasing the Al content in order to prevent cracking.

Figure 2.5: Polarization induced sheet charge versus Al content(a). Inset (a): drawing of polarization induced sheet charge density and directions of the spontaneous and piezoelectric polarization in a GaN/AlGaN/GaN struc-ture. Schematic band diagram illustrating the surface donor model with the undoped AlGaN barrier thickness (b) less than, and (c) greater than the crit-ical thickness for the formation of the 2DEG [29].

As anticipated in section 2.2, the AlGaN/GaN heterostructure has an incredible ability to form a two-dimensional electron gas (2DEG) at the in-terface of the two layers, and for a Ga-face structure GaN/AlGaN/GaN the sheet of electrons appears in the lower GaN layer(inset figure 2.5(a)). The 2DEG is a sheet of electrons confined in two dimensions with concentration ns, representing the channel of the GaN HEMT. Understanding the cause of

the 2DEG formation is very important in order to improve the performance of electrical characteristics of the devices. This accumulation of electrons is the result of a charge compensation, but, the origin of this charge is still a topic of discussion.

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Figure 2.6: 2DEG densities in AlGaN/GaN heterostructure as functions of (a) AlGaN thickness with fixed Al percentage and (b) Al content with fixed AlGaN and GaN thickness. Solid lines are fits of the experimental data [30]. Many studies [10],[11] associate the 2DEG formation to the amount of spontaneous and piezoelectric polarization. Since the spontaneous polariza-tion and the piezoelectric constants ( e31 and e33) increase with increasing

Al concentration, the total polarization of a strained AlGaN layer is larger than that of a relaxed GaN layer, shown in figure 2.5 (a). For this reason, the decompensation of charge is associated to the gradient of polarization in space.

Other studies, associate the 2DEG phenomenon to the presence of donor-like states in the AlGaN barrier [29]. In this case, the key parameters for the sheet charges formation and densities are the AlGaN layer thickness and the aluminum percentage. Until a certain thickness, called critical barrier thick-ness, the donor energy is not enough to make able the electron to transfer itself from occupied state to empty conduction band state at the surface, as shown in figure 2.5 (b). As soon as, the barrier thickness reaches the critical value the donor-like states are able to give up electrons for the 2DEG (fig-ure 2.5 (c)), leaving behind positive surface charge. As shown in fig(fig-ure 2.6 the features of the AlGaN barrier layer have a strong impact in the 2DEG density and, hence, play a key role for the performance of the GaN-based devices and in particular on the threshold voltage and ON-resistance.

2.3.4 Top Part of HEMT: from Capping to Surface

Passivation Layers

After AlGaN/GaN heterostructure, in many cases, a further GaN cap layer on the AlGaN barrier layer is deposited in order to improve the HEMTs performance from forward and reverse leakage point of view. By adding a

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thin cap layer of GaN, the piezoelectric effect is exploited in order to increase the Schottky barrier height and, therefore, to improve the gate leakage [31].

Figure 2.7: Schematic band diagram for the structure without (a) and with (b) cap layer [32]. 2DEG density and Hall mobility versus GaN cap layer thickness for a GaN/AlGaN/GaN heterostructure with AlGaN thickness fixed (c) [33].

As shown in figure 2.7 (a), without GaN cap the height of the Schottky barrier is relatively low and this means that electrons could penetrate the barrier for tunneling effect. By increasing the height of the barrier (figure 2.7 (b)) with the cap layer, the tunneling effect can be reduced. Further-more, adding the cap layer introduces a negative polarization at the upper heterointerface causing increase of the electric field in the AlGaN and the 2DEG density decrease with increasing GaN cap layer thickness (illustrated in figure 2.7(c)) [33]. With a further increase of the cap thickness there is a saturation in the 2DEG density due to the complete formation of 2DHG at the upper GaN/AlGaN interface. More information are available in [33]. Since the 2DEG is determined by polarization and conduction band engineer-ing, it follows that it is very sensitive to the surface charge of the structure which is responsible of a small depletion of the 2DEG [31]. So, for a further improvement in AlGaN/GaN HEMTS, a SiN passivation layer is added. This latter can mitigate dispersion effects, since, the Si atoms can compensate the surface change almost eliminating the 2DEG depletion under the gate [34]. A relatively thin SiN layer on the top can protect the lower layers during the growth and, furthermore, it can prevent the grooves caused by the out-diffusion of the gallium during cooldown after epitaxial growth.

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The SiN passivation and the GaN cap are used only for depletion-mode de-vices that will be discussed in the following section.

2.4 Lateral GaN Devices for Power

Applica-tion

In the previous section, the layer-by-layer description of the HEMTs has been interrupted because the top part of the devices depends on the various device designs and operation modes. One of the bigger issue of the GaN/Al-GaN devices, with the structure previously described, is that the 2DEG is present also without bias and it leads to have normally-ON devices, also called depletion-mode (D-mode) devices. However, in the case of power ap-plications, it is always preferable to have normally-OFF (enhancement-mode) devices for the following reasons:

• safety: the normally-on device is always turned on;

• power consumption: to turn off the normally-on device it is necessary to apply negative gate voltages;

• costs: driver mature technology already exists for normally-OFF silicon-based MOSFET and it can be expensive to invest money in research for new drivers.

Today, the most adopted and commercially available solutions for a normally-OFF GaN devices are: (1) using a cascode configuration by combining a low-voltage Si-MOSFET with a high-voltage D-mode GaN HEMT and (2) E-mode HV GaN HEMT by changing the design of the device.

2.4.1 Cascode Configuration: GaN + Si

One approach to achieve normally-OFF operation for GaN device is the combination of a high-voltage D-mode GaN HEMT with a low-voltage Si-MOSFET (figure 2.8)[35]. When the Si-FET is turned on by the driver system, VGS of the HV HEMT is slightly negative and , therefore, the

D-mode GaN device is also turned on since it has a high negative threshold voltage. When the Si-FET is turned off by the drivers its VDS is really high

and, consequently, the VGS of the HV HEMT is sufficiently negative to turn

it off, sustaining a high voltage. The advantage of this technique is to use a reliable driver for MOSFET already available on the market without any need to redesign another one. Another advantage is that the high OFF-state

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blocking voltage of the HEMT is exploited. The advantage of this technique is to use a reliable driver for MOSFET already available on the market with-out any need to redesign another one. Another advantage is that the high OFF-state blocking voltage of the HEMT is exploited.

Figure 2.8: Cascode method operation to achieve normally-OFF operation. The main disadvantages are two: (1) the high frequency at which the GaN-based transistor can work is not exploited since the whole circuit is controlled on the Si-FET that operates at lower frequency and (2) by using two devices the dimensions and complexity of the packaging increases and, furthermore, the connections can introduce parasitic effects that leads to a lower performance in switching operation [36].

2.4.2 E-mode GaN-based Transistor

In order to obtain normally-off GaN HEMTs devices the gate region need to be modified.

One of the first approach proposed was the ”recessed-gate” HEMT [37], which corresponds to positively shift Vth by etching the AlGaN barrier layer under

the gate. Once the remaining AlGaN thickness is thinner than critical Al-GaN thickness, the 2DEG is no longer able to form under the gate, making the device normally-off.

Another solution can be the ”fluorine-gate” HEMT [38], which consists in the introduction of negatively charged fluorine ions in the AlGaN layer below the gate, leading to a positive shift of Vth without etching the barrier as in

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the ”recessed-gate” technique.

It is possible to obtain normally-off HEMTs also combing the two approaches just described [39]. All these solutions have shown to be good from the point of view of the gate leakage in both reverse and forward bias but there are difficulties regarding the precision in AlGaN etching and in the right amount of fluorine implanted since they both play a key role in the threshold voltage shift.

The most used approaches for normally-off GaN-based HEMTs are the ”p-GaN gate” and the ”recessed gate hybrid MISHEMT” discussed in the fol-lowing subsections.

p-GaN gate HEMT

Interposing a layer of p-GaN between the gate metal and the AlGaN barrier (figure 2.9 (a)) it is possible to deplete the 2DEG under the gate leading the GaN-based HEMTs to a normally-off operation as a result of raising the GaN conduction band in the channel above the Fermi level, due to a deple-tion effect of a PN juncdeple-tion. In this scenario the features of the AlGaN and p-GaN layer or the kind of metal gate play an important role for an efficient threshold voltage positive shift.

As already discussed in the subsection 2.3.3, ns increases with the AlGaN

barrier thickness and Al concentration, leading to a lower RON but, as

re-ported in [40], a lower Vth is attained due to an inefficient depletion of the

2DEG at zero bias. As a result, it is important to find the right trade off between the ON-resistance and the threshold voltage. For GaN the p-type dopant is the Magnesium and the key parameter to improve Vth is the Mg

electrical activation and out-diffusion that strongly depend on the growth parameters and annealing conditions [41].

Many works report about the importance of the metal work-function on the threshold voltage and gate leakage. In [42] Vth between 1.7V and 2.1V have

demonstrate with the gate metal made by Ni/Au or Ti/Au, while, it has been reported a threshold voltage around 2.1V with the Schottky gate con-tact, instead of an Ohmic contac, made of TiN [41] or WSiN [43]. This latter works showed also that the gate leakage current can be reduced. As result there is a metal/p-GaN Schottky diode in series with a p-GaN/AlGaN/n-GaN junction 2.9 (b). The gate leakage is reduced since under positive gate voltages the metal/p-GaN diode is reverse-biased blocking the current and, similarly acts the p-GaN/n-GaN/AlGaN under negative gate bias.

Despite the reliability issues still under investigation, the normally-off HEMT with the p-GaN gate is still the only commercially GaN-based device for power applications [44], [45] and [46].

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Figure 2.9: Schematic of a normally-OFF HEMT with a p-GaN gate (a) and back-to back diode for gate leakage reduction (b).

Metal-Insulator-Semiconductor HEMT

The other promising way to have E-mode GaN transistors is the recessed gate MISHEMT. The depletion of the 2DEG is obtained by etching the AlGaN barrier and part of the GaN channel layer (where the 2DEG is located) un-der the gate electrode and deposing a dielectric layer before the gate metal. The characteristics and the performances of MISHEMT are unstable since the repeatability and precision in the etching depth and in the thin dielectric layer deposition have many difficulties.

In particular the gate length, the surface and deep traps present at dielec-tric/GaN interface, the roughness of the etched area and the quality of the dielectric have an important impact on channel mobility, Vth and RON

sta-bility [36].

Regarding the dielectric layer, the most used materials are: (1) Al2O3

de-posited by Atomic layer deposition (ALD) with a reported threshold voltage of 3.5V in [47] (2) SiO2, processed by plasma-enhanced chemical vapor

de-position (PECVD), that seems the one with the higher Vth (around 3.7V)

[48] and, finally, (3) SiN also deposited with PECVD [49]. More details can be found in [47]-[49].

From figure 2.10 (b), in comparison with the p-GaN HEMTs, recessed gate MISHEMTs showed lower gate leakage current and larger forward gate swing due to the gate dielectric but, as reported in [50], MISHEMTs showed a large hysteresis after applying forward gate bias, probably due to the defects at the dielectric/GaN interface.

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Figure 2.10: Schematic cross section of a normally-OFF GaN-based MISHEMT(a) and (b) comparison of the forward bias gate leakage char-acteristics between p-GaN HEMT and MISHEMT [50].

Summary

In this chapter the layer-by-layer description of the GaN HEMT has been dis-cussed. So strong is the desire, so difficult is to have GaN substrates in terms of costs and wafer diameters. Despite all the difficulties, the heteroepitaxy on foreign substrates has led to promising results. In particular, especially thanks to the nucleation layer and the buffer for the strain management, GaN-on-Si devices are commercially available with good performance and reliability. The most suitable growth technique for the epilayers is the metal-organic chemical vapour deposition (MOCVD). The correct use of MOCVD has a strong impact on the quality of the deposited crystal and, hence, on the device characteristics.

In this chapter, furthermore, the gallium nitride crystal structure and ma-terials features have been described in order to understand why GaN is the best wide band-gap material for certain applications. In particular, the pres-ence of an AlGaN/GaN heterostructure leads to the two dimensional electron gas (2DEG) that is the heart of GaN-based HEMTs. The problem is that the 2DEG is present also with zero bias and for this reason, in the last few years many solutions are adopted to achieve normally-OFF operating de-vices (Enhancement-mode). A particular importance has been given to the

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p-GaN gate HEMTs and recessed gate MISHEMTs, though, the p-GaN gate solution is the only one commercially available since MISHEMTs have some problem in terms of stability and repeatability in the process.

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Chapter 3 GaN Reliability Issues

In addition to excellent performance at reduced cost, a semiconductor power device must guarantee a good level of reliability before making it available on the electronic market. Despite GaN power transistors demonstrated impres-sive performance at comparable costs with respect to Si-counterparts, the long-term reliability is still an issue not to be underestimated. GaN-based HEMTs are usually adopted in switching power applications, where their state is continuously switched, at relatively high frequencies, between high voltage off-state and high current on-state operation. In such conditions, devices can be subjected to different kinds of degradation mechanisms lim-iting their long-term reliability. Furthermore, during the switching phases the devices might be simultaneously subjected, for a short period of time, to both high-drain voltage and current. This regime is called semi-on-state operation and can lead to additional degradation mechanisms.

In general, the time-dependent degradation of GaN-based transistors may be triggered by many factors,, widely classified in [51] as follow:

1. Material origin: crystalline defects and lack of uniformity in the de-posited epilayer;

2. Metallurgy: ohmic contact and passivation degradation, hydrogen con-tamination, etc.;

3. Electrical behavior: reduction in drain current (current collapse), in-creasing in power consumption (power drift), breakdown walkout, etc.; Beside the aforementioned failure mechanisms, this chapter will focus with particular attention on trapping defects and self-heating problems. The key to better understand how reliable a device is, or which failure mech-anism leads to the degradation, resides in the thermo-electrical stress and characterization of the devices.

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3.1 Trapping effects

Trapping effects are the main cause of power GaN HEMTs degradation. The term traps refers to the defects deriving as a consequence of crystal imper-fections, threading dislocation or impurities, etc. The traps can introduce energy states in the bandgap of the semiconductor. These states can be: i) acceptor-like, i.e neutral when empty and negatively charged when occupied; ii) donor-like, i.e neutral when empty and positively charged when occupied. [52]

Figure 3.1: Traps localization in GaN HEMTs.

As shown in figure 3.1, there are several possible trap locations. The most relevant ones are the follow:

• At the AlGaN surface: their existence has been confirmed by Vetury et al. [53] with OFF-state measurements (high drain voltage and floating gate). During these experiments the occupation of the electrons in donor-like neutralizing his positive charge with a consequent reduction of the 2DEG density (the resistance increase).

• In the AlGaN layer: due to the carbon and oxygen concentration that has been found to be higher than in GaN or due to nitrogen vacancies, etc. [54].

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• In the GaN layer: as seen in the previous chapter, a carbon doped GaN buffer is required to suppress the current leakage. Still, the doping introduces acceptor-like impurities [52], [55].

• At the interfaces between layers of different materials: these traps can be related to threading dislocation caused by lattice constants and ther-mal expansion coefficients between adopted epi-materials [56], [57]. • In the buffer (not shown in Fig. 3.1): this kind of traps are localized

in the stack between the GaN channel layer and the substrate due to lattice mismatch between the various epilayer made of different mate-rials.

To determine a specific degradation mechanism, it is necessary to understand how the traps behave and what energy levels they are related to, where they are physically localized and what trapping/de-trapping time constants do they have. To do this, various trap characterization experiments, such as Current-Transient measurements [58], frequency dependent capacitance and conductance measurements [59] and capacitance-voltage (C-V) have been employed.

Based on their localization, each kind of trap can impact a different param-eter. In particular, the traps localized in the region under the gate (in red in figure 3.1) have a dominant impact on the threshold voltage, while all the other impurities (in yellow in figure 3.1) could lead to a change in the transconductance due to resistivity increase of the gate-drain and gate-source access regions [60].

3.2 On-State Degradation Mechanisms

In on-state condition the GaN devices are submitted to a low drain volt-age, but normally-off devices operate with positives gate biases that lead to further degradation mechanisms. The reliability issues for MISHEMTs and p-GaN gate HEMTs are different because of the different gate stack.

As already said in the section 2.4, MISHEMTs suffer of threshold voltage instability due to defect states at the dielectric/AlGaN interface. Lagger et al. [61] explained Vth degradation with a schematic band diagram (Fig. 3.2).

In particular, by increasing the gate bias (VG), the electrons barrier height

between 2DEG and dielectric/AlGaN interface decreases, favoring electron injection. A further increase in VG pushes the AlGaN conduction band (Fig.

3.2(c)) at the interface with the dielectric below the Fermi level, with a con-sequent formation of a second channel. As a result, the Vth shifts depends

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on the amount of charge trapped at the dielectric/AlGaN interface and it can be improved by using different materials and deposition processes of the dielectric.

Figure 3.2: Band diagram variation for MISHEMT with different positive gate bias levels: (a) thermal equilibrium, (b) low positive gate voltage, (c) high positive gate voltage [61].

Regarding the p-GaN gate HEMTs, the gate breakdown phenomenon could be explained by avalanche multiplication in the depleted region of the Schottky metal/p-GaN junction [62]. As shown in Fig. 3.3 (a), under thermal equilibrium conditions the depleted region of Schottky junction has a width of 50nm. Under forward gate bias the metal/p-GaN junction is reversed biased, depletion region is further extended and AlGaN barrier height is lowered (figure 3.3 (b)).

Figure 3.3: Band diagram variation for p-GaN gate HEMT in (a) thermal equilibrium and (b) positive gate voltage [63].

In such condition, the electrons from the channel are injected in the p-GaN and, once they reach the depletion region, they are accelerated by the

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electric field promoting avalanche breakdown.

Tallarico et al. [64] demonstrated that the p-GaN layer plays a fundamental role on the gate failure, ascribing the breakdown mechanism to the creation of a percolation path in the depletion region of the Schottky junction (inter-face between gate metal and pGaN) due to the high electric field.

The effect of pGaN doping and gate metal work function are the key pa-rameters in order to achieve a gate bias operating range and a performance stability as wide as possible. In particular, Mg doped p-GaN layer growth conditions and doping concentration have significant impact on the p-GaN gate HEMT device performance and reliability (more details in [41], [65] and [66]).

3.3 Semi-On-State Degradation Mechanisms

Between on- and off-state there is a third operation regime, namely semi-on-state. When the device switches from off- to on-state and viceversa, for few tens of ns, the drain current starts to increase while the drain voltage still relatively high. The simultaneous presence of high current and high voltage on the drain may favour hot electrons degradation effects, limiting the performance and the lifetime of the device due to charge trapping processes.

Figure 3.4: Variation of the on resistance measured during (a) the 200s of stress and (b) 5000s of recovery (the RON values are normalized with a sample

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In particular, is such regime, electrons injected from the source are ac-celerated by the high longitudinal electric field toward the drain, acquiring enough kinetic energy to create new defects and/or to be trapped in pre-existing ones, [67]. The most affected parameter is the on-resistance, and in order to investigate the hot electrons role in the degradation, high temper-ature source current (HTSC) stress tests are performed. Here, the devices are stressed for a long period of time with constant current injection from the source and with a high drain voltage. In figure 3.4 (a), it is possible to notice that the RON increases with both the current and time, but, on the

other hand, the hot electrons induced degradation is recoverable as result of trapping in the gate-drain access region. By increasing the temperature, the on-resistance degradation decreases because the mean energy of the hot electrons is reduced by the scattering with the lattice. Still, these scattering could produce unrecoverable damage [62].

3.4 Off-State Degradation Mechanisms

During Off-state operation, the devices are submitted to a high drain voltage having their bulk, source and gate contacts grounded.

Figure 3.5: Different off-state breakdown mechanisms namely: (a) drain to substrate breakdown, (b) drain to gate breakdown and (c) drain to source breakdown

This operation mode can lead to an unrecoverable breakdown that is time-dependent, a situation that also occurs at drain voltages lower than the breakdown voltage evaluated by a dc sweep. The off-state breakdown mechanism can be summarized in:

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2. Later breakdown of the gate-drain region of the Schottky junction and the passivation layer (Fig. 3.5 (b));

3. Drain to source lateral breakdown of the GaN channel (Fig. 3.5 (c)).

3.4.1 Vertical Leakage/Breakdown

It is well known that the buffer and transition layers between GaN channel and the Si substrate are not intrinsic semi-insulating materials. So, in or-der to compensate the background donor doping (by residual impurities as silicon or oxygen) of the buffer/transition layer, intentionally or unintention-ally deep acceptors (such as carbon or iron) are introduced to increase its resistivity, obtaining lower off-state leakage current and suppressed punch-through mechanism that can induce a premature breakdown in AlGaN/GaN HEMTs. When high drain bias is applied, the high vertical electric field strongly interacts with both acceptor and donor deep levels in the buffer [68].

Figure 3.6: (a)Temperature dependent transient normalized drain current at VDS=1 Vm and VSU B=-100 V drain to substrate breakdown [68], (b) vertical

breakdown as a function buffer and GaN layer thickness [69].

As shown in Fig. 3.6 (a), by performing a transient current test, the drain current decreases and then increases with a behaviour depending on both temperature and time. Marso et al. [70] demonstrated with the back-gating measurements (sweep test with substrate from -100V to 0V, while drain, gate and source grounded in order to suppress the surface traps ef-fects) that the decrease in drain current is to be attributed to the generation of negative space charges in the GaN buffer/transition layer by the ionization

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of acceptor traps, which depletes the 2DEG, and that the increase in drain current is caused by the ionization of donor traps, which generates positive space charges. Fig. 3.6 (b) shows the trend of the vertical breakdown by varying the buffer thickness (TBuf) and the GaN layer thickness (TGaN). In

particular, it can be seen that the breakdown voltage is slightly affected by TGaN, while TBuf plays a more important role [69].

Many studies have investigated the responsible factors of the vertical con-duction, proposing some solutions such as the use of a highly resistive silicon substrate [71] or the insertion of a p-type region [72] due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate.

3.4.2 Lateral Breakdown in the Gate-Drain Region

The other region affected by degradation/breakdown is the one between drain and gate. In particular, the breakdown can occur at the Schottky junction and/or at the passivation layer, and it is caused by the high electric field due to high voltage between gate and drain, VGD. Regarding the Schottky

junction, the real cause is a high peak of the electric field at the gate edge on the drain side, as it can trigger the following mechanisms:

• Inverse piezoelectric effect: as it is well known, the AlGaN barrier layer is subject to a tensile stress due to the lattice mismatch with the GaN channel layer. This can produce crystallographic defects resulting in the degradation of the electrical characteristics due to trapping/de-trapping effects. Ancona et al. [73] demonstrated with an electrome-chanical analysis that the piezoelectric effect alone is not sufficient to generate a crack in the AlGaN layer, but the combination of the high electric field, gate leakage current and high temperature together lead to the breakage. The role of the AlGaN barrier properties is very im-portant and by reducing the Al content the mechanical stress with the GaN layer is reduced, though, the performance (such as the RON since

the 2DEG has a lower density) will be worse.

• Electrochemical degradation: by etching the passivation and the met-allization from the device (without damaging the AlGaN or the GaN surface) Makaram et al. [74] showed the presence of grooves and parti-cles. They also demonstrated that with the increase of the electric field in off-state conditions, the number of the particles and the depth of the grooves increased at the drain-side of the gate edge. These phenomena are related to an electrochemical reaction consisting in the oxidation of GaN or AlGaN, with formation of Ga2O3 and Al2O3 [75]. The main

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issue is that the grooves and the particles can charge the device sur-face, forming a virtual gate responsible of drain current collapse and gate leakage current increase [76].

• Percolation processes: high electric field is also responsible for an in-crease in the amount of defects in the AlGaN barrier layer (demon-strated by electroluminescence measurements [77]). This can create a percolation multistep tunnelling path. The number of defects creating a percolation path is voltage and time dependent, as they lead to an increase of the gate leakage current (until the permanent breakdown) and a shift of I-V curves measured after constant voltage stress [78]. It emerges that the main issues for the gate-drain region are the high electric field peaks and the impurities in the epilayers. Both of them may produce current collapse, which consists in a drastic reduction of the drain current (ID) after the application of a high drain voltage (VD) [79]. The

current collapse is caused by acceptor-like traps in both AlGaN/GaN layers and the passivation/AlGaN interface: this leads to trapping mechanism of the 2DEG electrons accelerated by the high electric field [52].

Figure 3.7: (a) Constant voltage test at VD = 900 V, demonstrating that the

extra nitride layer increases time to failure by one order of magnitude. (b) Box chart showing the measured time to failure in devices with and without extra SiN layer stressed at VD = 900 V and VD = 950 V [80].

One of the adopted solutions to suppress trapping effects (in particular the ones about the surface traps) was SiNX passivation (as mentioned in the

subsection 2.3.4 ). Although, during a constant voltage off-state stress, the electric field peaks at the gate edge on the drain side, reaching a value com-parable to the one of the breakdown electric strength of the SiN (6 MV/cm)

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[80]. In particular, in [80], an improvement has been found by adding an extra SiN layer above the already present one. The electric field peak has been reduced, resulting in one order of magnitude increase of the time to failure/breakdown with respect to the devices without the extra SiN layer, shown in Fig. 3.7.

Another way to increase the breakdown voltage is by reducing the electric field (close to gate edge) with the adoption of the field plates. As shown in Fig. 3.8, this approach consists in depositing three metal layers, two linked to the source and one to the gate, all of them separated by oxide layers. In particular, the longer the field plates, the lower the electric fields. However, it is worth noting that a too long field plate (e.g. S-FP2 in Fig. 1.5) could lead to a lower breakdown voltage due to short distance between field plate and drain contact. As a result, the right trade-off must be achieved.

Figure 3.8: Cross-section of a GaN HEMT with double source field plates (S-FP1 and S-FP2) and single gate field plate (G-FP).

3.4.3 Lateral Breakdown between Source and Drain

Finally, the last breakdown mechanism with regards to the off-state condi-tion, is the one involving th GaN channel layer. This breakdown is due to an increase in the drain-source leakage current, linked to the punch-through effects. If the region of the GaN channel under the gate is not well depleted, the high drain voltage allows a current flow through the GaN layer in a deeper position respect to the AlGaN/GaN interface and strongly depends on the gate length [81]. As shown in Fig. 3.9 (a) , the higher the negative VGS, the

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more depleted in the vertical direction (towards the buffer).

Figure 3.9: Drain current as function of the drain voltage at different negative gate bias (VGS) (a) [81]. Gate, Drain and source current during constant

voltage stress in off-state condition (b) [82].

In [82], the time-dependency of drain-source degradation has been proven and it has been attributed to positive charges originating under the gate. In particular, in Fig. 3.9 (b) it can be noticed that, with a high drain bias, the main contribute to the drain current is initially given by the gate leakage, while, increasing the stress time, the source current become negative, meaning that the current flows out of the source. When the device approaches to the breakdown, the main component of the drain current is the source one, since the gate current shows no changes.

In order to prevent this issue, a double structure AlGaN/GaN/AlGaN is used. The introduction of an AlGaN layer below the GaN channel layer leads to a better confinement of 2DEG electrons and prevents punch-through with a consequent reduction in the off-state drain leakage current [83].

Summary

Overall, gallium nitride-based HEMTs for power electronic applications are very promising devices with higher breakdown voltages, lower on-resistance and higher switching capability compared to silicon counterparts. However, being an emerging technology, further efforts in terms of optimization are required to ensure high levels of reliability in all operation regimes discussed

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in this chapter, i.e. (1) on-state, (2) semi-on-state, (3) off-state. The next chapter reports an experimental activity aimed at investigating the off-state reliability of power GaN HEMTs with p-type gate fabricated on 200 mm silicon substrates by imec.

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Chapter 4 Investigation of the Off-State

Reliability on 200V pGaN

HEMTs

In this chapter an Off-state reliability study is presented performed on 200 V p-GaN HEMTs featuring different structural configurations summarized in section 1.1.1. In particular, time-dependent dielectric breakdown and hard breakdown experimental tests have been performed in combination with TCAD simulations. Thanks to this approach, the root causes limiting the off-state device reliability have been identified, highlighting the role and the importance of structural parameters, which are fundamental for guiding de-vice optimization.

4.1 Experimental Details

Off-state electrical stress and measurements have been carried out by means of a MPI-TS2000-HP probe station connected to KEYSIGHT B1505A pa-rameter analyser equipped with high power, high voltage and ground source measure units (SMUs). In particular, the devices under test are connected as follows:

• Source contact: connected to high power SMU (HPSMU1); • Drain contact: connected to high voltage SMU (HVSMU); • Gate contact: connected to high power SMU (HPSMU2); • Substrate contact: connected to ground SMU (GNDSMU);

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During Off-state stress, the gate, source and bulk contacts are forced to 0 V while, the drain voltage is sweeped up to stress voltage and/or breakdown voltage. All contacts currents are monitored. Usually, accelerated stress tests are performed at 150 oC but, in this case, a temperature of 210 oC has been adopted to limit the stress voltage (< 500 V) and time-to-failure (< 105

s). Devices with different geometry parameters such as gate-drain distance (LGD) and the field plates lengths have been adopted. The role of the AlGaN

barrier thickness (TAlGaN), Al content, and GaN channel thickness (TGaN)

on the off-state degradation has been also investigated.

4.1.1 Device Under Test

P-GaN gate HEMTs grown on 200mm Si(111) wafers by imec (Belgium) with a class voltage of 200 V are considered in this study. The epi-stack grown on top of silicon (Fig. 4.1(a)) features a 3.3 um thick superlattice buffer, 200 or 400 nm thick GaN channel, 12.5, 14 or 16 nm thick AlGaN barrier. Then, a Al2O3 passivation is deposited on the access regions, whereas the

gate is composed by 80nm of p-GaN (doped with Mg) followed by 30nm of titanium nitride (TiN). The structure features three field plates namely gate metal (linked to the gate), source ohm metal and source metal1 (both linked to the source) field plates. For the sake of simplicity, in this chapter, the field plates will be named first field plate (FP1) for the gate field plate and second and third field plate (FP2 and FP3) for the source ohm metal and source metal1 field plates, respectively. More details on the device architecture can be found in [84].

Figure 4.1: Schematic cross section of p-GaN HEMT (a) and TAD simulator output (b).

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each device differs for gate-drain distance and field plate length configuration. Device name LGD (µm) FP1 (µm) FP2 (µm) FP3 (µm) Device1 3 0.35 0.65 1 Device2 4 0.65 1.35 2 Device3 5 1 2 3 Device4 6 1 2 3

Table 4.1: Overview of the devices under test.

4.1.2 Hard Breakdown

Hard breakdown measurements consist in sweeping the drain voltage from 0V up to breakdown voltage, as shown in Fig. 4.2. During the measure-ments gate, source and substrate contacts are grounded and their currents are monitored.

The breakdown voltage is defined as the voltage at which the drain current suddenly increases without control (see Fig. 4.2). Hard breakdown tests per-formed on different devices are helpful to provide an preliminary indication on the performance, reliability, variability of the process, etc. Moreover, such tests provide an average value of the off-state breakdown voltage, which is of paramount importance to choose the stress conditions for time-dependent dielectric breakdown tests.

Figure 4.2: Hard breakdown test performed on eight nominally identical de-vices.

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4.1.3 Time-Dependent Dielectric Breakdown (TDDB)

Time-dependent dielectric breakdown has been studied for the first time in thin oxide films [85] and [86], due to their importance in silicon CMOS in-tegrated circuits. Regarding GaN devices, the situation is slightly different since the time-dependent breakdown can occur in different regions/materials, i.e. passivation layers (SiO2, AlO2, SiN, etc.), or semiconductor layers (GaN,

AlGaN, etc.) [87], [80], [88] . The most commonly used test for the inves-tigation of TDDB behavior is ”constant stress”. Such stress can be applied in form of constant voltage stress (CVS) or constant current stress (CCS). In the case of CVS test adopted for off-state reliability of GaN devices, a voltage is applied to the drain, while its leakage current is being monitored up to failure.

Time-to-Breakdown

In [85], [86] it has been suggested that the time-to-breakdown is a conse-quence of traps located in random positions in the oxide, even in a fresh device. When the oxide is submitted to a relatively high electric field new traps are generated. The amount of traps increases with time causing one or more percolation paths with a sudden increase in the current (in the case of CVS), which means that the breakdown occurred (show in Fig. 4.3).

Figure 4.3: Current monitoring during a constant voltage stress in off-state condition with VD=430V.

OFF-State Reliability of pGaN Power HEMTs

OFF-STATE RELIABILITY OF pGaN

POWER HEMTs

Tesi di Laurea Magistrale in

III Sessione - II Appello

Anno Accademico 2018/2019

Acknowledgements

Abstract

Contents

Chapter 1

Introduction

1.1

Semiconductor Power Devices

Technolo-gies

1.1.1

Material Properties

1.1.2

Figure Of Merit (FOM)

1.1.3

Breakdown Voltage and On Resistance

Chapter 2

III-N materials and devices

2.1

Substrates for III-N Epitaxy

2.2

III-N Crystal Structures and Polarization

Effects

2.3

Metal-Organic Vapor Phase Deposition

for III-Nitride Epilayer Deposition on Si

2.3.1

The Nucleation Layer

2.3.2

The Buffer Layer for Mechanical Stress

Manage-ment

2.3.3

AlGaN/GaN Heterostructure and 2DEG

Forma-tion

2.3.4

Top Part of HEMT: from Capping to Surface

Passivation Layers

2.4

Lateral GaN Devices for Power

Applica-tion

2.4.1

Cascode Configuration: GaN + Si

2.4.2

E-mode GaN-based Transistor

Summary

Chapter 3

GaN Reliability Issues

3.1

Trapping effects

3.2

On-State Degradation Mechanisms

3.3

Semi-On-State Degradation Mechanisms

3.4

Off-State Degradation Mechanisms

3.4.1

Vertical Leakage/Breakdown

3.4.2

Lateral Breakdown in the Gate-Drain Region

3.4.3

Lateral Breakdown between Source and Drain

Summary

Chapter 4

Investigation of the Off-State

Reliability on 200V pGaN

HEMTs

4.1

Experimental Details

4.1.1

Device Under Test

4.1.2

Hard Breakdown

4.1.3

Time-Dependent Dielectric Breakdown (TDDB)