UNIVERSIT ´
A DEGLI STUDI DI PISA
Dipartimento di Ingegneria dell’Informazione
Tesi di Laurea Magistrale in Ingegneria Elettronica
FPGA Design of the digital acquisition
chain to test and implement ALPS,
the new Beam Position Monitor for the
Super Proton Synchrotron at CERN
University Supervisor Prof. Luca Fanucci CERN Supervisor Ing. Andrea Boccardi
Author Irene Degl’Innocenti
Summary
This thesis presents the firmware design and the data analysis to test and implement part of the acquisition chain of ALPS (A Logarithmic Position Moni-tor), the new beam position monitor of the Super Proton Synchrotron (SPS) at CERN, the European Organization for Nuclear Research.
CERN provides particle accelerators and detectors to accelerate beams of particles and observe their collisions and the SPS is the second larger circular machine in the accelerator complex. The SPS beam position monitor, the system that measures the transverse position of the accelerated particle beams along the pipe, is now under redesign. In the BPM acquisition chain the signal from the sensor is first conditioned by the analog front-end, then digitalised in the digi-tal front-end and transmitted to the back-end for being processed. The goal of the thesis is the conception of firmware modules and analysis tools integrated with the acquisition chain, aiming to acquire and analyse data to qualify the sys-tem and finally implement the digital processing modules to extract the position information.
I designed the back-end FPGA (Field programmable Gate Array) firmware and the control software to test the analog front-end prototype, based on logarith-mic amplifiers. The design is based on a synchronous static finite state machine, interfacing with the high-speed digital link to the front-end and with the machine timing from the accelerator. It is parametrizable and controllable by software on-line. Every modules and the whole firmware have been simulated and later tested in the lab. With the full acquisition chain I made data acquisition in the lab, with a signal generator beam emulator, and in the tunnel, with actual beam signals. The analysis of the data acquired allowed to characterise the front-end prototype in terms of linearity, intensity dependence and resolution, individuating limits and strong points.
The data collected are also the base of the second step of the thesis, aimed to explore the digital processing tools that can be implemented in FPGA to extract the position information. I studied and implemented a parametrisable algorithm to recognise the specific event linked to the position extraction. I designed the module to calculate the beam orbit, the position averaged at a programmable bandwidth, based on a IIR (Infinite Integral Response) digital filter with selectable bandwidth; the filter has an external control that adapts the bandwidth according to the read-out frequency. I developed also the modules to calculate the trajectory and the capture, the position measured turn by turn, respectively for all the beam batches and for a selected batch. All the modules are designed to be instantiated in parallel, as the logic building blocks of a more complex hierarchical system, adapting on-going to the future developments of the analog front-end.
In conclusion, this document offers several FPGA based solutions for acquir-ing and processacquir-ing Beam Position Data from circular machines; all the modules designed are simulated and, for the most part, they are also already verified with actual beam data.
Contents
1 Introduction 5
1.1 CERN and the Beam Instrumentation group . . . 5
1.1.1 CERN and the accelerators complex . . . 5
1.1.2 The Beam Instrumentation (BI) group and the Tune and Position (QP) section . . . 5
1.2 Beam Position Monitor: general overview . . . 6
2 The SPS Beam Position Monitor Upgrade 9 2.1 The Characteristics of SPS . . . 9
2.2 The Specifications of the BPM . . . 12
2.3 System design choices . . . 12
2.4 The acquisition chain . . . 13
2.4.1 The Analog Front-End prototype . . . 13
2.4.2 The Digital Front-End . . . 14
2.4.3 The Back-End . . . 16
2.5 My role in the project . . . 17
3 ALPS firmware generic structure and design flow 19 3.1 VFC-HD base project and design flow . . . 19
3.2 Clock domains . . . 20
3.3 The machine timing . . . 22
4 The experimental validation of the Analog Front-End board 25 4.1 The back end application firmware . . . 25
4.1.1 Specifications . . . 25
4.1.2 Acquisition logic . . . 26
4.1.3 The test of the firmware . . . 30
4.2 The test control software . . . 30
4.3 Data acquisition . . . 33
4.3.1 Beam test set-up . . . 33
4.3.2 Lab test set-up . . . 33
4.4 Data analysis . . . 34
4.4.1 Qualitative analysis of beam measure . . . 34
4.4.2 Linear characteristic from beam measure . . . 42
4.4.3 Resolution from beam measure . . . 45
4.4.4 Linear characteristic and resolution from lab measure . . . 49 3
4 CONTENTS 4.4.5 Position measurements and resolution dependence on
In-tensity . . . 52
4.5 Test results . . . 57
5 Implementation of the SPS BPM system firmware 61 5.1 The proposed algorithm to select valid position samples . . . 61
5.2 Implementation of the firmware . . . 64
5.2.1 Validation module . . . 65
5.2.2 Batch Window Marker module . . . 66
5.2.3 Orbit module with programmable bandwidth IIR Filter . . 66
5.2.4 Trajectory module . . . 68
5.2.5 Capture module . . . 69
5.2.6 FIFO Module . . . 69
Chapter 1
Introduction
1.1
CERN and the Beam Instrumentation group
1.1.1
CERN and the accelerators complex
CERN is the European Organization for Nuclear Research, it operates the world’s largest Particle Physics laboratory, where physicists and engineers study the basic constituents of matter and the fundamental laws of nature. The instruments used at CERN are purpose-built particle accelerators and detectors. Accelerators boost beams of particles to high energies before the beams are made to collide with each other or with stationary targets. Detectors observe and record the results of these collisions.
The accelerator complex at CERN (figure 1.1)is a succession of linear and circular machines with increasingly higher energies. Each machine injects the particle beam into the next one, bringing the beam to higher energy. The ac-celerated beams are composed of particles of the same kind, either protons or lead ions. The last element of this chain is the LHC, where each particle beam is accelerated up to the record energy of 6.5 TeV; experiments as ALICE, ATLAS, CMS and LHCb are installed in four huge underground caverns built around the four collision points. In addition, most of the other accelerators in the chain have their own experimental halls, where their beams are used for experiments at lower energies.
1.1.2
The Beam Instrumentation (BI) group and the Tune
and Position (QP) section
The Beam Instrumentation group is responsible for designing, building and main-taining the diagnostic equipment that allow observation of the particle beams and the measurement of related parameters to tune, operate, and improve all CERN accelerators and transfer lines.
The main questions the group aims to answer are the following: • How many particles are in the machine, i.e., the beam intensity.
• Where these particles are located, i.e., the position of the beam centroid. 5
6 CHAPTER 1. INTRODUCTION
Figure 1.1: The CERN accelerator complex
• How many oscillations in both vertical and horizontal planes the particles do per turn in the accelerator, i.e., the beam tune.
• How the tune changes with particle momentum, i.e., the chromaticity. • How distribution of particles in space looks, i.e., the beam profile in both
transversal and longitudinal dimensions.
• Is the beam losing particles and where, i.e., the beam loss.
The group is composed of several sections, with different tasks and expertises. Among these, the Tune and Position section (QP) is mainly responsible for de-signing, building and maintaining the instruments that allow measurements of the beam tune (Q), chromaticity (Q’) and coupling (C-) of all the circular machines, and the measurement of the beam position (P) in the SPS, LHC and many of its transfer lines.
1.2
Beam Position Monitor: general overview
A beam position monitor (BPM) has the role to provide information on the po-sition of the beam in the vacuum chamber at the monitor location. For linear accelerators and transfer lines the BPMs are used to measure and correct beam trajectories, while for synchrotrons the monitors are distributed around the ring and they are used also to calculate the closed orbit, i.e. the trajectory averaged over several turns. Modern BPMs are complex systems, capable of sensing, digi-tizing and processing beam signals to provide position data from several hundred local monitors in a fraction of a second. A BPM acquisition chain has the beam
1.2. BEAM POSITION MONITOR: GENERAL OVERVIEW 7 as source, the sensing element is called pick-up, whose output is processed to compute the beam position and transmit the information.
The Signal source
The reference parameters used to define the BPM input signal are the beam current Ib circulating in the machine and the transverse displacement of the beam
from the centre of the pipe [15]. The particles in the beam are grouped in so called bunches, so the total beam charge depends on Nb, the number of bunches, and
Qb, the charge per bunch in Coulombs. The beam current in a circular accelerator
is then expressed by the expression: Ib =
Qb· Nb
trev
The Pick-up
The pick-up is the element that translates the beam current into the electrical voltage seen by the signal processing system. There are several pick-up families, but the most commonly used are the electrostatic (electrodes). The idea [14] is to measure the charge induced by the electric field of the beam particles on an insulated metal plate; the charge is directly proportional to the beam intensity and inversely proportional to the distance between the beam and the plate (figure 1.2). Two pick-up plates are installed at the opposite sides of the beam pipe wall and the difference of their signals yields the beam’s centre of mass for that transverse plane. The button time response for different bunch lengths is shown in figure 1.3.
Figure 1.2: Schematic of a capaci-tively coupled electrode
Figure 1.3: Time response of a but-ton electrode [12]
The normalisation of the Position
Once obtained the signals A and B from the opposite electrodes or couplers of a pick-up, the meaningful position is extracted making the distance related signals independent of the beam intensity. Two algorithms are generally used and implemented [12]:
8 CHAPTER 1. INTRODUCTION • Difference over sum: if I is the intensity and x is the displacement with
respect to the centre of the BPM: (
A ≈ k · I · (1 + a · x) B ≈ k · I · (1 − a · x)
A − B
A + B ≈ a · x
Then the normalised position PN is highly linear and is given by:
PN =
A − B A + B
The sum and difference can be obtained either using a 0/180 passive hybrid, a differential amplifier or in the digital domain after digitalisation.
• Logarithmic ratio: the two pick-up signals are converted into their loga-rithmic counterparts and subtracted. In fact, assuming small displacement (a · x) 1 : A − B A + B ≈ A − B 2 · B = 1 2 A B − 1 Then, remembering that A−B
A+B ≈ a · x :
A
B ≈ 1 + 2 · a · x
It follows that we can calculate the normalised position PN as:
PN = log A − log B = log
A
B ≈ log (1 + 2 · a · x) ≈ 2 · a · x
In practice this is done using logarithmic amplifiers followed by a differential amplifier.
The Read-out electronics
The read-out system interfaces the BPM pick-up to the accelerator data acqui-sition (control) system. This requires signal conditioning, normalisation, and linearisation of the BPM signals with conversion to a digital format somewhere along this chain in order to ultimately provide a time-stamped beam position.
Chapter 2
The SPS Beam Position Monitor
Upgrade
Figure 2.1: The SPS tunnel
The Super Proton Synchrotron (SPS) is the circular accelerator that receives particles from the Proton Synchrotron and accelerates them to provide beams for the Large Hadron Collider, the NA61/SHINE and NA62 experiments, the COMPASS experiment and the AWAKE experiment.
The beam position monitors pick-ups, 216 in total, are distributed along the ring, providing horizontal and vertical beam signals. The current beam posi-tion monitor system, called Multi Orbit POsiposi-tion System (MOPOS), suffers from obsolescence of its electronics and needs an upgrade. The new system under development by QP is based on logarithmic amplifiers [10] and it is called A Logarithmic Position System (ALPS).
2.1
The Characteristics of SPS
The SPS ring has a circumference of approximately 7 Km; the vacuum pipe has a minimum radium of 25 mm. It accelerates proton beams up to 450 GeV, with
10 CHAPTER 2. THE SPS BEAM POSITION MONITOR UPGRADE a revolution time of nearly 23 µs. The particles trajectory is bended and focused in the circular ring employing dipole and quadrupole magnets; the acceleration is achieved with the mean of RF electric fields in resonant cavities tuned around 200 MHz and synchronous with the beam. The beam rigidity is increased with the energy, requiring higher magnetic fields to keep his trajectory. The particles in the beam are not distributed continuously, but grouped in so called bunches. Each bunch is synchronized to the RF field and must reside to be stable in what is called an RF bucket: one of the stability area in the RF period. The operation of the SPS is divided in cycles: the particles are injected at the lowest energy accepted by the accelerator during the so called flat bottom; then the filled beam is accelerated with an increase of the magnets current and the RF frequency, in the so called ramp; so the beam is extracted at its higher energy to be provided to the user, in a single shot or with a slow extraction, during the flat top; finally during the ramp down the remaining particles at the end of the extraction are dumped and the SPS magnetic cycle returns to the flat bottom. These stages are visible in the magnetic pulse and particle intensity curves.
Figure 2.2: Representation of the particle intensity and the magnetic field curves for two consequent cycles[6].
SPS serves several users: it is the injector for the LHC for both protons’ and ions’ runs, it provides beams to Fixed Target experiments and to a wake field acceleration test beam line (AWAKE). It follows that it has to operate with a number of different cycles. A super-cycle [4] is made up of a number of individual cycles, each of which has to be a multiple of 1.2 seconds in length, the basic time period of the SPS corresponding to the Linac repetition rate, the fastest cycling machine in the injector chain. These cycles are executed sequentially in a pre-set order, determined by the operator. The super-cycle is repeated until at least one of the user has satisfied its necessities.
This variety leads to a wide range of bunch filling patterns and bunch charge as shown in table 2.1. We call batch a bunch train coming from the Proton Synchrotron (P)S ring and injected in the SPS. The nominal number of batches NBAT can vary between 1 and 4 for protons and up to 13 for ion-beams.
2.1. THE CHARACTERISTICS OF SPS 11
Figure 2.3: Example of an SPS super-cycle representation on SPS Page-1, the monitor page for SPS operations. It is possible to read information about the super-cycle duration, the current user, the beam parameters and the experiments using the indicated targets[6].
Table 2.1: SPS Beam parameters
Beam Type Bunch spacing Bunch number Bunch charge [1010]
Fixed target 5 ns 400 ÷ 4200 0.2 ÷ 2.0 LHC25NS 24.96 ns NBAT × 72 1.0 ÷ 26.0
LHC50NS 49.92 ns NBAT × 36 1.0 ÷ 35.0
LHC single bunch 524.4 ÷ 2022.6 ns 1 ÷ 16 0.2 ÷ 50 LHC ion / Pb82+ 50 ÷ 100 ns NBAT × 6 0.2 ÷ 2.0
revolution time and revolution frequency are summed up in table 2.2 for protons and in table 2.3 for ions.
Table 2.2: SPS parameters for proton beams Momentum, p GeV /c 14 450 Revolution time, Trev µs 23.11 23.05
12 CHAPTER 2. THE SPS BEAM POSITION MONITOR UPGRADE Table 2.3: SPS parameters for ion beams
Momentum, p GeV /c/u 5.0 176.8 Revolution time, Trev µs 23.45 23.05
Revolution frequency, frev kHz 42.64 43.38
2.2
The Specifications of the BPM
The pick-up provides signals directly proportional to both beam position and beam intensity; the electronic must cover a dynamic range of approximately 70 dB, out of which 50 dB come from variations in bunch intensity, that, as we can see from SPS beam characteristics, can vary between 0.2 · 1010 and 50 · 1010.
The system should be able to provide for each cycle, that can be up to 100s long, the following measurements:
• Closed orbit : the average position of all the bunches in the machine at a programmable filtering bandwidth and sampling rate up to 1kHz.
• Trajectory: the position of each batch at each one of the first 50 turns (turn by turn data).
• Capture: the turn by turn position of a selected batch in the machine for 1000 turns following a SW or HW trigger.
The required resolution for low and high intensity beams is presented in table 2.4 for all the acquisition modes.
Table 2.4: SPS beam position measurements resolution requirements High Intensity (≥ 1010 p/bunch) Low Intensity
Orbit Mode 100 µm 400 µm Trajectory Mode 400 µm 1000 µm
Capture Mode 400 µm 1000 µm
2.3
System design choices
The main issues the current beam position monitor system is suffering from, other than the obsolescence of the electronic components, are linked to the way the dynamic range is covered and to the effects of radiation on the cables used to carry the signals to a a radiation free area.
2.4. THE ACQUISITION CHAIN 13 Logarithmic compression
The MOPOS deals with the high dynamic range via a series of variable gain amplifier. The operators are asked to pre select the appropriate gain setting for the cycle to measure. A setting error is seen only at the end of the cycle, when the result is read out and is too late to correct. The solution proposed by the new design is to base the analog front-end on logarithmic amplifiers: they can compress the high dynamic range, so that it is possible to reduce the number of different gain channels to two, maximum three, allowing to process and acquire them all in parallel and avoid any pre setting necessity.
Radiation tolerant digital front-end
The level of radiation in SPS, with doses up to 100 Gy/year, demands a special attention in the use of active components and monitoring of the degradation of the quality of the cables. The current system locates the front-end on the surface and the link requires very long and expensive cables that need periodic and time consuming measuring campaign to compensate for their degradation. To avoid this, the new system will place the front-end boards in the tunnel, imposing a radiation-tolerant design.
2.4
The acquisition chain
Figure 2.4: Schematic of the ALPS acquisition chain
Each BPM plane electrode couple (vertical or horizontal) will be read out using a radiation tolerant front-end, with independent analogue and digital circuits connected together. After a first analogue conditioning and compression stage, signals are digitized locally and transmitted via optical fiber over long distances to the read-out back-end board located in a surface building. The back-end communicates through a VME interface with the software environment in order to receive commands and send data.
2.4.1
The Analog Front-End prototype
The architecture of the single-plane analogue front-end prototype board is de-picted in figure 2.5. The input signals come either from the pick-up or from a
14 CHAPTER 2. THE SPS BEAM POSITION MONITOR UPGRADE
Figure 2.5: Simplified schematic of the analog front-end board prototype calibrator, which is remotely controlled by the digital front-end board. The signal from each electrode is split into two parallel acquisition chains with different low pass and band-pass filters to cover the different beam bunch spacing patterns available in the SPS: the 40 MHz chain for the 25 ns bunch spacing beam and the 200 MHz chain for the 5 ns bunch spacing beam. Both the chains perform the sum and the difference of the logarithm of the signals coming from the oppo-site electrodes. So the board produces two couples of sum and difference signals, both relative to the same pick-up plane, each adapted to a different sort of beam condition. An example of sum and difference signals coming from the front-end is shown in figure 2.6. The sum signal is proportional to the beam intensity and can be used to validate the difference signal, that is proportional to the beam position.
2.4.2
The Digital Front-End
The digital front-end is responsible for digitalising the data coming from the analog front-end and transmitting them by optical link to the back-end. It is composed of two boards: the BDF (BPM Digital Front-end) and the GEFE (GBT-based Expandable Front-End). The BDF (reference on CERN Engineer-ing & Equipment Data Management Service: EDA-03134-V2) is an FMC (FPGA Mezzanine Card); the FMC is an ANSI standard that provides a standard mez-zanine card form factor, connectors, and modular interface to an FPGA located on a carrier board, the GEFE in this case. On the BDF there are two AD41240 [5]: quadruple 12-bit, 40 MSPS radiation tolerant analog-to digital converter de-signed for the CMS experiment. A single BDF can potentially digitalise up to eight channels.
The GEFE [3](reference on CERN Engineering & Equipment Data Manage-ment Service: EDA-03168-V2) is a multipurpose FPGA-based radiation tolerant board designed by BI to be the new standard carrier for radiation tolerant digital front-end applications. The main purpose of the GEFE is the implementation of the interface between the back-end and the digitalization module, the BDF in this case. All the components chosen for this board are either radiation tol-erant by design, like the GBTx chipset and the power supplies designed in the PH-ESE group [7], or have been qualified for a total ionising dose (TID) up to 75krad, a limit imposed by the ProAsic3 FPGA from Microsemi. The board
2.4. THE ACQUISITION CHAIN 15
Figure 2.6: Full turn acquisitions for several turns overlapped, in ADC bin values; the sum signal is above and the difference signal is below. In the red square are pointed out the samples carrying information about the position
Figure 2.7: The GEFE with the BDF
hosts a connector for an optical transceiver, that is compatible with the commer-cial SFP+, but also with the VTRx, a rad-tolerant custom optical module also developed by the PHESE group. The VTRx and the GBTx chip implement the GBT (GigaBit Transceiver) [8]. The GBT is the latency deterministic link chosen by BI for the communication between its frontends and the VFC-HD. It allows to treat the link as a transparent pipe for the data with a constant delay that can
16 CHAPTER 2. THE SPS BEAM POSITION MONITOR UPGRADE be calibrated just once at the commissioning of the instrument. Additionally it features: a protocol (GBT Frame) with a robust error detection and correction algorithm (Reed-Solomon) without the need of further interventions of the users; high payload bandwidth, 3.2 Gbps on a 4.8 Gbps communication; the availability of a radiation tolerant chipset (the GBTx and the VTRx). For environment not subject to radiation, this link can be implemented in FPGAs in conjunction with commercial optical modules; this is the case for the other end of the link, in the back-end.
2.4.3
The Back-End
Figure 2.8: The VFC-HD
The VFC-HD [1](reference on CERN Engineering & Equipment Data Manage-ment Service: EDA-03133-V3) is the board designed to be the standard back-end for the BI applications. It is an FPGA-based 6U VME 64x module with a high pin count FMC (VITA 57) slot, the possibility to connect to custom VME rear transition module (RTM), 6 small form factor pluggable (SFP) slots, 4 of which dedicated to user applications and 2 to system ones, and on board DDR3 memory. The VME standard (Versa Module Europa) is a computer bus standard largely used by the existing BI systems. The first system SFP connections is dedicated to the reception of the beam synchronous timing and triggers, the second system SFP is for Ethernet connection. The four application SFPs are meant to connect the back-end to remote digital front-ends like the GEFE; those SFPs are con-nected to the FPGA multi-gigabit transceivers taking into account the clocking requirements for the implementation of the GBT link. The FPGA is the ARRIA V GX by Altera [9]. The back-end, through the VME crate and the its CPU, is connected to the accelerator control system.
2.5. MY ROLE IN THE PROJECT 17
2.5
My role in the project
I was responsible for the design of several back-end firmware and related control software to validate and qualify the system and to find and verify possible new design solutions.
I wrote the firmware and a specific control software to test and qualify the prototype of the analog front-end; using the full acquisition chain, I collected data in the lab and from the actual beam in the SPS tunnel. Then I analysed the data acquired writing the Python scripts to extract the performance of the board under test.
In a second stage I developed and added to the firmware the processing mod-ules that will be used for the operational BPM system, to evaluate the trajectory, the capture and the orbit of the beam. I studied and implemented in hardware description language an algorithm to recognise the valid samples in the difference signal automatically, based on the sum signal.
I also participated in the qualification of the GEFE FPGA from radiation tolerance point of view, and to the qualification of the BDF performance. In both cases I developed the FW for the back-end FPGA, the SW for the control and analysis, and I personally analysed part of the results. This work, because of time constrains, will not be part of this thesis.
Chapter 3
ALPS firmware generic structure
and design flow
All the developed gateware followed the same design flow and used the infras-tructure provided by the VFC-HD base project, that will be described in this chapter.
All the FPGA logic has been developed in Verilog language, simulated using Modelsim 10.4 software, analysed and synthesized using Quartus-II 15.0 Design Software.
3.1
VFC-HD base project and design flow
The VFC-HD project provides not only the board, but also a structured base firmware in which the user can insert his application functions and use the inter-faces already implemented to have easily access to the board peripherals. The top module, called VfcHdTop, contains a system generic module, called VfcHdSystem, and an application specific module, named VfcHdApplication. The VfcHdSystem module controls all the generic features and peripherals of the board, like the VME interface, the monitoring of the voltages, and the decoding of the beam synchronous timing and triggers. The VfcHdApplication module has direct ac-cess to the application specific interfaces: the FMC connector, the 4 application SFP, the DDR3, the front panel general purpose IO and the rear transition mod-ule connections. The internal bus for both modules is a wishbone one (WB [13]) where the VME interface acts as a master. The VfcHdApplication module appears to the VfcHdSystem like a generic block connected to its internal WB bus. In the base gate ware provided to the users of the VFC-HD the application module contains a few example modules connected to the internal wishbone bus. Among those example modules there is a FPGA implementation of the GBT link connected to the 4 application SFPs. Every firmware has a memory mapped description of all the firmware registers in communication with the VME crate CPU through the WishBone bus and the VME interface. The memory space is divided in two 2Mx32b blocks, the System memory space and the Application memory space. From the memory space description is generated the driver to compile for the kernel version of the VME crate CPU (L865). When the driver
20CHAPTER 3. ALPS FIRMWARE GENERIC STRUCTURE AND DESIGN FLOW
Figure 3.1: Schematic of the system-application division of the back-end firmware and of the interfaces with the main peripherals used on the board.
is installed, with a Python script running in the CPU is possible to access all the registers described.
The VFC-HD Base project is available on BI GitLab, a platform for software and HDL development based on Git, a free distributed version control system. Any new project on the VFC starts as a local clone of the Base, containing the top module, the application module with basic example modules, and two submodules: the BI Cores (with generic synthesis and simulation cores) and the VFC-HD System (with synthesis and simulation cores specific for the System module). The two submodules are two Git repository on their own and they are not supposed to be modified by the user. Then a Git remote repository is assigned to the new project, that is not linked any more to the Base.
3.2
Clock domains
The VfcHdSystem is clocked by a 12 5MHz local oscillator. The same clock (Clk k) has been chosen as main one for the VfcHdApplication module. The use of a multi clock domain design was avoided as much as possible. Nevertheless two more domain clocks can be identified in the design: the beam synchronous timing (BST) one (BunchClock), and the reference 40 MHz frame-clock for the GBT block, derived from a PLL configured by the application itself and referenced to a 20MHz local oscillator. The data and the triggers coming from the other clock domains are synchronised as soon as possible to the Clk k domain, where all the logic for the acquisition, control and processing is developed (figure 3.2). We can observe that the data are not synchronous to the beam timing, the digitalisation 40 MHz clock comes from the 20MHz local oscillator. This is not an issue for the system, given the low bandwidth of the analog front-end.
3.2. CLOCK DOMAINS 21
Figure 3.2: Schematic of the clock domains in the application firmware. GBT-to-System
The GBT registers, pseudo-static registers to be accessed by the GBT module, are synchronised with the 40 MHz clock using Dual Port RAMs with 1 bit long address, so just two locations. The write clock is Clk k (125 MHz) and the read clock is GbtTxFrameClk40MHz k. The GBT modules receives a serial encoded data-stream; per SFP, it decodes and rebuilds the 84-bits payload of each commu-nication frame and performs data correction. The module outputs these 84-bits per SFP at the frame clock frequency of 40 MHz. From the front-end are expected four channels on a single SFP, each channel digitalized in 12-bits at 40 MHz; so every GbtTxFrameClk40MHz k period we can read in the less significant 48 bits the new data coming from the four channels. After coupling the data with the turn flag, the 49 bits are synchronised with the 125 MHz clock of the acquisition logic using a FIFO: the write clock is GbtTxFrameClk40MHz k, the read clock is Clk k; the signal produced by the FIFO alerting about the presence of a new data to read is used as a data valid flag by the acquisition logic.
BST-to-System
The control registers to tune the turn clock flag and extract the trigger for the acquisitions, both used by logic that deals with the BST timing signals, are synchronised with the BST clock using bus synch modules. The bus synch module used is just a chain of 2 registers of 32 bits, clocked by reading clock, in this case BST clock; the value of the last register is copied to the output when it is a new value (so it is different from the current value of the output) and there is not metastability (the two registers have the same value). This simple technique is tailored on our case, in which the read clock is faster then the write one and the
22CHAPTER 3. ALPS FIRMWARE GENERIC STRUCTURE AND DESIGN FLOW input is a multi-bit register almost static. The acquisition trigger pulse generated by the trigger selector is synchronous to the BST clock. It is synchronised to the 125 MHz clock domain to be used in the acquisition logic using a pulse synchroniser circuit implemented in the FPGA, the schematic is showed in figure 3.3.
BST-to-GBT
The turn clock flag pulse is synchronous to the BST clock; after latency compen-sation (treated in 3.3) the turn flag must be synchronised to the 40 MHz clock to be coupled to the data from the GBT module. For this purpose the pulse synchroniser circuit is used 3.3.
Figure 3.3: Schematic of the pulse synchroniser circuit.
3.3
The machine timing
SPS measurement systems need a reference clock synchronous to the RF cavities, a marker of the turn to identify the first bunch in the machine and a series of triggers indicating injections and extractions of the beam. For example ALPS needs the injection trigger to identify the first 50 turns of which measure the tra-jectory; the system needs also the turn flag pulse to identify a batch. This signals are distributed to the systems along the machine through the beam synchronous timing (BST [2]) optical network, clocked with a 160 MHz clock locked to the 200 MHz frequency of the cavities. The signals are encoded in a serial stream composed of 256 messages of 8 bit, the BST Bytes, each one identified by an 8 bit code, the BST Address, and validated by a strobe. Signals as the triggers are encoded in single bits of specific BST Bytes; for example the SPS injection trigger is asserted in the bit 0 of the BST Byte with BST Address 10. Each turn the stream is sent through the network and not all the messages are sent. The stream encodes the information about the following turn. The timing serial message coming from the BST arrives to the VFC-HD through the BST SFP and it is decoded by the system module in the following parallel signals:
• BST Clock signal: the clock of the BST signals domain (160 MHz). • Bunch flag signal: pulse at ≈ 40 MHz that mark the start of each bunch. • Turn flag signal: revolution flag, 23 µs periodic for SPS.
3.3. THE MACHINE TIMING 23 • BST Byte: byte of the stream encoding information as the triggers.
• 8-bit BST address: identification code of the current byte.
The BST message is generated near the RF cavities and then sent through optic fiber to the systems. Then the turn flag is not actually synchronous with the first bunch of the turn in the pick-up location; the system should compensate the latency due to the time the BST signals take to be transmitted in the fiber and the time of flight of the beam from the RF cavities to the pick-up. The TckDelay module implement this compensation. It is based on a simple counter incremented with the bunch flag signal; the counter is reset with the BST turn flag and starts counting until reaching a value programmable through software, saved in the Turn Clock Delay Control register. When the setted value is reached, a new turn flag is produced.
An other fundamental signal for the test is the acquisition trigger, and it is produced also from the machine timing. The acquisition can be triggered by software, but also by BST triggers for beam synchronous acquisitions.
Figure 3.4: Schematic of the acquisition trigger generation circuit.
Every turn the Trigger Selector module reads the BST byte stream, checking if the selected trigger is asserted. If so, the BST trigger pulse is asserted until the new turn clock flag. The BST Byte Address and bit in which reading the trigger are parameters of the Trigger Selector module, programmable by software and stored in the BST Trigger control register. During the test we used as acquisition trigger the injection trigger, coded in the bit 0 of the byte with address 10. The acquisition trigger can be delayed with respect to the injection trigger to select different windows of the cycle; a delay circuit with micro-second granularity follows the trigger selector module after a synchronization of the trigger pulse to the main clock domain from the BST clock domain. The acquisition trigger from BST is armed or disabled by software and it works in parallel with the software trigger.
Chapter 4
The experimental validation of
the Analog Front-End board
Figure 4.1: Picture of the board under test.
The prototype of the analog front-end board (reference on CERN Engineer-ing & Equipment Data Management Service: EDA-02759-V1) has been tested implementing the full acquisition chain, with a custom back-end firmware. The test purpose is to verify the functionality of the board and the correct processing of all the SPS beams, and to verify that the resolution requirements are met.
4.1
The back end application firmware
4.1.1
Specifications
The test system must be able to store the data acquired with the board under test, digitalized and selected with the timing of the machine as reference. To maximize the amount of significant data stored, given the limited memory space,
26CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD the system should give the possibility to store only selected sections of the turn,
corresponding to the beam passage. So it should be possible to save the data acquired in a selected window of the turn, for a selected number of turns, starting after a programmable delay after injection. To provide significant data for the qualification, it should be possible to store at least 100 full turns; once selected a window of ≈100 samples the system should be capable of storing up to ≈1000 turn acquisitions.
4.1.2
Acquisition logic
The acquisition module (figure 4.2), called MoposTestProject from the name of the current beam position monitor system, is composed of two parts: the Acqui-sitionControl module and the dual port RAM 256Kx48. The SRAM is controlled on one side by the acquisition logic and on the other side is connected to the wishbone bus, giving access to its content to the software for the readout of the results.
Figure 4.2: Block diagram of the MoposTestProject module. Acquisition Control
As required by the specifications of the test, the acquisition control module takes care of enabling the writing into the memory of the selected data after that the acquisition is triggered. The data comes from the GBT module as four 12-bits measurements (Sum at 40 MH, Difference at 40 MHz, Sum at 200 MHz and Difference at 200 MHz). Every new sample comes with a one clock period flag indicating when the data is available. The acquisition is controlled with the following signals:
• AcqStartPulse: generated by software (Acquisition Control register) or com-ing from the machine timcom-ing, it triggers the acquisition;
• AcqAbort : generated by software (Acquisition Control register), it stops the acquisition.
4.1. THE BACK END APPLICATION FIRMWARE 27 • MemInit : generated by software (Acquisition Control register), it writes
zeros in all memory locations.
The acquisition is configured with the following settings:
• TurnsToAcquire: 16-bits value defining how many turns acquire;
• SamplesPerTurn: 10-bits value defining how many samples (bunches) are acquired each turn, so the size of the acquisition window; given the maxi-mum turn length ≈23.45 µs and the sample rate at 40 MHz, the maximaxi-mum number of samples in a turn is 938;
• BunchToWait : 10-bits value defining the position of the bunch in the turn from which starting the acquisition.
The memory interface comprises the write enable signal, the 18-bits address bus and the 48-bits data bus; when the write enable is asserted, the data on the data bus is written in the location identified by the address on the address bus. The logic has been designed and implemented as a finite state machine with the following states (figure 4.3): Idle, Acquisition and Memory Initialization.
Figure 4.3: Finite state machine that controls the acquisition.
In Idle state the parameters signals are saved in the relative registers, the counters are resetted, the memory write enable is kept low. When an acquisition triggers arrives, the state switch to acquisition state; when a memory initialisation request comes, the next state is the relative one.
In Memory Initialisation state zeros are written in the whole memory. The status bit of Memory Initialisation On in the Acquisition Status register is as-serted. The machine gets back to Idle state when the whole memory has been reset, or if an abort signal is asserted by software.
In Acquisition state, to manage the cycles inside each acquisition counters are used as memory elements. So the outputs, i.e., the writing memory interface signals, are defined not only by the current state, but also from the input flags (turn and data available flags) and by the values of the following counters:
28CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD • TurnsToTake: 16-bits counter, in Idle state has been loaded with the Turns
to acquire value, it is decremented of one unity in every clock cycle a turn flag arrives;
• SamplesToTake: 10-bits counter, in Idle state has been loaded with the sum of the bunch to wait and the number of sample to acquire per turn, so its value is the number of data available flag after the turn flag at which the acquisition in that turn is done. It is decremented of one unity in every clock cycle if a turn flag arrives or it is arrived and if there is a new sample available. At the last sample acquisition of each turn, when the counter itself has value 1, the original value is reloaded.
• DavDelayToWait : 10-bits counter, in Idle state has been loaded with the bunch to wait value, it is decremented of one unity in every clock cycle if the turn flag arrives or it is arrived and if there is a new sample available. The original value is reloaded at the last sample acquisition of each turn, so the counter value is zero only when on the input there are the samples to store in the memory.
The data on the input must be written in the memory only when it is part of the selected window of the first defined quantity of turns after the acquisition trigger; so the data is copied on the memory data input bus, the write enable is high and the address bus is incremented at every data available flag, if a turn flag arrives or it has arrived and the DavDelayToWait counter is zero. While on acquisition state, the status bit of Acquisition On in the Acquisition Status register is asserted. The machine gets back to the Idle state if an acquisition abort occurs, or when all the samples of the last turn to acquire have been stored, so when the TurnsToTake and the SamplesToTake counters are both zero.
The logic has been designed to be functional and tested in simulation in all corner situations, performing all the combinations of zero value and maximum value of all the acquisition parameters.
Acquisition Memory
The FPGA Arria V GX provides embedded memories, based on the logic array blocks or dedicated memory resources. The embedded block RAMs offer easy and fast communication with the logic and an immediate implementation. The limit is given by the maximum size that the memory can reach and how its presence can affect the rest of the implemented logic in terms of timing issues. The FPGA model present on the VFC-HD board [9] has 15100 M10K blocks (each 10 Kb) and on 1852 MLAM blocks (each 640 bit). While the M10K blocks are ideal to build large memory arrays, the MLAB are more indicated for shallow memory arrays, optimized for implementation of shift registers, FIFO and filter delay lines. Since we require to store at least 100 full turn (every bunch in a turn, a total of almost 1K of 48 bit samples, 100 times, so 480Kb) the M10K block RAMs are more indicated to our case. Naturally, it is in the interest of the test achieving the realization of the largest memory possible. With Altera it is possible to implement a memory array generating it from the library, following
4.1. THE BACK END APPLICATION FIRMWARE 29 the configuration GUI; otherwise by describing in the hardware description code a memory array that can be identified during the analysis and the related block memory is inferred during the synthesis and assigned to the physical M10Ks by the fitter. Anyway, the designer does not have full freedom in the configuration of the single M10K block, there are constraints about the maximum configuration supported, listed in table 4.1.
Depth(bits) Programmable Width 256 x40 or x32 512 x20 or x16 1K x10 or x16 2K x5 or x4 4K x2 8K x1
Table 4.1: Supported Embedded M10K Memory Block configurations for Arria V devices; when a double programmable width is indicated, the larger refers to the implementation without parity check bits reserved [9]
As we can observe from the table 4.1, an M10K does not always use all the 10K bits, but it can preserve 2 bits every 8 bits for parity check; this solution is forced for blocks deeper than 1K locations. So out of the declared 15100 Kb, if all the blocks are implemented with parity bits, only 12080 Kb are programmable. Considering our case, with a 48 bits width memory, the difference would be in fitting 256K locations or just 128K locations, since the number has to be a power of two. In order to maximize the size of our memory array then it is important to minimize the number of blocks with parity bits. The synthesis software Quartus-II do not allows to force this parameter and automatically it tries to implements the memory array stacking a minimum number of serialised memories, so max-imising the depth of the used blocks. As consequence, configuration with forced parity bits are implemented. So for example, the description of a memory array 256Kx48b, leads the software to try to synthesize 32 lines of 48 serialised 8Kx1b M10K, that would require 1536 M10K, more than the 1510 available.
The solution found and adopted in this project is to force the software to synthesize blocks with 2K locations, describing the 256Kx48b memory as the stack of 128 2Kx48b memories, each one inferred as eight 2Kx5b memories plus two 2Kx4b memories, total 128 times ten M10Ks, so 1280 M10K, less than 1510. As consequence, the hardware description code has to control the addressing of each inferred 2Kx48b memory, not any more left to the automatic synthesis. So, out of the 18 bit memory address, the 7 most significant bits select which 2Kx48b memory access, the 11 less significant bits specify the location inside the selected memory.
On the writing port the memory is seen as arranged in 48bit words, each containing the data from the 4 12bit channels. For the readout the memory is accessed by the VME crate CPU, through VME bus and Wishbone interface.
30CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD
Figure 4.4: Structure of the Dual Port RAM implemented with M10K block RAM.
The protocol allows to read through the bus only 32 bit words, so, to keep data coherence in the memory read-out, the memory block has four different Wishbone slave interface, one per channel.
4.1.3
The test of the firmware
Every module has been tested with tailored test-benches on ModelSim, generat-ing data input and control signals and readgenerat-ing back output and status signals, checking the coherence with expected signals automatically. Following the hi-erarchy of the design, the test-bench grows, until testing the whole VfcHdTop module. Then the bit-stream produced by Quartus-II is used to configure the Arria V FPGA on a VFC-HD board and verify the functionality of the design in the lab. At first, the data stream is internally generated by a module in the FPGA outputting a 12 bit counter value emulating each of the 12 bit samples instead of the data stream from the GBT module. The aim was to test the acqui-sition logic and the communication with the software control independently from the communication with the front-end. Then the GBT module is used as input for the acquisition module and the digital front-end is connected to the VFC-HD through optical link. To test the system independently from the analogue front-end, a signal generator is used as analogue input to the ADC mezzanine on the digital front-end.
4.2
The test control software
Below we found the register map (figure 4.5).
The application specific registers are (in square brackets there are the default values in hexadecimal for the writeable registers):
• Acquisition triggers [0x00000000] and Status register, they monitor and con-trol the acquisition status, arming an acquisition trigger from the BST, or
4.2. THE TEST CONTROL SOFTWARE 31
Figure 4.5: Module registers.
asking an acquisition by software, or aborting an acquisition, or initialising the memory;
• Acquisition parameters registers, so how many samples per turn [0x00000384], the first bunch to acquire in each turn [0x00000000] and how many turns [0x000000C8];
• Data Source control [0x00000000], to choose as acquisition input between the stream data decoded by the GBT module or the data generated inter-nally;
• BST Trigger Control [0x0000000A] and BST Trigger Delay [0x00000000], to select the trigger from the BST message and manage the trigger delay in microseconds;
• Turn Flag BST Delay [0x00000000], to control the turn flag delay in bunch clock periods;
• The four memory blocks, for the Sum and Difference of the 40 and 200 MHz conditioning chains acquired.
The script RunAlps.py, single process, has an interactive structure; from a menu the user can select what function execute in an interactive mode. Before entering the interaction mode, all the control registers are set to default values.
The options in the menu are the following:
• Exit : it abandons the menu and the Python script.
• Acquisition Abort : it aborts the acquisition via the Acquisition Abort bit in the Acquisition control register, forcing the state machine to Idle state; before returning, it prints to screen the Acquisition status register value. • Set Parameters: it enters another menu, in which the user can decide which
32CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD asking for the desired value and checking if it is in the correct range; only
when a correct value is given, or the user presses the exit command, the functions returns to the Set Parameters menu. If the user does not want to set other parameter, he can get back to main menu with the exit command. • Read Status: it prints to screen the Acquisition status register value in hexadecimal and a string stating the acquisition status, if the acquisition is on going, if the trigger is armed and if the system is initialising the memory. • Initialize Memory: it starts the memory initialization process using the memory initialisation bit in the Acquisition control register, moving the state machine to the Memory initialisation state if in Idle state; then it waits for the end of the memory initialisation, reading the status register. When the initialisation is complete, the function returns to the main menu. • Read Memory: it performs a selective read-out of the memory, printing to screen the content of the desired consecutive locations from all the four memory blocks.
• Arm Acquisition: it sets the Arm Acquisition bit in the Acquisition control register, to enable the trigger from the BST message; since the arrive of the trigger clears the trigger arm, checking the Arm On bit in the Acquisition status register it waits for the trigger. Then it reads the Acquisition pa-rameters from the relative registers, saves in four buffers the content of the four memory blocks, plots the data and eventually saves them in a file with parameters, date and time.
• Clear Arm Acquisition: it sets the clear Arm Acquisition bit in the Acqui-sition Control register.
• SW Acquisition Start : it sets the SW Acquisition trigger bit in the Acqui-sition control register, moving the state machine to the AcquiAcqui-sition state if in Idle state; then it reads the Acquisition parameters from the relative registers, saves in four buffers the content of the four memory blocks, plots the data and eventually saves them in a file with parameters, date and time. • Reset BST : it sets the BST reset in the BST Control register, useful in case
of loss of lock in the communication.
• Clear BST Reset : it clears the BST reset in the BST Control register, useful in case of loss of lock in the communication.
At the end of each acquisition, to plot the data, two windows are opened sequentially. In the first window there are four plots, one per channel; in each plot on the x-axis there is the sample number after the first bunch in the turn, on the y-axis the sample value in ADC bins; the several turns are plotted overlapped. Then the user selects from keyboard a sample in the turn, an x value; the second window shows four plots, one per channel, and in each plot is represented on the x-axis the number of turn and on the y-axis the relative value of the selected
4.3. DATA ACQUISITION 33 sample in ADC bins. If the acquisition looks useful to the user, he can save the data and the relative parameters in a file, deciding file name and path in the technical network.
4.3
Data acquisition
The analogue front-end board under test has two inputs for the two pick-up signals from a single plane. It is also possible to use a beam generator to simulate the beam signal in the lab. So, after checking the correct operation of the test system in the lab, the system with the prototype under test has been connected to a pick-up in the tunnel, acquiring actual data from the beam. Then, some systematic measurements have been repeated in the lab, where it is possible to recreate all beam settings, taking the beam measurements as reference point to normalize the system in terms of beam intensity and position.
4.3.1
Beam test set-up
The board under test has been connected to the pick-up in the HCA4 hall in SPS. Then we controlled the acquisitions from the CERN Control Center, where it is possible to talk directly with the operators who are driving the accelerator and, when allowed, to ask for specific machine developments (MD) beam settings. In the table 4.2 are listed the different beam acquisition done in four days of measurements. We tried to cover the different particle species, bunch spacing, single or multi bunch, intensities; in two MDs dedicated to us we could asked for localised displacements of the beam orbit (or beam bumps).
Table 4.2: Beam measurements
User Particles Bunch Spacing # bunches Intensity Date LHCIon2 ions 25 ns multibunch ≈ 1011 18/11
SftIon3 ions 25 ns multibunch ≈ 1010 18/11
Hiradmat protons 25 ns single bunch ≈ 1011 21/11
MD3 protons 5 ns multibunch 5 · 108 21/11
MD1 protons 25 ns multibunch 9 · 1011 23/11
MD1 protons 25 ns single bunch 1 · 1011 23/11 MD3 protons 5 ns multibunch 5 · 108 24/11
4.3.2
Lab test set-up
To analyse the dependence of the measured position and of the resolution on the beam intensity, the pick-up signal has been recreated in the lab in controlled conditions, using a pulse generator. Playing with the settings of the generator it is possible to emulate single bunches or trains, 25 ns or 5 ns bunch-spaced. The generated signal goes through a common attenuator and then it is split in
34CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD two signals, each one passing through a different attenuator and representing
the signal from one of the two electrodes (figure 4.6). All the attenuators have variable gain. Varying the attenuators values it is possible to emulate intensities variations (common attenuator) and position variations (separated attenuators). Increasing the attenuation of the signal representing the top electrode of a vertical plane pick-up, for example, would cause a decrease of the difference of the two signals, becoming negative, emulating a movement of the beam towards the lower half of the pipe; but, considering that the sum of the signals is proportional to the intensity of the beam, we would emulate also a decrease in the intensity. To keep the intensity constant while varying the position it is necessary to compensate with the common attenuator. Instead, to change the common attenuator value without changing the separated attenuators emulates only an intensity change with constant position.
Figure 4.6: Schematic of the attenuators chain to emulate the signals from a pick-up plane.
To plot a linear characteristic of the position to compare with the one taken from the bumped beam measurements, I did acquisitions varying the position in 2 dB steps and keeping the intensity as high as possible and constant. To evaluate the dependence of the measurements on the intensity, I did a series of acquisitions of constant central position signals with common attenuation varying in 3 dB step, from 0 dB to 39 dB. The two test set-up have been set both for 5 ns and 25 ns bunch-spacing.
4.4
Data analysis
4.4.1
Qualitative analysis of beam measure
I checked qualitatively that the data acquired from the beam were coherent with the beam condition and acquisition moment. In each case I created four plots, one per channel, using the matplotlib library for Python. In each plot on the x-axis there is the sample number after the first bunch in the turn, on the y-axis the sample value in ADC bins; the several turns are plotted overlapped.
4.4. DATA ANALYSIS 35 Machine Development (MD3) proton beam, 5 ns spaced multibunch, very low beam intensity (5 · 108)
Proton beam for machine development, multibunch 5 ns spaced. On 21/11 I made two different acquisitions, one at injection (figure 4.7) and one at flat bottom (figure 4.8), 500 ms after the injection. Because of the 5 ns spacing the 200 channel is the more suitable to measure the beam. We can see in the injection acquisition the intensity growing in the different turns and then, at flat bottom, getting stabilised, as the position in the difference signal.
Figure 4.7: MD3 acquisition at first injection.
Figure 4.8: MD3 acquisition at flat bottom.
On 24/11 the MD3 cycle was for us. Here we asked again for multi bunch structure 5 ns spaced very low beam intensity. It is interesting here to observe two acquisitions plots: just at injection (figure 4.9) we can see the sum signal, the intensity, growing with the turns and the position in the difference signal oscillating before stabilising (figure 4.10); then in figure 4.11 we see the gradual bump rise over 1024 turns, with the beam stable in intensity while the position
36CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD is changing (figure 4.12). The bunch charge of the beam was ≈ 5 · 108, a factor 4
lower than the minimum intensity in the specifications.
Figure 4.9: MD3 multi bunch acquisition at injection.
Figure 4.10: MD3 multi bunch acquisition at injection, position measured in sample 27 over 1000 turns.
4.4. DATA ANALYSIS 37
Figure 4.11: MD3 multi bunch acquisition during bump rise.
Figure 4.12: MD3 multi bunch acquisition during bump rise, position measured in sample 27 over 1024 turns.
SPS Fixed Target (SftIon3) ion beam, 25 ns spaced multibunch, medium beam intensity (≈ 1010)
Ion cycle for the fixed target in the North Area, with several bunches, 25 ns spaced. In each cycle there are four injections, here I show the acquisitions after the first (figure 4.13) and the fourth injection (figure 4.14). Here the injections are more spaced, we can resolve them also with the 40 channel. We can also observe the position not being stable just after the injection for the injected particles, while the others have been stabilised.
38CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD
Figure 4.13: SftIon3 acquisition at first injection.
Figure 4.14: SftIon3 acquisition at fourth injection.
LHC (LHCIon20) ion beam, 25 ns spaced multibunch, high beam in-tensity (≈ 1011)
Ion beam, with several bunches, 25 ns spaced, then filling the LHC beam. In each cycle there are seven injections, and we acquired the first turns after the first, the second, the third and the seventh injection. Here I show the plots of the acquisitions at the second (figure 4.15) and seventh injection (figure 4.16); we can easily distinguish the injections in the intensity 200 signal, while they are less resolvable in the 40 channel. Anyway, because of the 25 ns bunch spacing, the difference 40 signal shows a more stable value in the various turns.
4.4. DATA ANALYSIS 39
Figure 4.15: LHCIon2 acquisition at second injection.
Figure 4.16: LHCIon2 acquisition at seventh injection.
HiRadMat proton beam, single bunch, high beam intensity (≈ 1011) Proton beam, single bunch, serving the High-Radiation to Materials (HiRadMat) Facility, where radiation tests on material samples and accelerator components are mare. I did three different acquisitions: one immediately at injection (figure 4.17); one at flat bottom, 500 ms after injection; one at flat top, when the beam has been already accelerated, 5428 ms after injection (figure 4.18). We can observe the intensity in the sum and the position in the difference varying in the different turns, while they are stable in flat top and flat bottom.
40CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD
Figure 4.17: HiRadMat acquisition at injection.
Figure 4.18: HiRadMat acquisition at flat top.
Machine Development (MD1), single bunch and multi bunch, very high intensity (1 ÷ 9 · 1011)
Proton beam in a machine development cycle for us, acquired on 23/11. At first we asked for single bunch beam, bunch charge 1 · 1011, with local orbit bumps, to control the position. Here are showed the acquisitions with a displacement of plus 8 mm (figure 4.19) and minus 8 mm (figure 4.20); we can easily observe the change in position in the difference signal in the 40 channel.
4.4. DATA ANALYSIS 41
Figure 4.19: MD1 single bunch acquisition with plus 8 mm bump.
Figure 4.20: MD1 single bunch acquisition with minus 8 mm bump.
Secondly we wanted to repeat the measurements with trains of 12 bunches 25 ns spaced, but here we had the first unexpected behaviour of the electronics. With high intensity and multi bunch structure (total intensity 9 · 1011) the
front-end gets saturation, as we can see in figure 4.21; asking for lower intensity we could observe again normal behaviour, as shown in figure 4.22.
42CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD
Figure 4.21: MD1 multi bunch acquisition at high intensity (9 · 1011)
Figure 4.22: MD1 multi bunch acquisition at lower intensity (4 · 1011).
4.4.2
Linear characteristic from beam measure
In the MD1 cycle for us, on 23/11, we could have bumps on single bunch, high in-tensity proton beam, to force the orbit to the following values: ±500µm, ±1mm, ±2mm, ±4mm, ±6mm, ±8mm. I selected a sample number, the same for all the turns, with stable difference value. In order to make a good choice, considering that in the stable area the distribution of the difference values in the same sample in all the turns looks Gaussian-like (figure 4.23), I picked as sample number the one at which the standard deviation of such distribution of the central position acquisition is minimum, the sample number 40 in this case. Then with a python script I averaged the difference values of that sample number over all the turns, giving as result an estimation of the position measured in ADC bins for all the acquisitions of beams with different displacement. The average slope of the lin-ear characteristic in ADC samples is 83 samples/mm. To convert the measured position values in µm, I normalised them, subtracting the mean value measured
4.4. DATA ANALYSIS 43
Figure 4.23: Distribution of the ADC values of the sample number 40 of each turn in the MD1 acquisition in central position.
in the central position acquisition and then dividing by the End Point Linearity Slope. As End Point Linearity Slope I took the difference between the main val-ues for the plus 8 mm position and the minus 8 mm position, divided by 16000 µm, the total displacement imposed. To evaluate the integral linearity of such characteristic, I traced the minimum square error fitting line and the absolute distance from it of each measurement calculated (figure 4.24).
Figure 4.24: On the left: in blue the interpolated linear characteristic, the red points are the actual averaged measurements from the MD1 beam acquisitions; the green dashed line is the minimum square error fitting line. On the right: the absolute error in micrometer of the measured point from the fitting line.
The same procedures have been repeated on the data acquired in the MD3 cycle for us, regarding multi bunch 5 ns spaced, low intensity proton beam. The
44CHAPTER 4. THE EXPERIMENTAL VALIDATION OF THE ANALOG FRONT-END BOARD bumps in this case are ±2mm, ±4mm, ±6mm, ±8mm. The relative plots are
represented in figure 4.25 for the Gaussian-like distribution of the difference sam-ples for the measurement in the central position, precisely the sample 44 of each turn, selected as minimum standard deviation point in the stable area; figure 4.26 for the averaged position measured with different displacements and the linearity error seen as absolute distance from the minimum square error fitting line. The average slope of the linear characteristic in ADC samples is 96 samples/mm.
Figure 4.25: Distribution of the ADC values of the sample number 44 of each turn in the MD3 acquisition in central position.
Figure 4.26: On the left: in blue the interpolated linear characteristic, the red point are the actual averaged measurements from the MD3 beam acquisitions; the green dashed line is the minimum square error fitting line. On the right: the absolute error in micrometer of the measured point from the fitting line.
4.4. DATA ANALYSIS 45
4.4.3
Resolution from beam measure
The resolution of the system is a fundamental parameter of the BPM. The design specifics require to reach a certain resolution, depending on the intensity (bunch charge higher or lower than 1010) and on the kind of measurement (orbit or trajectory). The beam acquisitions we have allow us to analyse two extreme cases, in terms of beam intensity: MD1 single bunch beam has very high bunch charge (1011) while MD3 multi bunch beam has very low intensity bunch charge (5 · 108), lower than the minimum foreseen by the specifications for normal operation. As we will see, this has a big impact on the resolution value.
On the Concepts and Glossary for the Specification of the Beam Instrumenta-tion [11] the resoluInstrumenta-tion is defined as the smallest increment that can be induced or discerned by the measurement device within given conditions. The resolution usually arises from systematic (ns(t)) and random (nr(t)) noise effects. If our
measure is m(t) and the true value we want to measure is s(t), we can write: m(t) = s(t) + ns(t) + nr(t)
In the case of the trajectory measurement: t would be the turn; s(t) would be the actual position of the beam at turn t passage through the pick-up; ns(t) would
be the sum of the systematic errors, having a mean of zero as the quantization error of the ADC or a non-zero mean, like an error caused by an asymmetry between the two logarithmic amplifiers used in the 40 channel; finally nr(t) would
be the sum of random errors caused by the noise in the instrument or by random fluctuations of the influence quantities, all having a mean of zero. It is interesting to observe that s(t), even without bumping the beam, is not constant over several turns, because of the beam dynamics it oscillates around an average position value s0. Then we can write:
m(t) = s0+ ∆s(t) + ns0+ ∆ns(t) + nr(t) = s0+ n0+ (t)
Where the term (t) sums up the variation due to random noise, zero-mean components of systematic errors, beam dynamics; so our measurement noise. Ideally, averaging an infinite number of trajectory measurements of the same nominal beam, we would obtain:
m0 = s0+ ns0
Since our system has not been calibrated and we are not using an other measurement system in parallel, we can not distinguish the systematic error ns0
from the real value s0. Anyway we can have an approximation of s0+ns0averaging
an huge number (N ) of turn acquisitions of beam with nominal position s0. From
the measurements we can so extract an estimate of the statistical distribution of (t):
(ti) = m(ti) − s0+ n0 ≈ m(ti) − ¯m = mi− ¯m i ∈ [1, N ]
Where ¯m is the average of the measured trajectories and mi a more synthetic
expression of m(ti), the realizations of the random variable M . Then, if the
