Universit`
a di Pisa
DIPARTIMENTO DI INGEGNERIA DELL’INFORMAZIONE Corso di Laurea Magistrale in Ingegneria Elettronica
Tesi di laurea magistrale
A second order ∆Σ converter
for quasi-DC signals
Candidato:
Vladimir Pietro Cravero
Matricola 451542
Relatore:
Prof. Paolo Bruschi
Correlatori:
Prof. Massimo Piotto Ing. Francesco Del Cesta
Abstract
This thesis deals with the design of a ∆Σ (delta sigma) analog to digital con-verter and it encompasses the design space exploration, the subsequent high level design and simulation and finally the electrical design and verification. The first stage of the converter is the actual ∆Σ modulator that, through oversampling, shapes the quantization noise greatly reducing its in band portion. Great care has been put in the modulator design to reduce flicker noise and offset effects on the output signal since our target input signal will have most of its power near DC.
After digitalization the signal must be low pass filtered and decimated in order to increase its precision to our target value, 16 bits. A single stage digital filter has been designed: a CIC decimator implementing a third order sinc low pass filter was designed and tested.
Contents
Introduction 1
1 Analog to Digital converters 3
1.1 An historic introduction . . . 3
1.2 Analog to Digital converter types . . . 5
1.3 Nyquist rate and oversampling ADCs . . . 6
1.4 The Delta Sigma ADC . . . 10
1.4.1 The modulator . . . 10
1.4.2 The digital filters . . . 13
1.4.3 Multibit modulators . . . 14
1.4.4 Limit cycles . . . 15
1.4.5 Dead band. . . 17
1.4.6 Zeros optimization . . . 19
1.5 Design and simulation tools . . . 20
1.5.1 The delta sigma toolbox . . . 20
1.5.2 Cadence Virtuoso . . . 22
2 High level design 23 2.1 Data acquisition systems . . . 23
2.2 The proposed solution . . . 27
2.3 Modulator design and testing . . . 29
2.4 Filter design and testing . . . 38
2.5 Spectral estimation in Delta Sigma converters . . . 41
3 Electrical design and testing 45 3.1 The modulator . . . 45
3.1.1 Integrators topology . . . 46
3.1.2 Operational amplifiers . . . 51
3.1.3 Offset cancellation techniques . . . 60
3.1.4 Capacitors sizing . . . 61
3.1.6 DAC . . . 64 3.1.7 Switches . . . 67 3.2 Digital filter . . . 68 3.3 Clock generation . . . 73 4 Simulation results 74 4.1 Operational amplifier . . . 75 4.1.1 Frequency response . . . 75 4.1.2 Output swing . . . 76 4.1.3 Noise analysis . . . 77 4.2 Comparator . . . 79 4.3 Pass gates . . . 86 4.4 Modulator . . . 88 4.5 Full system . . . 91
5 Conclusions and future developments 95 5.1 Conclusions . . . 95
5.2 Future developments . . . 96
A Acronyms 97
List of Figures
1.1 The Electron Beam Coder . . . 4
1.2 A simple converter structure . . . 6
1.3 Converter simplified model . . . 7
1.4 Oversampled converter . . . 8
1.5 Quantization noise power spectrum . . . 9
1.6 ∆Σ ADC top level structure . . . 10
1.7 ∆Σ modulator. . . 10
1.8 Second order ∆Σ modulator.. . . 12
1.9 Dual stage low pass filter . . . 13
1.10 A z-domain simple linear model for a 1st order modulator . . 15
2.1 A data acquisition system . . . 24
2.2 DAS: chopped inamp . . . 26
2.3 DAS: chopped converter . . . 27
2.4 DAS: system level “chopping” . . . 27
2.5 Empirical SQNR limit for 1 bit modulators of order N. . . . 30
2.6 Noise transfer function . . . 31
2.7 Time domain simulation . . . 33
2.8 Frequency domain simulation . . . 34
2.9 Input output characteristic . . . 35
2.10 Input output characteristic: low side particular . . . 36
2.11 Our reduced CIFB structure . . . 38
2.12 CIC filter transfer function . . . 40
2.13 CIC filtered output and modulator input . . . 41
2.14 Some normalized, 100-samples windows. . . 43
3.1 Modulator structure . . . 46
3.2 First integrator schematic . . . 47
3.3 Second integrator schematic . . . 49
3.4 Operational amplifier schematic . . . 52
3.5 Noise generator . . . 53
3.7 Dynamic CMFB with AC path. . . 60
3.8 Chopper topology . . . 61
3.9 Latched comparator . . . 63
3.10 D latch . . . 65
3.11 One bit DAC . . . 66
3.12 Pass gate . . . 67
3.13 CIC structure . . . 69
3.14 Non overlapping clock generator . . . 73
4.1 Operational amplifier test circuit . . . 75
4.2 Operational amplifier frequency response . . . 76
4.3 Output swing: DC sweep . . . 77
4.4 Output swing: ramp . . . 78
4.5 Operational amplifier total input referred noise. . . 79
4.6 Input differential sweep, vcm= 900 mV . . . 80
4.7 Input differential big sweep, vcm= 900 mV . . . 81
4.8 Input differential sweep, transition. . . 83
4.9 Input differential big sweep, transition . . . 84
4.10 First good transition . . . 85
4.11 Last good transition . . . 85
4.12 Pass gate test circuit . . . 86
4.13 Passgate resistance . . . 87
4.14 Modulator DC sweep test . . . 89
4.15 Modulator chopper test . . . 90
4.16 Full system DC sweep test . . . 91
4.17 Full system chopper test . . . 92
4.18 Full system montecarlo test: chopper off . . . 93
List of Tables
2.1 Our modulator specification . . . 29
2.2 CIC filter design parameters . . . 39
3.1 The modulator coefficients . . . 46
3.2 Calculated widths and lengths . . . 57
3.3 Transistor dimensions for our op amp. . . 58
3.4 Capacitors’ ratios . . . 61
Introduction
In the smartphone and wearable electronics era the environment awareness has become a necessity for competitive devices. We can easily find many different sensors in a single hand held apparatus, and each of them needs its analog readout to be properly treated. The need for small, accurate and power saving analog to digital converters has thus increased exponentially. There are two types of ADCs: Nyquist rate converters and oversampled converters. As the name suggests, Nyquist rate converters sample the ana-log signal at a frequency that is twice the signal bandwidth. While keeping the sampling frequency as low as possible is great for wide band signal, such as in telecommunications, some special techniques are required to achieve high precision. Matching error is reduced making bigger devices, and some-times trimming is inevitable. A big device takes more space on the die and usually dissipates more power, while any additional manufacturing step, as trimming, adds up to the cost of the final product. Oversampled converters transfer these problems into the digital domain: the input analog signal is sampled at a frequency much higher than the Nyquist rate, then converted with a low precision ADC in order to produce a fast bit stream. A bank of digital filters low passes the bit stream producing a slower but more accurate digital stream. Oversampled converters have a big downside though: if the signal bandwidth is too wide, oversampling is not practical, or not possible at all. This is not true for many sensors though, where bandwidth is limited to 1 kHz or less. Oversampled converters are then a perfect match for slow sensors where the bandwidth is limited but high precision is required.
This thesis deals with the design of an oversampling analog to digital converter featuring small bandwidth and high resolution. Great care was put into limiting the offset and the flicker noise since our circuit presents such a narrow bandwidth and the input analog signal is supposed to have much of its power near DC. Our particular target application is to digitize data from an anemometer through an instrumentation amplifier: since the sensor’s core consists of thermal devices the bandwidth will be quite small. In chapter 1, after a brief historical introduction, we will present the
chosen ADC topology, its limitations and features and the tools we used to design our solution. We will also note some of the main difficulties the designer must tackle when dealing with such a project.
In chapter 2 the first part of the design process is presented: we define the specifications, analyze some design choices and make heavy use of high level design tools such as Matlab. High level design is recommended when dealing with a ∆Σ modulator: long transient simulations are necessary and doing them with an high level tool drastically reduce computation time.
In chapter 3 we perform the electrical circuit design and simulation. A ∆Σ modulator is composed of many building blocks and we wanted to design something from scratch, leaving no aspect unexplored or approximately implemented.
In chapter 4we present all the simulation results and discuss them com-paring them with the expected outcome. All the main components were thoughtfully tested and simulated to ensure a robust design, staying as much as possible away from critical corners in the design space.
Finally, in chapter 5, a critical debate of our design is reported together with some insights on possible future development.
Chapter 1
Analog to Digital converters
1.1
An historic introduction
ADCs have been around since a long time ([1], Chapter 1). Digital data is easier to handle, to transform and is virtually immune to noise. A digital conversion for data transmission is then very attractive.
The first ADC brings us back to a 1926 paper by Paul M. Rainey: it describes a system conceived to transmit a document over a telegraph line, much like a modern fax does. The transducer consisted of a photocell used to mechanically scan the original copy of the document. The output current was fed to a galvanometer that deflected a narrow beam of light through a small mirror fixed to its axle. The deflected beam illuminated one of 32 photocells connected to a relay matrix that generated a 5 bits signal. The bits, along with the position of the scanner, were serialized through a rotating electromechanical commutator and transmitted over an ordinary telegraph line.
On the receiving side the data was de serialized and the five bits con-trolled a resistor network that powered a lamp. The light intensity was proportional to the photocell readout and was focused on a photographi-cally sensitive receiving plate, actuated by a system controlled by the analog scanner position signal. The operator on the receiving station only needed to wait for the “printing” process to be completed in order to retrieve a somewhat accurate copy of the original document.
Although this device may seem quite primitive nowadays, it illustrates several key concepts of a modern PCM system: quantization of the analog signal through a “flash ADC”, serialization of the digital data and recon-struction of the original signal using an “interpolating light DAC”. This paper was unfortunately forgotten until 1937 when Alec Harley Reeves
rein-Electron gun
Y Deflectors
Shadow Mask
Collector
Figure 1.1: The Electron Beam Coder
vented PCM taking full advantage of existing vacuum tube technology. His ADC was what we would call today a ramp-compare ADC and effectively is one of the first all-electronic data converters on record.
The project was shared with the Bell Laboratories that, since 1940 and during World War II, conducted studies on a speech digitalization system code-named Project X. Unfortunately most of the wartime results were not published until several years later because of secrecy issues, but today we know that they developed a PCM communication system that included a 5-bit, 8kSPS successive approximation ADC featuring logarithmic quanti-zation. Their ADC was based on an electron beam coder, a vacuum device designed specifically to perform analog to digital conversions. A sketch of such a device is shown in figure 1.1.
A fan-shaped electron beam, spread along the x axis, is deflected along the y axis by the input analog voltage. Before the collector there is a shadow mask with different hole patterns per each y level. The collector translates the light pattern into bits that are the digital output signal. Their device was capable of sampling at 96kSPS with 7-bit resolution and is the first electronic flash converter. Later devices, developed just before solid state technology started to rise, were capable of 12MSPS sampling rates at a 9 bits resolution.
The first commercial data converters were produced in the mid 1950s and since then the evolution of converters proceeded rather quickly, with improvements each year. The firs noise shaping modulator appeared in 1954 and the name Delta Sigma was coined in the 1962. Crystal Semiconductor produced the first 16 bits ∆Σ commercial converter in 1988 and by the
mid 1990s ∆Σ modulators market share started to grow. Nowadays the ∆Σ converters are widely used and studied and they probably represent the future of analog to digital conversion.
1.2
Analog to Digital converter types
Since many types of analog to digital converter exist we will give a brief overview on some of the most common structures, highlighting pros and cons.
Flash A flash ADC, also called direct conversion ADC, features a bank of comparators that simultaneously sample the input signal. The comparator outputs feed a logic network that produces the appropriate output code. Flash converters are very fast, achieving sampling rates in the GHz range, but they are usually limited to 8 bits resolution since the number of required comparators is 2n− 1 for n bits. A big resistor network is also required, and matching between all the resistances is critical and often requires some post processing, such as trimming.
Successive approximation The successive approximation ADC uses bi-nary search to convert the analog input. It requires an internal DAC and a memory register, plus some digital control circuitry. The SAR converter tries to guess the input signal as VR/2where VR is the input range, converts
it with the DAC and compares it to the input. Depending on the result of the comparison the next guess will be VR/4or 3VR/4, and so on. In an n bits
converter a total of n comparisons are needed. This ADC is slower than a flash converter but higher resolution can be achieved.
Ramp compare The ramp compare converter has an internal sawtooth wave generator. When the wave starts to rise a timer is also started, while the input sample is compared to the wave. When the comparator output flips, meaning the sawtooth overtook the input sample, the timer is stopped. The time elapsed is proportional to the input voltage. Unfortunately, the sawtooth wave frequency is usually sensitive to temperature so some sort of compensation is necessary. The same sawtooth signal can be used to simultaneously convert multiple inputs though, so this kind of converter is indicated when an high level of parallelism is needed.
Pipelined A pipelined ADC consists of several comparator stages each featuring a smaller input range. The first stage computes the MSB then
feeds the second stage the error resulting from its very coarse conversion, i.e. the difference between the input and the analog representation of its conversion result. Each stage adds a bit of precision and one unit of de-lay, but thanks to the pipelined nature of the converter the throughput is constant also for a large number of stages. In a popular variation of this architecture, the single stages consist in low resolution flash converters (e.g. n = 4 bit). In this way a smaller number of stages is required with benefits in terms of latency.
Frequency or Time converters These ADCs feature a voltage to fre-quency or a voltage-to-time converter, then the frefre-quency or time is digitally measured through common and simple techniques. These converters do not require a complicated analog front end unless great linearity or little temper-ature dependency are needed, and they allow complete insulation between the signal source and the digital measurement circuit.
It is important to note that no hypothesis was made about the sampling frequency, i.e. any of the above converters works from Nyquist rate up to any higher frequency, the only limit being other design constraints. The ∆Σ converter inherently is an oversampled ADC and was then excluded from the list. In the next section a comparison between Nyquist rate and oversampled converters will be carried out.
1.3
Nyquist rate and oversampling ADCs
In this section we will discuss the advantages of an oversampling converter over a Nyquist rate converter. A Nyquist rate converter is an ADC whose
converter
vin D
Figure 1.2: A simple converter structure
sampling frequency is fs = 2BS where BS is the input signal bandwidth, while in an oversampling converter fs > 2BS. Referring to figure1.2, vinis the input analog voltage while D is the output code made of n bits: there are thus 2n possible output codes. The output data is a digital representation of the input analog voltage. The converted voltage is then:
v(c)in , VREF
where VREF is the reference voltage and ∆ is the LSB value.
We know that the output converted voltage can not be equal to the input because of quantization error vnq:
vnq , v (c) in − vin
If we assume that quantization is the only non ideality, we can schematize our converter as in figure 1.3. It is important to notice that the output is
++
vin v(c)
in vnq
Figure 1.3: Converter simplified model digital but is represented by its equivalent voltage vin(c).
If the input signal varies “rapidly enough”, and its variations are wider than one LSB the power spectral density (PSD) of the quantization noise (vnq) can be considered flat on the whole discrete time band, i.e. −f2s,f2s. In addition, the probability distribution of vnq can be considered uniform over the interval −∆
2, + ∆ 2, so that: v2 nq = 1 ∆ Z −∆2 −∆ 2 e2de = ∆ 2 12
. Since the quantization noise is spread over an fs wide band: Svnq =vnq2
1 fs
If fs is wider Svnq is reduced. If our signal occupies a narrow band with respect to fs we can filter it after digitalization, reducing the total noise.
To give a measure of the oversampling benefit we should now introduce
the dynamic range DR , VREF
vnq . When dealing with analog to digital
converters referring to the number of bits is usually enough, but we want our analysis to include the dynamic range because it is a universal figure of merit, not tied to the converters’ world.
converter filter
vin D
Figure 1.4: Oversampled converter
Performing some manipulations: DR = VREF vnq = VREF ∆ √ 12 =√12VREF ∆ = √ 12VREF 2 n VREF = 2n·√12 solving for n: n = log2(DR) − 1 2log2(12) ≈ log2(DR) − 1.79 (1.1) Equation (1.1) provides a fundamental relationship between the dynamic range and the equivalent number of bits, or ENOB, and will be thoroughly used in the subsequent sections.
If one can build a converter that features a lower in band noise power v0nq < vnq it is possible to calculate the gained bits by means of equa-tion (1.1): DR0 = VREF v0 nq = VREF vnq vnq v0 nq = DR vnq v0 nq n0 = log2(DR0) −1 2log2(12) = log2 DR vnq v0 nq −1 2log2(12) = = log2(DR) −1 2log2(12) + log2 vnq v0 nq = n + log2 vnq v0 nq
The bit gain is then defined as:
∆n , log2 vnq v0
nq
For an oversampled converter we can define the oversampling ratio as:
OSR , fs
2BS
(1.2) Let us assume that after the converter we have an ideal low pass digital filter of band BS, as in figure 1.4. The quantization noise power spectrum
-BS BS -fS/2 -BS BS fS/2
SnNR
SnOVR
Figure 1.5: Quantization noise power spectrum
before the filter is depicted in figure 1.5, where: SnN R= ∆2 12 · 1 2BS SnOV R = ∆2 12 · 1 fs These equations finally lead to:
SnOV R =
SnN R
OSR (1.3)
We can now calculate the total quantization noise power as a function of oversampling and finally compute the gained bits:
D vnq0 2E= SnOV R· 2BS = SnN R OSR2BS = hvnq2i OSR ∆n = log2 vnq v0 nq = 1 2log2(OSR) (1.4)
Equation (1.4) is a great result: there seems to be no limit in the resolu-tion increment deriving from higher sample rates. Unfortunately a mere oversampled converter followed by a low pass filter is quite inefficient: to gain a single bit the sampling frequency must be quadrupled. To give some numbers, if OSR = 256 then ∆n = 4. In addition the whole idea fails if the input is a DC signal: the quantization noise power spectrum is a delta in the origin and there is no way for the low pass filter to get rid of it.
Since our main interest lies in low frequency signals, an oversampled comparator, although a step forward, is not enough.
1.4
The ∆Σ ADC and its characteristics
The ∆Σ analog to digital converter can be divided in two main sections: the modulator and the filters bank: see figure 1.6. These two sections have been designed separately and are fairly independent thus will be examined in two different sections.∆Σ filters
u v
Figure 1.6: ∆Σ ADC top level structure
1.4.1
The modulator
The modulator is the core component of a ∆Σ analog to digital converter. The analog input signal is sampled at its input and a bit stream is produced at its output. A schematic block diagram is provided in figure 1.7 (top). As in figure 1.3 we will assume that the only effect of the digitizer is the
− + F (s) ADC DAC u(s) v(s) − + F (s) ++ u(s) n(s) v(s) Figure 1.7: ∆Σ modulator
quantization noise, while the DAC is ideal. This leads to the simplified model depicted in figure1.7, on the bottom. Inspecting the diagram we can easily write: STF(z) , v(z) u(z) = F (z) 1 + F (z) NTF(z) , v(z) n(z) = 1 1 + F (z)
where the STF is the Signal Transfer Function while the NTF is the Noise Transfer Function1. It may appear clear that a wise choice for F (z) can lead to noise reduction, at least in the signal band.
If F (z) is an ideal integrator: F (z) = z −1 1 − z−1 STF(z) = z−1 NTF(z) = 1 − z−1 (1.5)
We can see that the STF is just a delay, so the signal is accurately re-produced at the output, while the NTF computes the noise discrete time derivative. To better understand what happens to the noise it is worth moving into the frequency domain. Making the substitution z = ejωT in equation (1.5) we get: NTF(jω) = e−jωT2 2j sin ωT 2 NTF(jω) 2 = 4 sin2 ωT 2
were the power spectral density was also calculated. The T parameter that we used to switch domains is the inverse of the sampling frequency fs, so ωT = πff
s holds. If we assume f fs the above PSD becomes:
NTF(f ) 2 ≈ 4π2f2 f2 s (1.6) Let us check when the condition f fs holds in a ∆Σ modulator. We introduced the OSR in equation (1.2): OSR = fs
2BS. In a good oversampled
converter we can assume OSR 1, working from that we get fs 2BS. Since we are interested in the NTF in the signal band also f < fs holds. We finally get:
f < BS < 2BS fs ⇒ f fs
Equation (1.6) provides a fairly good approximation in the signal band then. We shall now compute the total in band noise power in order to calculate 1It is worth stressing that we are examining the system assuming that only
quan-tization noise is present. We will also refer to it just with the word noise from now on.
the bit gain ∆n as a function of the oversampling ratio. D v0nq2E= Z BS −BS SnOV R· |NTF(f)| 2 df = Z BS −BS SnN R OSR · 4π2 f2 s f2df = = SnN R OSR · 4π2 f2 s ·f 3 3 BS −BS = SnN R OSR · 4π2 f2 s 2BS3 3 = = SnN R· 2BS OSR · π2 3 2BS fs 2 =vnq2 π 2 3 1 OSR3 =⇒ vnq v0 nq = √ 3 π OSR 3 2
The bit gain is now higher than before since the OSR coefficient is 32:
∆n = log2 √ 3 π ! +3 2log2(OSR)
With OSR = 256, as before, ∆n ≈ 11.1: for the same OSR the preci-sion is nearly triple what the mere oversampled converter granted. The log2
√ 3 π
≈ −0.86 is a small price to pay for the increased 3/2 coefficient.
All the above calculations are true if the modulator is followed by an ideal low pass filter. Since the modulator output is a digital bit stream, a digital filter will be used and will be discussed in section 1.4.2.
Second order modulator The ∆Σ modulator can be improved in many
ways. A widely used modification consists of adding an integrator in the loop, as shown in figure 1.8.
− + z z−1 +− z z−1 ADC DAC u(s) v(s)
Figure 1.8: Second order ∆Σ modulator. After some calculations we find:
and finally: ∆n = log2 √ 5 π2 ! +5 2log2(OSR) The price to pay is now higher since log2
√ 5 π2
≈ −2.14, but for the usual OSR = 256 we get ∆n ≈ 17.86, so there’s an overall improvement.
1.4.2
The digital filters
The low pass digital filtering following the modulator is key to achieve the promising results discussed in section1.4.1. Unfortunately, even in the dig-ital domain, an ideal low pass filter is not feasible thus some compromises are necessary. In this section we will discuss some low pass filtering archi-tectures and their pros and cons.
In [2], Section 1.3, a multistage low pass filter is suggested. In a 2nd order low pass modulator the NTF rises at 12 dB per octave, building a low pass filter with a slope much greater than this is not too difficult but often impractical and worthless. Since the sampling frequency might be quite high building such a filter in a single stage can also prove quite expensive, hence a dual stage approach will be illustrated. A block schematic is given in figure 1.9. The intermediate frequency fD must be chosen and as usual
sincK ↓ n1 IIR or FIR ↓ n2
from ∆Σ fs fD 2BS to DSP
Figure 1.9: Dual stage low pass filter
there is a trade off for its value. In [3], Section 3.5, two guidelines are given to design a low pass filter for a ∆Σ modulator:
a. the LP filter should fall faster than the NTF rises near BS
b. the gain of the first stage around multiples of fD must be lower than the NTF gain in the signal band
The first condition insures that as little noise as possible is left in the output digital signal, while the second condition guarantees that the folded noise contribution due to decimation is minimal. Both these conditions require the sinc order K to be greater than the modulator order L, usually K = L+1 is enough. In our case a sinc3 filter will be employed.
The above guidelines help us in choosing an appropriate value for fD: a lower intermediate frequency reduces the speed requirements and the com-plexity of the second filter, but increases the folded noise in the baseband. An acceptable compromise [3, p. 88] for the intermediate frequency is fD = 8BS, i.e. an intermediate oversampling ration OSRD = 4.
The second filter might be an FIR or IIR, but thanks to the down-sampling carried out by the sinc the transition band requirements are quite relaxed and a steep response can be achieved using less taps than the higher sampling frequency would have required. Single stage FIR filtering is used in application where linear phase is fundamental, such as high quality digi-tal audio, but in our case there is no need to have a precise phase response. The second filter can also compensate for the in band “droop” introduced by the sinc filtering. A sinc low pass filter is not flat and if the signal band-width is not much less than the first null frequency the output signal is distorted: higher frequency components are attenuated. The second filter can compensate this behavior with an higher gain at higher frequencies.
After careful examination of the pros and cons of a multistage filter we opted for a single stage architecture using only a third order sinc filter. Our main goal is to develop a reliable platform to learn how to deal with the problematics associated with ∆Σ converters so we decided to keep the non essential parts as simple as possible. As will be discussed in section 2.4 the advantages of a multistage filter were not so strong in our design, moreover given our slow output sampling rate droop compensation can easily and cheaply be implemented in software.
1.4.3
Multibit modulators
Another way to increase the precision of a ∆Σ modulator is increasing the quantizer resolution. The feedback DAC must be modified accordingly to match the quantizer number of bits, and that is where the big disadvan-tages lie. A single bit DAC has only two possible analog outputs thus being inherently linear. If the number of levels is increased, linearity must be assured through other usually expensive means, like laser trimming. The DAC linearity is fundamental because thanks to the feedback loop its out-put is forced to follow the modulator’s inout-put. If the DAC presents some nonlinearities it can work properly only if its input is somewhat distorted, but its input is the modulator overall output, and a distortion on the output is of course an undesirable effect.
Multibit modulators exhibit some advantages though, the most impor-tant being the resolution increase other things being equal. When speed is a concern, e.g. in analog video digitalization, multibit often represents the
only feasible solution. The use of a multibit quantizer also facilitates higher order loop transfer function design: high order modulators often oscillate at low frequencies because the quantizer is overloaded. Avoiding overload in a 1-bit quantizer is difficult because its gain can not be defined.
Apart from trimming there are some advanced techniques that help in-creasing the DAC linearity, such as dynamic elements matching. It consists in swapping appropriate components at a certain frequency, e.g. in a simple ladder DAC all the resistors can be interchanged. If the swapping occurs fast enough the “mismatch noise” is effectively modulated, hopefully out of the signal band. Sometimes the swapping is pseudo randomized so that the mismatch noise is even more white-noise like and subsequent noise shaping techniques are more effective in getting rid of it.
Our converter will feature high resolution, nevertheless the input band-width requirement is quite relaxed so we can afford an high OSR, sticking with a single bit quantizer.
1.4.4
Limit cycles
A ∆Σ ADC behaves quite nice for a certain class of signals: all the results obtained in the preceding sections are based on the assumption that the input analog signal changes enough, making the quantization noise flat. Since we are interested in converting very low frequency signals the ∆Σ behavior with DC input was investigated. Let us consider the simple first
− + + + Q z−1 z−1 U (z) Y (z) V (z)
Figure 1.10: A z-domain simple linear model for a 1st order modulator order modulator given in figure 1.10. In the time domain it implements the following equation:
y(n) = y(n − 1) + u(n) − v(n − 1) where v(n) = sgn(y(n)). This finally leads to:
It is worth noting that since the DAC is considered a unity gain function all the voltages should be normalized to the reference voltage.
Let us assume a constant input u = a/b with 0 < a < b odd positive
integers with no common factor. The initial state y(0) is also given, its absolute value being less than unity, i.e. less than VREF. If our converter is working well, the average of the digital output will be an accurate represen-tation of the input. If we look at the first b samples of v they will contain
a+b
2 samples of 1 and b−a
2 samples of −1. The average of the output is a/b so that the total net input for the integrator after b clock cycles is zero, meaning that the modulator state at t = bT is exactly the same it was at t = 0: the output waveform is periodic of period b.
This sequences are called limit cycles and are produced when the input voltage is a rational constant value. It is possible to demonstrate that if a or b is even there is still periodicity [3]. It is worth noting also that limit cycles may be present even for slowly changing signals: if the analog input stays near enough a rational value for some time a cycle could start and be present at the output.
For a second order modulator there is an empirical formula that connects the input DC level and the limit cycle’s harmonics[2, p. 86]:
f0 = kfs|Adc| 2∆
where k > 0 is an integer, ∆ is the quantization step size, fs is the sampling frequency and 0 ≤ Adc< 1 can be calculated as:
Adc = 1 − 2 2n vin− 2n 2 = 1 − 1 2n−1 vin− 2n−1
where n is the converter number of bits and vin is expressed in LSB. Adc represents a normalized distance between the input signal and the input limits. If we are working with a 16 bits converter and vin = 32 then Adc ≈ 976 × 10−6. The first limit cycle harmonic would probably end well in the signal band, together with higher order harmonics. It should be noted that these disturbances are generated by DC signals that are near the input limits: to avoid the problem it is possible to restrict the input limits.
Limit cycles do not represent instability of the loop but they are an inherent characteristic of the ∆Σ modulator. It’s important to note that for DC inputs near the input limits the limit cycle first harmonic may well fall in the signal band, possibly with a number of higher harmonics. The presence of this disturbance is highly undesirable: limit cycles are usually not very powerful but they are present at the converter output untouched.
There are some techniques that help avoiding limit cycles formation, such as dithering. The input signal is summed with a small pseudo random signal so that the input will never stay too near to a rational constant value. Dithering also help in whitening the quantization noise and can prove useful also if limit cycles are neglected.
In our design we did not implement any technique to avoid limit cycles. Since our modulator is an exploratory prototype we decided to keep it as simple as possible, leaving advanced topics to be explored in future versions.
1.4.5
Dead band
∆Σ modulators exhibit a somewhat exotic behavior that depends on the gain of the op amps used to implement the integrators needed for the loop filter function[3, pp. 51 to 53]. Let us start with a first order modulator, assuming that the initial state y(0) = 0 is known, and that a small positive DC input u0 is applied to the modulator. Working from equation (1.7):
y(1) = y(0) + u0− sgn(y(0)) = u − 1 < 0 y(2) = u0− 1 + u0+ 1 = 2u0 > 0
y(3) = 2u0+ u0− 1 = 3u0− 1 < 0
and so on. The output is alternating between −1 and +1. We can write a general formula for y(k):
y(k) = (
ku0− 1 if k is odd
ku0 if k is even
Since we expect the modulator to work, the alternating pattern depicted above must change at some point in time: when ku0 − 1 ≥ 0 we will have two consecutive +1.
If the integrator in the filter is lossy because the op amp gain A is finite its transfer function becomes:
H(z) = p
z − p, where p = 1 − 1 A then equation (1.7) becomes:
Under the same conditions given at the beginning of this section: y(1) = y(0) + u0− sgn(y(0)) = u − 1 < 0
y(2) = pu0− p + u0+ 1 = (1 + p)u0+ (1 − p) > 0
y(3) = p(1 + p)u0 + p(1 − p) + u0− 1 = (1 + p + p2)u0− (1 − p + p2) < 0 · · ·
Again it is possible to derive a general formula:
y(k) = k−1 X i=0 piu0+ (−1)k k−1 X i=0 (−p)i (1.8)
As before we are seeking for some condition that will stop sgn(y(k)) from alternating: this requires that the magnitude of the first term of equa-tion (1.8) becomes larger than that of the second term. We can solve the geometric series assuming k → ∞:
u0 1 − p > 1 1 + p that gives: u0 > 1 − p 1 + p = 1 2A − 1 ≈ 1 2A (1.9)
The result given in equation (1.9) is of great importance: a dc (normalized) input smaller than1/2Awill produce no effect on the converter output.
For a second order modulator the dead zone behavior will be better since the open-loop gain of the loop filter is proportional to A2, thus we expect the dead zone width to be proportional to 1/A2. In [3, pp.77-78] the
dead zone width is calculated as the largest dc input that can maintain a particular 2-period limit cycle, here we will only give the final result:
|u0| < 3 4
1
A2 (1.10)
It’s worth to point out that equation (1.9) refers only to half dead zone, so the coefficient is slightly worse for a second order modulator, but this difference is greatly compensated by the A2 at the denominator.
The results presented in this section are based on solid math but the model used for the modulator is not perfect thus the dead zone width will need to be verified during the design process and when a prototype is even-tually built.
1.4.6
Zeros optimization
So far, we have considered delta-sigma modulator where the input signal and the feedback signal (dac output) are processed by simple integrators. More generally, an arbitrary, two-input filter (the ”loop filter”) can be used to process the input and feedback signal and produce the quantizer input.
For a second order low pass modulator it is possible to calculate a zeros location that minimizes the in band quantization noise[3, sec. 3.4.5]. These optimized zeros are no longer in DC (as in the case of simple integrators shown in figure 1.7, on top) but shift up a little bit. The quantization noise does not decrease indefinitely anymore when the frequency approaches zero, but the total in band quantization noise is reduced.
Let us start with a generic NTF: NTF(z) = (1 − z
−1)2
A(z) where A(z) = az
−2
+ bz−1+ c
If the oversampling ratio is high enough the magnitude |NTF(z)| in the signal band is:
|NTF(z)| ≈ Kω2 where K = 1
|A(1)| (1.11)
If we now shift the zeros, from z = 1 to z = e±jα the magnitude becomes: |NTF(z)| ≈ K(ω − α)(ω + α) = K(ω2− α2)
To compute the in band noise we shall now integrate the square of the above quantity over the signal band and then choose an alpha that minimizes the integral: I(α) = 2 Z ωB 0 K(ω2− α2)2dω = · · · = 2K ω 5 B 2 + α 4 ωB− 2α2ω 3 B 3 dI(α) dα = 2K 4α3ωB− 4α ωB3 3 ( = 0 when α = αopt) 0 = 2KαoptωB 4α2opt−4ω 2 B 3 ⇒ α2 opt− ω2 B 3 = 0 αopt= ωB √ 3 Since the ratio I(0)/I(α
opt) =9/4 we expect an SQNR improvement of about
ap-proximation 1.11 is valid.
Finding the optimum poles is a bit trickier and can be achieved through exhaustive search of the NTF design space. If the figure of merit is the peak SQNR it can be found: Aopt(z) = 1 −1 2z −1 + 4 25z −2
It can be demonstrated that the overall NTF is now flatter in the signal band and supports inputs closer to full-scale without saturating.
1.5
Design and simulation tools
1.5.1
The delta sigma toolbox
The Delta Sigma toolboxo or DSt, written in Matlab, is a collection of functions and scripts thought to ease the design process of a ∆Σ modula-tor. Starting from a small set of necessary specifications it is possible to design an optimal NTF, test a generic modulator that implements it, scale the transfer function to avoid saturactual circuit and finally produce the coefficients needed to implement the circuit of the modulator. Some of the most important functions are listed below [3, p. 399].
synthesizeNTF the synthesizeNTF function is probably the core of the DSt. It takes up to five parameters, here given with their default values: order = 3 the NTF order that will determine the steepness of the
func-tion itself. For a bandpass modulator order must be even, as in bandpass filters.
OSR = 64 the oversampling ratio of the input signal. This parameter is only used when some sort of zeros optimization is performed as explained in section 1.4.6.
opt = 0 flag used to request the zeros optimization. opt = 1 opti-mizes the zeros of the NTF.
H inf = 1.5 the out-of-band maximum gain of the NTF. Stability is guar-anteed if H inf < 2.
f0 = 0 the center frequency of the modulator, f0 = 0 yields a low pass modulator.
The output of synthesizeNTF is a zpk (zeros, poles and gain) object that represents the required noise transfer function and can be used as an input for the subsequent functions.
simulateDSM this function will be heavily used throughout the whole design process. It performs a time domain simulation of the given delta sigma modulator. Its parameters are:
u the input sequence for the modulator. It is an 1 × N row
vector: N simulation steps are performed. The full scale input is defined by nlev.
ntf a zpk representation of the noise transfer function. The sig-nal transfer function is assumed to be unity.
nlev = 2 the quantizer number of levels. The input u must be in
±(nlev − 1).
x0 = 0 the initial state of the modulator.
The output can be written in the form [v, xn, xmax, y]. v is the output sequence, one sample is given per each input sample thus producing another 1 × N row vector. xn, xmax and y contain the internal states of the mod-ulator, the maximum absolute value of each state and the sequence of the inputs to the quantizer, respectively. These numbers can be useful to verify that all the values are within the desired range and that the modulator internals are working properly.
realizeNTF the realizeNTF function is the interface between the zpk representation and a real world representation. Its parameters are listed below:
ntf the zpk object representing the noise transfer function
form = `CRFB` the desired modulator topology. Supported topologies and their differences will be treated in section 2.2.
stf = 1 a zpk object representing the signal transfer function. The STF poles must match the NTF poles to guarantee that the STF can be realized without the addition of extra state variables.
The output can be written as [a, g, b, c]: these coefficients can be used to design the modulator high level schematic as the one given in figure2.11. stuffABCD this function is used to transform the [a, g, b, c] rep-resentation of a modulator into the ABCD reprep-resentation. Since the latter representation does not depend on the topology one of the stuffABCD ar-guments is the form parameter so that the [a, g, b, c] coefficients, that conversely depend on the form, can be correctly interpreted.
mapABCD the mapABCD function instead converts from the ABCD rep-resentation to the [a, g, b, c] one. The last two functions are useful
because dynamic range scaling is easily performed with the ABCD represen-tation, but to realize the modulator we need the [a, g, b, c] coefficients. scaleABCD this function is used to limit the state variables maxima. This is useful because it allows the designer to have some margin since the state variables will be output voltages of operational amplifiers. The max-ima are normalized to nlev. The function output, that of course includes the scaled ABCD matrix, also provides umax that is the maximum stable input.
1.5.2
Cadence Virtuoso
To design and simulate the converter we used the Cadence Virtuoso suite. This choice was tied to the design kit that STMicroelectronics supplied (Process BCD8s), built around uniCAD personalization. The simulator we used is ELDO (Mentor Graphics), as usual when working with ST.
Chapter 2
High level design of the
proposed Sigma Delta
converter
Like in any complex electronic design a certain level of abstraction is neces-sary to properly perform our project. Building such a complicated system directly at transistor level may actually be possible for an experienced de-signer, but there are at least two big challenges that can be dealt with some abstraction:
• The design at transistor level without a block diagram would prove error prone at least
• A ∆Σ ADC inherently needs long transient simulations that shall be done on a system as simple as possible
The need of an high level model of the modulator lead us to a Matlab toolbox: the sigma delta toolbox, by Richard Schreier.
In this chapter we will first discuss the generalities of a data acquisition system, then we will focus on our converter, its specifications and its pe-culiarities. The high level design will be discussed in two separate sections since the modulator and the filter can be designed independently.
2.1
Data acquisition systems
A Data Acquisition System, or DAS, is an electronic system whose aim is to acquire some non electronic data and transform it into a usable, usually digital, format. The first element of a DAS is a sensor, or transducer: it
is the component that turns the to-be-measured physical quantity into an electronic quantity such as voltage, current or capacitance.
The sensor usually needs some sort of biasing, its output should probably be filtered and some feedback to ensure linearity might also be needed: this is achieved through the analog front end (AFE), i.e. some circuitry that directly interfaces with the sensor, powers it properly and usually outputs a voltage that is a function of the measured quantity. In this section we will purposely confuse the sensor with the analog front end, calling the whole system “sensor” and assuming all sensors can be modeled as an ideal voltage source.
The sensor output usually needs some initial amplification. A thermo-couple typical output is in the tents of microvolt range: a certainly too low voltage to be directly fed to an analog to digital converter. Amplification is achieved through an instrumentation amplifier, or IN-AMP. After the instrumentation amplifier the signal is finally digitized.
The signal generally needs some filtering: this can be done in any stage throughout the described path, a filter is usually included in the analog front end to avoid feeding the IN-AMP with too much out of band noise, while a steeper filter is finally implemented in the digital domain.
In figure 2.1 a block diagram for a generic DAS is given.
A ADC LP
vin vc
Figure 2.1: A data acquisition system
One of the main problems of a data acquisition system lies in the low frequency noise: many sensors have a low pass characteristic and a lot of power can be usually found at very low frequencies. At such low frequen-cies thermal noise can usually be neglected, while flicker noise and offset dominate the noise power spectral density. There are many techniques to remove low frequency noise, both static and dynamic.
Static techniques mainly rely on some sort of chip post processing, such as laser trimming of critical components, or external precision components, as the offset resistors that can be connected to a µA741 operational am-plifier. Static remedies are unfortunately not much effective nor cheap: individual trimming must happen for each amplifier even on a multi op amp chip. Finally, consider that trimming is only effective against offset but leaves flicker noise unaltered.
The aforementioned motivations lead to the development of dynamic techniques: the dynamic approach can be much more effective and cheaper
than its static counterpart so it has gained much popularity in the amplifier design.
The three most used dynamic techniques are: • Auto Zero
• Correlated Double Sampling • Chopping Modulation
Auto Zero The idea is simple: if it is possible to measure the amplifier offset we can then subtract it from the output data during a normal ac-quire phase. The amplifier inputs are shorted to set its input to 0 V, then the output voltage is memorized and used to effectively calibrate the instru-ment. The measured value will be subtracted from the subsequent readings, effectively removing the offset effect.
In an Auto Zero automated system this calibration is performed at a few kHz so this technique belongs to the dynamic low noise cancellation family. It is important to note that during the auto zero phase the amplifier output corresponds to the output referred offset and must not therefore be considered valid. This said, a system that exploits the auto zero technique may seem a discrete time system, but since the auto zero phase is usually quite faster than the normal acquire phase the instrument can be treated as continuous time for all practical purposes.
Correlated Double Sampling Correlated Double sampling technique
may appear quite similar to auto zero, but there is a big difference: the signal is sampled as well as the offset. The CDS process consists of two phases: during the first phase the signal is removed from the input and the offset is sampled, while during the second phase the input, together with the offset, is sampled. The output sample is then calculated as the difference between the second and the first sample.
This system is then a sampled data system, there is a precise phase when the output is valid, while when using the Auto Zero system technique we can consider the apparatus a continuous time system.
Chopper Modulation Chopper Modulation can be used to virtually re-move all offset from an amplifier. The signal is modulated at a somewhat high frequency, amplified and then demodulated back to baseband. The trick lies in the fact that offset is not modulated and demodulated, but it gets only demodulated thus ending well away from the signal band. It is
then possible to filter it out in a subsequent stage. The big disadvantage of chopper modulation is the need of two analog multipliers and a readily available sinusoidal signal to properly modulate the input.
Luckily enough this problem is non existent in fully differential systems. In a fully differential amplifier it is very easy to multiply the signal by −1: you just need to swap the relative connections. Since modulating is possible with a square wave we can then substitute the multipliers with an easy to implement matrix of switches, realized with pass gates, that inverts the signal, being controlled by a digital clock.
Offset and low frequency noise afflict also the performances of low-pass sigma delta ADCs, so that a cancellation strategy should be adopted when high accuracy is required.
The choice for our system seems now obliged: we opted for a chopper modulation solution since we are dealing with a fully differential discrete time system. There are some different ways to implement chopping in a Data Acquisition System, some examples are given below.
In figure 2.2 the instrumentation amplifier only is chopped. This tech-nique is quite valid and widely used, the offset contribution to the output noise is drastically reduced as well as flicker noise. The ADC is a low pass converter since its input signal is in the baseband, and the final low pass filter must be steep enough to ensure no additional thermal noise is kept in the output. If the chopping frequency is somewhat low there is the risk that some residual flicker noise ends up in the signal band, but since there is no theoretical limit to fc this problem is usually easily solved.
A ADC LP
vin vc
fc fc
Figure 2.2: DAS: chopped inamp
In figure 2.3 the ADC is included in the chopped portion of the circuit, thus it must be a band pass converter. These kind of converters are usually more difficult to implement but if the ADC offset is a concern then chopping it away is a great way to deal with it. It is worth stressing that if the ADC offset is referred to the whole system input it must be divided by the amplifier gain, so it can usually be neglected with respect to the amplifier input referred offset.
A ADC LP
vin vc
fc fc
Figure 2.3: DAS: chopped converter
Finally, in figure 2.4 another somewhat different approach is presented. The output signal is not brought back to baseband but two consecutive samples are subtracted, effectively canceling offset. For the system to work the input chopper should just multiply the analog signal by ±1 and it should wait a whole conversion time before changing the sign. This dramatically reduces the maximum fcthus making this technique quite poor in rejecting flicker noise. This technique is effectively used when the whole system is integrated in a chip together with a microcontroller: the “demodulation” is usually done in software as well as the input swapping, i.e. fc is software controlled too. Letting the designer control the system behavior via software grants a certain degree of flexibility that can be useful sometimes.
A ADC LP +−
T
vin vc
fc
Figure 2.4: DAS: system level “chopping”
The chopping options in a Delta Sigma modulator are even more and will be discussed in section 3.1.3.
2.2
The proposed solution
Our main goal is to build an high resolution, narrow bandwidth “all pur-pose” ∆Σ analog to digital converter. A pass band topology would guaran-tee the maximum flexibility being suitable for band pass signals, commonly used in impedance measurements, and low pass signals. The latter can be achieved including the ∆Σ in the chopped section of the data acquisition system, as shown in figure2.3. All performances being equal though, a band pass modulator requires double the order to achieve the same performances
of its low pass counterpart, just as an nth-order bandpass filter requires 2n singularities. This being our first ∆Σ modulator we decided to stick to the low pass topology. The other specifications depend on the input signal nature and on the employed technology.
Our converter will be used to digitize the output signal from a thermal flow meter. The transducer that will be used is extensively presented in[4][5] so we will only give a brief description of its operation.
The to-be-measured fluid is guided through a narrow duct and is heated through a couple of resistors. A couple of thermocouples measure the fluid temperature, upstream and downstream. The difference between this tem-peratures is a function of the fluid speed: the slower the fluid the narrower the difference. Since the section of the duct is known it is possible figure out the volumetric flow rate. These sensors can be coupled with slow sam-pling systems because of the measured quantity: flow rates typically feature a narrow bandwidth. The sampling system bandwidth is important only if the input flow is steady for a long period, then settles to a new value through a quick step: the (measured) settling time could be distorted by a slow measuring system. It was experimentally proven[6] that the time constants associated with a flow meter are around 10 ms so our system will feature a 100 Hz bandwidth.
What these sensors seem to lack in speed they compensate in dynamic range: it is usually higher than 80 dB, or more than 13 bits. To add some margin to our design, and since the dynamic range is usually quite higher than 80 dB our target resolution will then be 16 bits.
To keep our project as simple as possible we decided employ to a single bit quantizer. Multi bit designs have been briefly presented in section 1.4.3 and at first glance may seem quite attractive. Designing a two or a three bits quantizer is not much more difficult than a single bit version, but a big problem rises when going to the silicon. As explained, linearity is funda-mental for the modulator’s functioning, and while a single bit quantizer is inherently linear for a multi bit converter some action must be taken to en-sure it, as laser trimming or external precision components. This reasoning finally lead us to the previously stated decision of employing a single bit quantizer.
Following our “simpler is better” policy one can think we opted for a first order modulator, but that is not the case. A first order modulator surely is the more straightforward solution but all the problems associated with higher order modulators usually rise from the third order on. In this case the benefits outdid the disadvantages, especially the possibility to use a much slower sampling frequency while keeping the projected SNR high
enough, so we choose a second order modulator.
The technological process that we will be using is a the BCD8 from STMicroelectronics, but in order to guarantee maximum compatibility only the CMOS subset will be used. The transistors supplied by the foundry are rated for 1.8 V so our analog supply voltage will be 1.8 V, single ended. The chosen mosfets are actually meant for logic designs, the design kit in fact includes many different 5 V devices specifically meant for full custom analog design. We decided to use the low voltage devices for their better noise performances and to facilitate operation at low supply voltages.
The above specifications are summarized in table 2.1. Signal band 100 Hz
Resolution 16 bits
Order II
Quantizer 1 bit
Power source 1.8 V
Table 2.1: Our modulator specification
2.3
Modulator design and testing
In this section we will describe the design procedure we followed while de-signing the modulator. This whole stage of the design was carried out in Matlab exploiting the delsig toolbox functions. We closely followed the pro-cedure described in [3, chap. 8] since our goal was quite similar to the one set by the author.
The first parameter to be chosen is the Oversampling Ratio, or OSR. Figure 2.5 was taken from [3, p. 112]. It shows the empirical relationship between the signal to quantization noise ratio, SQNR, and the oversampling ratio, for various modulator orders N . While the order is a specification we already set the SQNR must be calculated. This is possible because the bit number, 16, is specified. Since 16 bits correspond to about 100 dB, OSR = 256 was chosen in order to add a little margin to our design: the SQNR limit is thus 110 dB, or about 18 bits. Our sampling frequency will then be:
fs= OSR · 2BS = 256 · 2 · 100 Hz = 51.2 kHz
The OSR and the order are enough to calculate the poles and the zeros of the NTF, which is done through the synthesizeNTF function:
Figure 2.5: Empirical SQNR limit for 1 bit modulators of order N
Listing 2.1: Synthesizing the noise transfer function o r d e r = 2 ;
OSR = 2 5 6 ; o p t = 1 ;
H = s y n t h e s i z e N T F ( o r d e r , OSR, o p t ) ;
The opt parameter deserves a little digression. When designing a NTF for a low pass ∆Σ modulator one can argue that all the zeros should be located in DC while the poles location depends on the admissible out of band gain. For a second order modulator this is not true: shifting the zeros away from f = 0 leads to a finite DC gain for the noise transfer function, but the total in band noise is reduced. Setting opt = 1; we are telling the synthesizeNTF function to apply such an optimization in order to achieve an higher peak SQNR as shown in section1.4.6. The output value is stored in H as a zpk object:
Listing 2.2: The NTF zpk object >> H
H =
( z ˆ2 − 2 z + 1 )
−−−−−−−−−−−−−−−−−−−−−−− ( z ˆ2 − 1 . 2 2 5 z + 0 . 4 4 1 5 )
and can be easily plotted to verify that it complies with our expectations. Figure 2.6 shows the ideal synthesized NTF. The frequency is normalized to fs, meaning that BS = 100 Hz corresponds toBS/fs =1/2 · OSR≈ 2 · 10−3.
0.0005 0.001 0.01 0.1 0.5 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 normalized frequency amplitude (dB)
Figure 2.6: Noise transfer function
Listing 2.3: Calculating the SQNR >> sigma H = dbv ( rmsGain (H, 0 , 0 . 5 /OSR) )
sigma H = −73.5672
>> sigma Q = sigma H + dbp ( 1 / 3 ) − dbp (OSR) sigma Q =
−102.4208
Now that an NTF is in hand, we can use the toolbox to perform time and frequency domain simulations. The first thing we’re interested in evalu-ating is the SQNR: there is an handy function called rmsGain(H, f1, f2) that computes the rms gain of the given zpk object in the [f1, f2] band. To compute the SQNR we will need to know also the quantization noise power, that in an oversampled converter is SnOV R = ∆
2
12OSR as shown in
equation (1.3). As outlined in section 1.5.1 in the delta sigma toolbox all signals are assumed to be bipolar, i.e. in a single bit converter the input range is [−1, 1] thus giving ∆ = 2. It easily follows SnOV R = 1/3OSR. The Matlab code used to calculate the total SQNR is given in listing 2.3.
The dbv and dpb functions convert a voltage signal and a power signal into dB, respectively. The resulting SQNR σ2
q ≈ −102 dB corresponds to 17 bits, leaving us with a somewhat small margin. Given the prototype nature
Listing 2.4: Testing the modulator nLev = 2 ; N f f t = 2 ˆ 1 5 ; t = [ 0 : N f f t − 1 ] ; t o n e b i n = 3 0 ; u = 0 . 5∗ ( nLev −1)∗s i n( 2∗p i∗ t o n e b i n / N f f t ∗ t ) ; v = simulateDSM ( u , H, nLev ) ; s p e c = f f t( t r a n s p ( v ) .∗ hann ( N f f t ) ) / ( N f f t ∗( nLev −1)/4); s n r = c a l c u l a t e S N R ( s p e c ( 1 :c e i l( N f f t / ( 2∗OSR))+1) , t o n e b i n ) ; NBW = 1 . 5 / N f f t ;
Sqq = 4 ∗ ( evalTF (H, exp( 2 i∗p i∗ f ) ) / ( nLev − 1 ) ) . ˆ 2 / 3 ;
of this design we decided it to be satisfactory.
We can now perform a time domain simulation to confirm that the mod-ulator is working as expected: we will use a −3 dBFS pure tone. The code is provided in listing2.4. In the first part we define some parameters: nLev represents the quantizer number of levels, while Nfft holds the number of points we will be using to compute the Fast Fourier Transform, or FFT, of the modulator’s output. The number of FFT points equals the number of clock cycles that will be simulated, at our sampling frequency that corre-sponds to 640 ms. The tone bin parameter holds the normalized frequency at which we will stimulate our modulator. The actual frequency will be f = fs
Nffttone bin ≈ 47 Hz, well in our signal band. The test vector u is then generated and finally simulateDSM is called. This function takes the NTF and the input sequence and generates the output bitstream.
In figure 2.7 the output of the time domain simulation is depicted. Our modulator seems to be working since, when the input sine wave is near its maximum, i.e. −3 dBFS, the bitstream is “more time” high than low, while when the input is near zero the bitstream approximately exhibits a 50% duty cycle.
In the last part of listing 2.4 some more quantitative results are pro-duced. The spectrum of the output signal is computed and saved in spec, then the SNR is evaluated through to the calculateSNR function. It’s worth stressing that we are using Hann windowing as discussed in section2.5. Sqq and NBW will be used to plot a correctly scaled ideal NTF, together with the simulated spectrum. That plot can be seen in figure 2.8. A red line has been added to approximately mark the signal band limit. Two data cursors were also added: one at the peak of the input tone and one at the limit of the signal band. Both the cursors refer to the simulated NTF, i.e. the blue line.
0 50 100 150 200 250 300 350 400 450 500 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 time n o rm a liz e d i n p u t bitstream input
Figure 2.7: Time domain simulation
the normalized frequency, its denormalized value is f0 = fs · x ≈ 47 Hz, that is precisely the result we calculated before. The amplitude though, being only −6 dBFS, might surprise a little. Since our input sine wave is a −3 dBFS, that is what we would expect. The result obtained is right though, and comes from the fact that Matlab computes the bilateral FFT: only half of the power is present for positive frequencies.
The other point was highlighted to show that the highest noise level obtained by this particular simulation is about −110 dBFS, that roughly translates to 18 bits, giving us some margin.
Finally the calculated snr is about 95 dB. This result seem fair enough since it corresponds to 16 bits. The calculateSNR function takes the in band portion of the evaluated spectrum and the bin where the signal tone is located and then evaluates the SNR.
The plot depicted in figure 2.8 may appear quite noisy and somewhat rough, especially for the out of band portion of the NTF. That is because the quantization noise is a random process and its FFT can not be as smooth as what we get plotting the NTF.
To overcome this problem one could run multiple simulations adding some variability to the input signal such as different phase or a little
dither-ing on the amplitude, then averagdither-ing the power of all the spectra obtained. Since we were already satisfied with the shown results we decided not to perform such a test, that is very time consuming.
104 103 102 101 180 160 140 120 100 80 60 40 20 0 X: 0.0009155 Y: 6.021 X: 0.001923 Y: 110.9 normalized frequency a m p lit u d e simulated NTF ideal NTF
Figure 2.8: Frequency domain simulation
There is another important simulation that we finally performed, to-gether with the CIC (cascaded integrator comb) filter that will be described in the next section. We wanted to plot the input output characteristic of the modulator to verify its correct functioning. We fed it a varying input: a ramp from −1 to 1 that lasted 223 samples, almost three minutes of real time. The resulting graph is shown in figure 2.9.
As we can qualitatively see the characteristic seems to be ideal. We calculated the average error as:
= v u u t 1 216 216−1 X n=0 e2 n where en, n − vout(n)
0 1 2 3 4 5 6 x 104 0 1 2 3 4 5 6 x 104 input (LSB) output (LSB)
Figure 2.9: Input output characteristic
stressing that this error was calculated including the dynamic extremes, we will briefly see that the modulator is not properly working there, as expected.
In figure 2.10 a particular of the input output characteristic is shown. Some weird oscillations are clearly visible: these are due to limit cycles as was shown in section1.4.4. The graphs shown ranges from 0 to 2048: we have seen that after that code linearity is pretty much reestablished. Since a symmetric phenomena can be observed on the top part of the dynamic the total “bad” codes are 4096. If we calculate again the error, excluding the bad codes, we get:
= v u u t 1 216 216−1−2048 X n=2048 e2 n ≈ 5.7
0 500 1000 1500 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 input (LSB) output (LSB)
Figure 2.10: Input output characteristic: low side particular
or about 2.5 bits.
After throughly testing the NTF we can start to translate it to an actual circuit choosing an appropriate topology. The delta sigma toolbox supports feedback and feedforward structures, both can be built using delaying inte-grators only or alternating delaying inteinte-grators and non-delaying inteinte-grators (resonators).
The four resulting structures are called CIFB, CIFF, CRFB and CRFF, where CI and CR stand for “Cascade of Integrators/Resonators” while FB and FF stand for “Feedback or Feed Forward”. We chose the CIFB structure because it is the more straightforward structure to be implemented and we did not have any other particular requirement beside simplicity.
shortly see why not all the coefficients are needed. Listing 2.5: Realizing the NTF form = ’ CIFB ’ ;
[ a , g , b , c ] = r e a l i z e N T F (H, form ) ; b ( 2 :end) = 0 ;
ABCD = stuffABCD ( a , g , b , c , form ) ; xLim = 0 . 9 ;
[ ABCDs umax ] = scaleABCD (ABCD, nLev , f 0 , xLim ) ; [ a g b c ] = mapABCD(ABCDs, form ) ;
b ( 2 :end) = 0 ;
The delta sigma toolbox provides a convenient function to calculate the coefficients shown in figure 2.11: realizeNTF. Its usage is shown in listing 2.5. The [a, g, b, c] vector contains the unscaled coefficients for the given topology, i.e. the internal states of the modulator occupy an unspecified range. In a real life modulator such a situation is unacceptable: real amplifiers have a limited output range that should be carefully taken in account when designing the circuit.
The next step is the dynamic range scaling: the coefficients are first translated in the ABCD representation, then the scaleABCD function is used to scale the matrix so that no state variable absolute value will ever be more than xLim. The resulting scaled matrix is translated back into the CIFB coefficients, then b2 and b3 are set to zero. It can be shown that the latter operation leads to a maximally flat, all poles STF.
For the xLim parameter we chose 0.9. In the Matlab environment this guarantees the state variables to be included in 0.9 · [−1, 1] = [−0.9, 0.9]. In our real circuit the state variables will correspond to the outputs of the integrators, being limited at least by the supply voltage. In a single sup-ply fully differential system the maximum signal dynamic is [−Vdd, Vdd], where Vdd = 1.8 V for us. Our scaled state variables will then be in [−1.62 V, 1.62 V]. This is a somewhat tight requirement for our operational amplifiers and we will need to verify that our circuits are capable of out-putting such signals.
The resulting coefficients are given in the following listing: Listing 2.6: Scaled coefficients
a = [ 0 . 1 8 7 9 0 . 1 1 5 6 ]
b = [ 0 . 1 8 7 9 0 . 0 0 0 0 0 . 0 0 0 0 ] c = [ 0 . 1 7 1 8 6 . 7 0 3 3 ]
g = [ 0 . 0 0 0 3 ]
Looking at the scaled coefficients we can see that there are some simplifica-tions that can be made.
First of all, a1 = b1. This condition will prove very useful when design-ing the actual circuit since both coefficients scale the inputs of the same integrator. As we will se in section 3.1.1 this equality will let us save two capacitors and some pass gates.
It is clear that g1 can be neglected, being three orders of magnitude smaller than the other coefficients.
We can finally set c2 = 1 because we are using a two level quantizer in a fully differential system: we only care about the second integrator’s output’s sign, and scaling the number do not change that.
b1 +− 1 z−1 c1 +− 1 z−1 c2 Q a1 a2 DAC u(n) v(n)
Figure 2.11: Our reduced CIFB structure
Now that a scaled set of coefficients has been determined, the last step is to translate these informations in components values ready to be used in an electrical design. This transform depends on the integrators topology, a matter that will be discussed deeply in section 3.1.1.
2.4
Filter design and testing
As discussed in section 1.4.2 a single stage filtering will be designed. The filter will be a sincK filter implemented as a CIC, Cascaded Integrator-Comb: we have chosen this topology because it can easily and economically be implemented. Before discussing the design process we will explain why we opted for a single stage filtering, while the literature we examined suggested a dual stage solution.
The main issue with a CIC filter is that the response in the signal band is all but flat, especially for higher order filters. For low frequencies the CIC magnitude response is quite similar to a sincK and, depending on the location of the first null, the in band droop can be not negligible at all. A dedicated filter would perform much better, but designing one working at the relatively high bitstream sampling rate can prove quite difficult and is surely more expensive than a CIC: that is why a CIC is generally used to downsample the bitstream, then another filter is implemented in order to
