SCUOLA DI INGEGNERIA
CORSO DI LAUREA IN INGEGNERIA ELETTRONICA
Anno Accademico 2016-2017
Elaborato finale
LOW-POWER AND COMPACT CMOS DESIGN OF A VOLTAGE REFERENCE CIRCUIT WITH THERMAL COMPENSATION
FOR DIGITAL PIXEL SENSORS FOR X-RAY IMAGERS IN 65 NM TECHNOLOGY
Candidato: Stefania Molfetta Relatori:
Prof. Paolo Bruschi Roger Figueras i Bagué
The purpose of this work is to design a full custom volt-age reference circuit. This circuit will be used in a more complex circuit that consists in a pixellated detector, used for X-ray imager.
A previous version of the same circuit in 0.18 µm is improved, in order to complete it in a 65 nm technol-ogy. Starting from the old version, some modifications are done with the aim to achieve precise specifications, imposed by the whole project.
The work includes an introductory survey on these types of circuit, a comparison between recent topolo-gies and the design of the proposed circuit, illustrating the principle of operation, and the transistor-level and layout-level descriptions.
The final result is a compact cell (14 µm x 12 µm) which has been fully validated by means of DRC, LVS checks and post-layout simulations.
1 Introduction 1 1.1 Motivations . . . 2 1.1.1 X-Ray System main Highlights 3 1.2 Figures of Merit . . . 8 1.3 State-of-the-art of Voltage Reference
Cir-cuit . . . 10 1.3.1 Bandgap reference circuit . . . 10 1.3.2 Limits of the BJT-based bandgap
and alternative solutions . . . . 21 1.4 Objectives and Scope . . . 23
2 Circuit Design 29
2.1 Initial Circuit . . . 29 2.1.1 Principle of Operation . . . 30 2.2 CMOS Technology . . . 39
2.2.1 MOS and Technology
Parame-ters Extraction . . . 41 2.3 Implementation . . . 48
3.1 Simulations Setup . . . 53 3.1.1 DC Simulation . . . 53 3.1.2 AC Simulation . . . 55 3.1.3 Transient Simulation . . . 55 3.1.4 Montecarlo Simulation . . . 55 3.1.5 Corners Simulation . . . 56 3.2 Results . . . 57 3.2.1 Sensitivity . . . 57
3.2.2 Power Supply Rejection Ratio . 62 3.2.3 Start-up Time . . . 63
3.2.4 Mismatch analysis . . . 65
3.2.5 Technology corners analysis . . 68
3.3 Summary of Results . . . 69
4 Layout Implementation 73 5 Post-Layout Simulation Results 79 5.1 Results post-layout . . . 80
5.1.1 Sensitivity . . . 80
5.1.2 Power Supply Rejection Ratio . 84 5.1.3 Start-up Time . . . 85
5.1.4 Mismatch analysis . . . 86
5.1.5 Technology corners analysis . . 88
5.2 Summary of Results post-layout . . . . 89
6.1 Comparation with the state-of-the-art . . 92 6.2 Next steps . . . 93
AD analog-to-digital
ADC analog-to-digital converter AFE analog front-end
BJT bipolar junction transistors
CMOS complementary metal-oxide-semiconductor CSIC Consejo Superior de Investigaciones Científicas CTAT complementary to absolute temperature
DA digital-to-analog
DFM design for manufacturing DPS digital pixel sensor
DRC design rule check DUT device under test
EKV Enz, Krummenacher, Vittoz FOM figures of merit
FPN fixed pattern noise
ICAS Integrated Circuit and Systems
IMB-CNM Institut de Microelectrònica de Barcelona
- Centre Nacional de Microelectrònica
LVS layout versus schematic
MOS metal-oxide-semiconductor NTC negative thermal coefficient PDM pulse density modulation PSRR power supply rejection ratio PVT process-voltage-temperature
PTAT proportional-to-absolute-temperature ROI region of interest
ROIC read-out integrated circuit
Introduction
Generally, integrated circuits and specially analog ones, use voltage references and biasing currents for their proper polarization in order to perform as required.
A voltage reference generator is an electronic device that ideally produces a fixed (constant) voltage irrespec-tive of the loading on the device, power supply varia-tions, temperature changes, and the passage of time.
In most of the applications, these reference voltages and biasing currents are preferably generated inside the same integrated circuit due to the intrinsic advantages regarding the signal integrity despite the extra circuit area and power consumption required.
Some of the most remarkable applications of refer-ence circuits are in analog-to-digital (AD) and digital-to-analog (DA) converters,and in analog front-end (AFE) circuits for sensors and detectors. Depending on the context in which the reference circuit is used, design
specifications are defined, either giving priority to power consumption, area, speed, noise, power supply rejec-tion ratio (PSRR) or robustness against process-voltage-temperature (PVT) deviations [1].
The main purpose of this work is to cover the full de-sign flow in order to obtain a compact all-metal-oxide-semiconductor (MOS) full-custom voltage reference and current biasing generator circuit.
This chapter introduces the motivations of this work, the state-of-the-art of reference circuits, and the main objectives.
1.1 Motivations
In this case, the designed reference circuit is conceived for its use in a more complex circuit: an X-Ray imager, which is a sensor composed of an array of pixels (that are basic picture elements), in charge of converting in-formation into image data.
Although it is not the aim of this work, and in order to understand the reasons under the circuit specifications, next subsection describes the X-Ray system which the proposed circuit is conceived for.
1.1.1 X-Ray System main Highlights
X-Ray imagers are currently dominated by hybrid sys-tems, which present advantages in terms of radiation dose reduction (efficiency is extraordinarily increased), signal integrity improvement and spatial resolution scal-ing when compared to their classical counterparts.
The latter are usually based on indirect detection of radiation by means of a scintillator, in charge of con-verting X-Ray radiation into visible light that will be processed by photodiodes.
On the other hand, hybrid systems are based on hy-bridization, using bump-bonding and flip-chip packag-ing techniques, of a direct conversion detector with the read-out integrated circuit (ROIC) as shown in Fig. 1.1, where bumps connect pixel-by-pixel the readout circuitry with its corresponding X-Ray detector.
One remarkable advantage of hybrid systems (apart from allowing a sensitive area of almost 100% filling factor) is that it allows the use of different detectors with a given ROIC and vice versa. However, of course, these systems present higher costs and usually lower yields.
Regarding the direct conversion detector, it consists on a high resistivity crystalline semiconductor pixellated in an array of p-n junctions usually reverse biased at a high voltage (to create a depletion region covering all
Detector layer
Bump bonds
Single pixel cell
Electronics chip ASIC
Figure 1.1: X-Ray sensor consisting on the bump-bonding hy-bridization of a direct conversion detector with its readout circuitry.
the detector thickness).
These materials take benefits of the small amount of energy needed to create electron-hole pairs while still keeping this threshold high enough to avoid thermally generated charge carriers. Furthermore, the carriers life-time is orders of magnitude higher than in amorphous or polycristalline structures, allowing higher thickness and/or lower biasing voltages.
Their main drawback is that large area crystalline struc-tures that are difficult to obtain. Additionally, the re-verse current, called dark current, increases with tem-perature.
Their principle of operation consists in directly con-verting the incoming X-Ray photons into an amount of charge proportional to the photon energy. Since the
p-n jup-nctiop-ns are reverse biased, the gep-nerated charge is collected/sent to each ROIC pixel counterpart through the bonding bump in order to be processed and generate image data.
Concerning the pixel circuit, it collects the charge generated in the direct detector and usually integrates it to convert it into a voltage that can be treated in differ-ent ways to obtain information, frequdiffer-ently in the digital domain.
Two main processing strategies can be distinguished: charge-integration and photon-counting methods.
Photon-counting pixels are based on the compari-son of the charge generated by each X-Ray photon with a (usually programmable) threshold. Thus, the back-ground noise (and the dark current) is eliminated, and information on the photon energy could be extracted.
However, information can be lost basically due to charge-sharing and pile-up effects. The former occurs when the charge cloud generated by a single photon is shared among different pixels and in none of them the threshold is reached. The latter occurs when different X-Ray photons reach the detector so close in time that the circuitry can not distinguish them, generating erro-neous information.
re-stricting the spatial resolution. Pile-up increases at high photon fluxes, thus requiring more time for the same amount of radiation, which can be a drawback in appli-cations where the imaged sample can be moved.
On the other hand, Charge-integrating pixels inte-grate all the incoming charge including the dark cur-rent, and can not distinguish the energy of each photon. However, it is robust against charge-sharing and pile-up effects.
Fig. 1.2 shows an example of a ROIC pixel archi-tecture based on the charge-integrating readout method. It is mainly built using different circuit blocks includ-ing a programmable AFE and an analog-to-digital con-verter (ADC). In this case, it works integrating the input charge and digitizing this information using a pulse den-sity modulation (PDM) approach. Additionally in this case arbitrary test patterns can be supplied as input.
Here, but also in different architectures (even ones used in photon-counting pixels), analog circuit blocks require voltage references and biasing currents for its proper operation.
In order to reduce crosstalk between neighboring pix-els, which affects resolution and consequently image quality, it is preferred to locally generate (at pixel level) both biasing currents and voltage references needed for
Figure 1.2: Pixel Architecture used in [3]. Thanks to the lo-cal bias generation, communications between pixels are re-duced to the digital domain. Pixels are daisy chain serialized in columns and the whole pixels array is to be bump-bonded to an array of detectors (represented as reversed diodes) in charge to convert X-Ray photons into charge.
the polarization of the pixel circuit blocks, over using global (at array level) analog signals. Besides, inter-connectivity between pixels is reduced and technology requirements at layout level are relaxed.
On the other hand, however, the complexity (and area) and power consumption of pixel circuitry tends to in-crease.
Since the imager spatial resolution is directly related to the pixel dimensions, one of the main targets of this voltage reference circuit is to reduce its area to have the
smallest possible pixel.
Other important specifications are discussed in the following section.
1.2 Figures of Merit
The main metrics to be considered regarding reference voltage and biasing current generator circuits are sum-marized as follows:
• Circuit dimensions: although it is not a key parame-ter for the circuit performance, a reduced area helps obtaining a small pixel in order to increase spatial resolution.
• Power consumption: due to the fact that the detec-tor performance degrades at high temperatures (the diode inverse current, called dark current, increases with temperature), power consumption must be kept low.
• PSRR: in order to decouple the reference voltage from the power supply noise, a high rejection ratio is required.
• Robustness against PVT deviations:
– Thermal Coefficient: it is desirable to obtain an
in order to maintain the pixel performances over a large temperature range. Therefore, low tem-perature sensitivity is imperative.
– Minimum supply voltage: the obtained
refer-ence voltage must be decoupled from fluctua-tions of the supply voltage and also be able to operate at supply voltages lower than the nomi-nal one to enable the possibility of saving power consumption minimizing supply levels if needed.
– Mismatch and corner deviations: since the
volt-age reference generation is done at pixel level, and the imager is composed of an array formed by a large number of pixels, divergence between reference voltages in different pixels must be small in order to reduce the so called fixed pat-tern noise (FPN) in a flat image due to mis-match, process and corner deviations.
• Speed: in the case of this application, pixels should incorporate the possibility to be disabled in case of malfunction to avoid image distortion and unuseful power consumption, or to be able to define a region of interest (ROI). Therefore, a low "start-up" time needed to turn on the circuit is desired.
1.3 State-of-the-art of Voltage Reference Circuit
A voltage reference circuit can be obtained in different ways, that can be distinguished in two main groups [2]:
• with Zener diode
• Bandgap
The first ones are not recommended because they in-troduce process problems, higher dependence on tem-perature, high supply voltage and noise.
Noise problems could be solved using big capacitors, which however are not integrable.
The Bandgap reference circuits are composed by tran-sistors, therefore comply with stringent matching rules and they can be integrated.
1.3.1 Bandgap reference circuit PRINCIPLE OF OPERATION
The principle of operation of a bandgap circuit is showed in Fig.1.3.
The output voltage obtained is
Vout = b1V1 +b2V2 (1.1) If V1is a proportional-to-absolute-temperature (PTAT) voltage and V2 a complementary to absolute
tempera-Vout
b2
V2
b1
V1
Figure 1.3: Principle of operation of a bandgap circuit.
ture (CTAT) voltage, the sum of these two voltage gives a quantity independent on temperature.
The derivative of Vout has to be zero if V2 increases with temperature while V1 decreases.
A temperature independent voltage reference circuit is useful because if a circuit is temperature independent, therefore it is usually process independent as well [1].
A simple BJT bandgap circuit is showed in Fig.1.4. The diode-connected transistor is fed by the current gen-erator and has a VBE about 0.6− 0.7 V.
VBE is the PTAT voltage and decreases in
tempera-ture, because of the strong influence of exponential be-haviour of IC(T) IS(T): VBE(T) = kT q ln IC(T) IS(T) (1.2) By adding the VT = kTq (the CTAT voltage) that
ob-Ic Vcc VBE Vout b VT
Figure 1.4: Principle of operation of a bandgap circuit.
tained.
The result is that:
dVout dT = dVBE dT +b k q (1.3)
With kq = 8.61 ∗ 10−5 V/K, b has to be opportunely
chosen.
It is possible to obtain a perfect compensation only for a precise temperature.
Nevertheless, the dependence on temperature is very low for a wide range.
This principle of operation is used to design a lot of different voltage or current reference circuit.
Q1 Q2 A nA R1 R2 R3 Vout X Y I I
Figure 1.5:Temperature independent voltage reference circuit.
BJT BANDGAP REFERENCE CIRCUIT
In Fig.1.5 is shown an example of a reference circuit with BJT transistors.
It is supposed that the base currents are negligible, transistor Q2 consists ofn unit transistors in parallel and
transistor Q1 is a unit transistor with area A.
The principle of operation explicated in the previous subsection is now achieved in the following way.
Supposing that somehow VX = VY is forced and R1 = R2 then I is equal in both branches. Finally, it
can be written:
with
I = VBE1 −VBE2
R3 =
VTln(n)
R3 (1.5)
and consideringVBE1−VBE2 = VTln(nII 0
S1) −VTln(
I0 IS2),
with IS1 = IS2 therefore VBE1 −VBE2 = VTln(n).
In conclusion, it is possible to calculate Vout and dVout
dT : Vout = VBE2 + VTln(n) R3 (R2 + R3) (1.6) Vout = VBE2 + 1 + R2 R3 VTln(n) (1.7) dVout dT = dVBE dT +b k q (1.8)
It is clear that, choosing the right quantities for n and R2 = R3, b is defined and it is possible to avoid the de-pendence on temperature of Vout, making the derivative
equal to zero.
A drawback of this type of reference circuit, although they have a low output impedence, is that they can achieve a minimumVre f at most about1.5−1.2 V. With this val-ues they cannot be used for low voltage applications.
SUPPLY INDEPENDENT CURRENT CIRCUIT
Before showing another example of bandgap reference circuit, it is important to introduce supply independent current circuits.
Vdd Vout Iref M1 M2 Iout (a)
Vdd Vout M1 M2 Iout R1 (b)
Figure 1.6:Current mirror-biasing using (a) an ideal source and (b) a resistor
In Fig.1.6 (a) there is a simple current mirror with Ire f generated with an ideal source.
Supposing that Ire f does not vary withVDD and channel-length modulation of M2 is neglected, then Iout is
inde-pendent on VDD.
In Fig.1.6 (b) Ire f is generated through a resistor R1, and in this case Iout changes with VDD as follow:
∆IOUT = ∆VDD
R1 +1/gm1
(W/L)2
(W/L)1 (1.9) With the aim to obtain a lower dependence on the supply, it is thought to put two mirrors, n and p type, cross-coupled with the output of each mirror, driving the input of the other mirror, that can be viewed as a two-mirror feedback loop, as in Fig.1.7 (a).
Each diode-connected MOS feeds from a current source, so it results relatively independent of VDD.
If transistors are in saturation with λ = 0 then Iout =
KIre f seems can support any current levels.
In order to limit the possible high current level, a re-sistor is included in the circuit, as it is possible to see in Fig.1.7 (b).
This is a possible circuit which could be used to im-plement PTAT current generator, useful for bandgaps.
CMOS BANDGAP CIRCUIT
With the aim to obtain a bandgap circuit in CMOS pro-cess, some modifications of the circuit in Fig.1.5 are necessary, as previously anticipated.
In fact, in a n-well process a pnp+ transistor can be obtained, using the substrate p+ in the n-well as emitter and the n −well itself like base. It is necessary for the p-type substrate, that acts like the collector, to be
Vdd W/L K*W/L W/L K*W/L Iref Iout M1 M2 M3 M4 (a)
Vdd W/L W/L W/L K*W/L Iref Iout M1 M2 M3 M4 Rs (b)
Figure 1.7:Simple circuit to establish supply-independent cur-rent.
nected with the most negative voltage of the circuit, i.e. the ground.
Therefore, in a CMOS process, the npn BJTs of the circuit in Fig.1.5 have to be replaced by pnp BTJs with
bases ground-connected. The circuit showed in Fig.1.8 is an example of implementation and works as follow (A is again the BJT area).
Vdd
M3 M1 M4 M2 M5 Q1 Q2 R1 Vr1 IPTAT A nA X Y Q3 R2 VoutFigure 1.8:Temperature independent current and voltage gen-erator.
It is assumed that M1, M2 and M3, M4 are identical
pairs, therefore if ID1 = ID2 the circuit has to ensure VX = VY.
It is expected the same behaviour for ID5 = IPTAT, which should be equal to
ID1 = ID2 =
VTln(n)
R1 (1.10)
But, the mismatching between the transistors and the resistor temperature coefficient, causes a deviation from the ideal equation.
The problem is solved using resistor R2 and the out-put voltage becomes:
Vout = VBE3 +VTln(n)R1
R2 (1.11)
The drawback of this reference circuit is that the min-imumVout possible is about1.5−1.2 V. These levels are too high for low-voltage applications and then it is not possible to use it.
LOW-VOLTAGE CMOS CIRCUIT
The circuit illustrated in Fig1.9 is the solution to the problem of high Vout value of the previous configura-tion.
The core circuit is (again) the PTAT current genera-tor. Although the ∆VBE causes an increasing of PTAT voltage (dropped accross R1), the absolute VBE of Q1 and Q2 is CTAT. VBE1 controls the current through R2 and R3. The result is a temperature independent current if the currents are scaled correctly.
Vdd
M3 M1 M4 M2 M5 Q1 Q2 R1 IPTAT A nA X Y Q3 R4 Vout R2 R3 I1Figure 1.9:Low voltage CMOS bandgap circuit.
I1 = IPTAT + ICTAT (1.12) IPTAT = VTln(n) R1 (1.13) ICTAT = VBE1 R3 (1.14)
Vout = R4I1 = R4 R1 VTln(n) + R4 R3 VBE1 (1.15)
Both last two CMOS bandgap circuits have the "draw-back" of having two different operation point possibles. One is with all currents in three different branches equal to zero. The other with current equal to I1.
It is important to make sure that the circuit operates in the right operation point. Thus, it is necessary a start-up circuit to inject some current if it is at or close to the undesirable operating point.
1.3.2 Limits of the BJT-based bandgap and alternative so-lutions
It is important the presence of bipolar transistors, or at least diodes. In fact in CMOS process technologies, par-asitic BJTs are used to implement a bandgap-like cir-cuit.
In literature, there are several low-power reference circuits compatible with complementary metal-oxide-semiconductor (CMOS) technologies.
In some cases, due to the use of parasitic bipolar junc-tion transistors (BJT), diodes or resistors, some of them are not suitable for modern CMOS processes or require extra technology options for their fabrication as above
said, and increase costs.
Furthermore, even when these components are avail-able, they are relatively large and then not suitable for very compact reference circuits.
This is the case of [4], and [5], in which a voltage reference is designed in a 65 nm technology, achiev-ing good performances (high PSRR and low tempera-ture coefficient for both reference voltage and biasing current) but with complex circuitry and large area, and power consumption relatively high.
Other topologies present resistors [6], multi-threshold process options [7]-[9] or more complex circuits and larger areas as in [10]. Therefore, a promising good so-lution is provided by the all-MOS-based topologies.
In order to show the potential of the technology used in this work, figures of merit in other two more recent different topologies [12] and [13] are summarized in Ta-ble 1.1.
Work Reference [11] [11] [12] [13] Units
CMOS Technology 0.35 0.18 0.065 0.065 µm
Reference Voltage 855 825 468 275 mV
Thermal coefficient <100 100 to 200 45 176 ppm/oC
Supply Voltage 3.3 1.8 1.2 0.6 V
Min. Supply Voltage 1.4 1 1.1 0.4 V
Power Consumption <50 <2 488 62 µW
PSRR (@100 Hz) −58 −45 −56 −36 dB
Silicon area 0.0077 0.0012 N.A. 0.01 mm2
Table 1.1: Performance parameters in different technologies
implemented using two different technologies, while in the third one, a bandgap-like topology is used. There is a clear improvement in the thermal coefficient, PSRR, and silicon area occupied, when comparing0.35 µm and 65 nm technologies.
1.4 Objectives and Scope
This work has two main goals: to review the full design flow / methodology used in analog mixed-signal micro-electronics design, and to use it to design a challenging analog circuit to generate reference voltage and biasing currents.
From transistor-level schematics design and simula-tions to layout design and post-layout verificasimula-tions, the design is made using Cadence Virtuoso EDA tools, a very common and widely used tool in microelectronic design.
In this sense, this work starts with a general introduc-tion to the project context and a review of the Cadence EDA tools software guides used for the development of the analog circuit design. Firstly, simple digital cells are designed as examples to assimilate the use of these tools from the circuit conception to the final physical layout verification including the following steps:
• Schematics entry.
• Symbol cell generation.
• Development of setup environment for different cir-cuit simulations.
• Definition, execution, display and analysis of simu-lation results.
• Layout circuit design.
• Layout verification: design rule check (DRC) in this case using Calibre tools, and layout versus schematic (LVS) analysis using Assura tools.
• Layout parasitics extraction using Assura tools.
• Post-layout simulations generally reusing the test setup already developed.
Due to time constraints, the design for manufacturing (DFM), fabrication and experimental tests fall out of the scope of this work.
This project has been entirely developed at Institut de Microelectrònica de Barcelona - Centre Nacional de Microelectrònica (IMB-CNM), a public research center located near Barcelona and one of the members of the Consejo Superior de Investigaciones Científicas (CSIC), the greatest Spanish scientific public institution. The
staff of IMB-CNM is around 175 people. The research activity of IMB-CNM covers from technology, devices and integrated circuits (in micro and nanoelectronics) to sensors, actuators, micro and nano electromechanical systems, smart systems and so on. Its R&D activities are complemented with training of students, researchers and engineers and also with technology transfer to com-panies.
Within IMB-CNM, this work has been developed in the framework of the Integrated Circuit and Systems (ICAS) group, devoted to analog, digital and RF CMOS design and test of integrated circuits and systems to im-prove and exploit nano/micro-technologies for advanced applications. One of these main applications is X-Ray imagers.
In this case, the group projects in this field take ad-vantage of two fundamental aspects. First, the group knowledge (and availability of the required tools) in ana-log CMOS circuits design for the ROIC development of X-Ray systems explained in Section 1.1.1. Second, the fact that IMB-CNM have its own clean-room where the detector part of the X-Ray Imager (also designed within ICAS group) can be fabricated. In addition, the insti-tute also counts on the possibility of performing most of the packaging steps for these hybrid systems (such as
bump-growing and flip-chip hybridization).
The last version of X-ray Imager and its voltage ref-erence circuit were designed in a 0.18 µm technology [3], [11] . As noticed from Table 1.1 , this approach shows better performances in comparison with the im-plementation in 0.35 µm technology. In order to update the technology node, the presented circuit is designed in a 65 nm technology from Taiwan Semiconductor Manu-facturing Company (TSMC), a challenging technology not previously used in the framework of ICAS group.
This work is organized as follows. Next chapter in-troduces the idea behind the circuit design, its principle of operation and its implementation in the 65nm tech-nology. In addition, a brief introduction to this technol-ogy and some key parameters extraction (for the circuit design) are provided.
Chapter 3 describes, presents and analyzes the simu-lation setup and results, at schematic level, covering all the figures of merit described in Section 1.2 .
Chapter 4 details the layout implementation of the proposed design while Chapter 5 presents the post-layout simulation results and compare them with the schematic level simulation results.
Finally, Chapter 6 includes the conclusions. This work is compared with the state-of-the-art voltage reference
circuits and possible improvements and/or future works are discussed.
Circuit Design
2.1 Initial CircuitThe entire work is based on an alternative circuit design approach for thermally compensated voltage references, exclusively based on single-threshold all-MOS devices [11], shown in figure 2.1.
The circuit has three cascade sections with different aims:
• M1-M2-M3-M4 form a proportional to absolute
tem-perature (PTAT) voltage core.
• M5-M6-M7 generate the specific current Ibias.
• M8-M9 are used to thermally compensate the out-put voltage reference Vre f.
The dashed boxes have different colours to show dif-ferent matching groups.
M8 X M5 M M41 M31 M2 1 M1 P M6 N M7 1 M9 Y Vref MS 1 Ibias Ibias Ibias MIbias XIbias Vbias Vptat
Figure 2.1:Circuit proposal for the reference voltage (Vre f) and
biasing current (Ibias) generation. Dashed boxes show the
matching groups.
2.1.1 Principle of Operation
It is possible to explain the principle of operation start-ing from the transistors couple M1-M2 that operates in weak-inversion saturation (i.e. sub-threshold).
It is supposed that it is possible to neglect the channel length modulation like in the Enz, Krummenacher, Vit-toz (EKV) model [15], therefore the following expres-sions for forward (eq.2.1) and reverse (eq.2.2) currents in this region can be used:
IF = 2nβUt2e VP−VS Ut (2.1) IR = 2nβUt2eVP −VD Ut (2.2) with VP = VG − VT0 n (2.3)
where VP is the pinch-off voltage and VS and VD,
which normally represent drain and source voltage, are considered referred to the bulk, so they become VSB and VDB and in the same way VGB.
It is obtained ID = ISeVGB −VT0 ηUt e− VSB Ut (2.4) with IS = 2nβUt2 (2.5)
where IS is called the specific current, VTO is the
threshold voltage, n is the sub-threshold slope factor, Ut (= KT/q) is the thermal voltage and β (= µCoxW/L)
Due to symmetry of the current mirror (M3-M4), and because M1 has multiplicity P, it is imposed that
ID1 = ID2 (2.6) IS1eVGB1 −VT0 ηUt e− VSB1 Ut = IS2eVGB2 −VT0 ηUt e− VSB2 Ut (2.7) IS1 = PIS2 (2.8)
Replacing in (2.7) with VSB2 = 0, VSB1 = Vptat and
knowing that VGB1 = VGB2:
PIS2e Vptat
Ut = IS2 (2.9)
Hence, Vptat follows a proportional to absolute tem-perature law:
Vptat = Utln P (2.10)
Since Ibias is obtained from the non-linear load at-tached to Vptat, M6 has to be in strong inversion satu-ration, following in this case the EKV model:
ID =
βn
2 (VP −VS)
ID6 =
β
2n(VGB6 −VT0− nVSB6)
2 (2.12)
M7 is also in strong inversion but in triode region, so
it follows the equation:
ID = nβ VP − VS +VD 2 (VD − VS) (2.13) ID7 = β7 h VGB7 −VT0− n 2(VSB7 +VDB7) i (VDB7+VSB7) (2.14) Knowing that M5 has scaling factor M and M6 and M7 have ratio N between them [16]:
ID6 = MIbias = Nβ7 2n (Vbias −VTO − nVptat) 2 ID7 = (M +1)Ibias = β7 Vbias − VTO − n 2Vptat Vptat (2.15) Mathematically solving, it can be proved that the bi-asing current is proportional to the specific current:
Ibias = QIS7 (2.16)
Q = " ln P 2(M +1) r M N + r M N + M +1 !#2 (2.17) Since, from second equation of 2.15,
Vbias −VT0 = IbiasM + 1 UtlnP 1 β7 + n 2UtlnP (2.18) and replacing it in the first equation of 2.15,
s 2nM Nβ7 Ibias = IbiasM +1 UtlnP 1 β7 + n 2UtlnP − nUtlnP (2.19) thus, M +1 UtlnP 1 β7 2 Ibias2 − M+1 β7 n+ 2nM Nβ7 Ibias+ n 2UtlnP 2 = 0 (2.20)
Solving the second order equation:
Ibias = 1 2nβ7(UtlnP) 2 (M+1)N+2M N + r (M+1)N+2M N 2 − (M+1)2 (M+1)2 (2.21)
Ibias = IS7 lnP 2(M +1) 2 (M + 1)N + 2M N + s (M +1)N +2M N 2 − (M +1)2 (2.22)
That can also be written as
Ibias = IS7 lnP 2(M +1) 2 M N + M N + M + 1 + s M N + M N + M + 1 2 − (M + 1)2 (2.23) Defining A = MN and B = MN + M +1, Ibias = IS7 lnP 2(M +1) 2 (A + B) + q (A+ B)2 − (A− B)2 (2.24) or Ibias = IS7 lnP 2(M +1) 2 h A+ B +2 √ AB i = IS7 lnP 2(M + 1) 2h√ A +√Bi2 (2.25)
Ibias = IS7 " ln P 2(M +1) r M N + r M N + M +1 !#2 (2.26) which is eq. 2.16 with Q defined as in eq. 2.17.
As last step, to obtain Vre f, it must be considered that the current through the current mirror with output on M8 has a ratio equal to X, and that M9 (with ratio Y
respect to M7 and acting as an active load) has to operate
in strong inversion saturation, according to eq. (2.11). Therefore:
ID9 =
β9
2n(VGB9 −VT0− nVSB9)
2 (2.27)
In case represented in Fig. 2.1, the work conditions are VSB9 = 0 VGB9 = Vre f (2.28) So, equation 2.27 becomes
ID9 = β9
2n(Vre f −VT0)
2 (2.29)
Vre f = s 2nID9 β9 +VT0 (2.30) knowing that ID9 = XIbias Ibias = QIS7 (2.31) and replacing IS7 = 2nβ7Ut2 (2.32) in ID9 = QXIS7 (2.33) ID9 = 2nQXβ7Ut2 (2.34) Finally, Vre f = s 2n2nQXβ7U 2 t β9 +VT0 (2.35) Vre f = 2n s QXβ7 β9 Ut2 + VT0 (2.36) β9 = Yβ7 (2.37)
Vre f = 2n r
QX
Y Ut + VT0 (2.38) Knowing that VT0, in a MOS, follows a linear
be-haviour with negative thermal coefficient (NTC), in gen-eral: VT0(T) = VT0(T0) − α T T0 −1 (2.39) with α being the thermal coefficient for a particular CMOS technology , T0 and T respectively the reference
and working temperatures.
Combining (2.39) with (2.38): Vre f = 2n r QX Y Ut + α T T0 +VT0(T0) + α (2.40)
in which the first two components depend on the tem-perature.
With the purpose to have Vre f independent of T, it must be imposed the derivative dVdTre f equals zero, there-fore: r QX Y = 1 2n α Ut(T0) (2.41) In this way, Vre f becomes a temperature independent local reference:
Vre f = α+ VT0(T0) (2.42)
It is important to remember that for the design analy-sis, it has been taken into account a good matching be-tween M1 and M2 so, in order to assure eq. (2.8) to be robust, it is important to use P 1.
Also to guarantee that M6, M7 and M9 operate in
strong inversion, it has to be accomplished that QMN 1 and QXY 1.
Furthermore, Ibias can be mirrored in order to obtain biasing currents for analog circuits.
Thanks to the relation given by eq. (2.16), the inver-sion factor (IF = ID
IS) determining the device operating
point, is robust against CMOS process variations.
2.2 CMOS Technology
The technology used for the circuit design is the 65 nm node of TSMC.
The main reason for this to be the target technology is that, as stated in Section 1.1, this design will be used as part of a digital pixel sensor (DPS) for X-Ray Im-agers that will be integrated in this submicron technol-ogy node. Moreover, this design will complete the work started in [11], to prove the technology robustness of the
circuit principle based on the EKV model equations. From the designer point of view, besides, it is a chal-lenging analog design to be carried under such a submi-cron technology node which, in addition, is newly used in the ICAS framework.
Only standard MOS transistors of this technology are used, presenting these main characteristics:
• use of Low-K inter-metal dielectric for thin metals
• support of wire bond or flip chip terminals and laser or electrical fuse
• normal power supply for thin oxide of 1.2 V
• operation temperature range between−40oC to125oC
• possibility to use up to 9 metals (and vias) • Lmin= 0.06 µm and Lmax= 20 µm
• Wmin= 0.12 µm and Wmax= 900 µm
• metal-in-metal capacitors of 1, 1.5 and 2 fF/µm2 • oxide thickness Tox of 2 nm in NMOS and 2.2 nm
in PMOS.
• saturation current of 879.15 µA/µm and 502.8 µA/µm for a 0.12µm/0.06µm NMOS and PMOS devices respectively.
• off current of 11.06 nA/µm and 13.684 nA/µm for a0.3µm/0.06µm NMOS and PMOS devices re-spectively.
• gate leakage current of 121 nA/µm2 and30 nA/µm2
for a a 1µm/1µm NMOS and PMOS devices re-spectively.
In addition, other important parameters are necessary to calculate the theoretical values, obtained from the EKV model, in order to compare the final results of the simulations.
It could not be possible to use the general values given in the documentation, since they are referred to precise dimensions.
These parameters have different meaning with respet EKV model.
For these reasons it is necessary to extract these im-portant parameters by studying a single MOS, in spe-cific conditions and of spespe-cific dimensions, as explained in the following section.
2.2.1 MOS and Technology Parameters Extraction
The problem in submicron technologies is that scaling down the dimensions of the transistors, the threshold voltageVT0and features of device begin to fluctuate
sig-nificantly.
Besides, VT0 becomes small in small channel length
devices and this causes a higher leakage current. This implies hard challenges for the design of precision ana-log circuit like voltage references, especially for low-power and low-voltage applications.
Using a submicron technology, it is clear that second order effect and leakage current should be considered, as said.
Therefore, in order to evaluate the expressions ex-tracted in Section 2.1.1 using the EKV model, a single MOS transistor device circuit is studied to extract useful parameters.
The researched parameters are summarized in Table 2.1.
Parameter Definition α temperature coefficient n sub-threshold slope β transconductance coefficient VT0 threshold voltage IS specific current
Table 2.1: Technology parameters extracted for theoretical evaluation of equations of Section 2.1.1
Fig 2.2 shows circuits studied to obtain the specific current IS and the threshold voltage VT0. Once obtained VT0 and IS, it is possible to extract other parameters.
The same circuits are studied for four different tran-sistors with different sizes (small, long, wide, and large
Vdd
ID
Vs
(a)Vdd
ID
Vs
(b)Figure 2.2: Single-MOS circuits used for technological param-eters extraction. IS extraction circuit (a) and VT0 extraction
circuit (b). Maximum supply voltage is 1.2V.
device), in order to study the scalability of these param-eters.
The simulated devices present the following dimen-sions:
• WL = 0.20.2µm
µm: small device. • WL = 0.22 µm
• WL = 0.22 µm
µm: wide device. • WL = 22µm
µm: large device.
The specific current IS is obtained from a parametric
analysis varying the drain current ID in Fig. 2.2 (a). In order to achieve the correct value of IS, it is nec-essary to study gmsI Ut
D that is the interpolation function between weak and strong inversion.
As defined from [14], it can be approximated to:
gmsUt ID = 1 q 1 4 + ID IS + 1 2 (2.43) Imposing ID
IS = 1, the point where curves of weak and
strong inversion asymptotes intersect, equals to 0.618, is given and IS is obtained from the corresponding ID
value.
It is important to remark that, in higher node tech-nologies IS, calculated with EKV model, has a scaling factor proportional to the device dimensions. Instead, in this case the quantity gIms
D Ut give us different intersection points, i.e. different specific currents for different device dimensions, demonstrating the non-scalability property of the parameters, for the used technology.
Fig 2.3 shows the plot of gmsI Ut
D vs. the drain current ID.
10-12 10-10 10-8 10-6 10-4 I D [A] 10-2 10-1 100 101 g ms U t /I D small device long device large device wide device Figure 2.3: gmsI Ut
D vs. ID curves for four different dimensioned
devices.
On the other hand, to obtain VTO some considerations are necessaries.
In Fig. 2.2(b) it is represented the circuit used to ex-tract it.
As known from [15], it is possible to define ID in dif-ferent operation regions, that are clarified in Table 2.2.
Region ID Weak Inversion ISe VGB−VT0 nUt e −VSB Ut Moderate Inversion ISln2(1+e VGB−VT0−nVSB 2nUt ) Strong Inversion β 2n(VGB−VT0−nVSB) 2
Imposing ID = IS
2 and polarizing the transistor with
VG = VD, the MOS is in moderate inversion and
satu-ration.
Moreover, if VSB = VP = 0, the MOS is still in moderate inversion and saturation. So:
IS 2 = IS ln 2( 1+ eVGB −VT0−nVSB 2nUt ) (2.44)
In this way, it is easy to obtain:
VGB = VT0+ 2nUt ln(e 1 √ 2 −1) (2.45) 0 0.2 0.4 0.6 0.8 1 1.2 V G [V] -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 V S [V] small device long device large device wide device
Figure 2.4: VS vs. VG curves for four different dimensioned
The term 2nUt ln(e
1
√
2 − 1) (around 1.5 mV) can be neglected, and hence VT0 is obtained in the point where
VS = 0.
In the same way of IS, also VT0 have not a unique value. Fig. 2.4 shows VS vs. VG.
The slope of the curve in Fig. 2.4 equals 1n, therefore n can be obtained.
The obtained results are summarized in Table 2.3.
L W 0.2 µm 2 µm 0.2 µm VT0=271.88 mV VT0=302.515 mV IS=462 nA IS=5.44 µA n=1.11 n=1.13 β=3.32e-4 β=3.85e-4 2 µm VT0=220.96 mV VT0=259.29 mV IS=36.57 nA IS=458 nA n=1.08 n=1.1 β=2.7e-4 β=3.33e-4
Table 2.3: Technology parameters in different W/L
It is possible to see that there is a ratio between the extracted specific current values approximately equal to 12, while the ratio should be 10.
It seems reasonable to consider as right values an av-erage of those obtained in the case of WL = 1, for both
IS and VT0.
Finally, the extracted values can be summarized as in Table 2.4.
Regarding α and β parameters, they are automatically extracted by Cadence simulator.
They are simply read in the list of technological pa-rameters: α results the same in each case, while β changes and it is chosen as an average, like in the case of IS and VT0.
Parameter Extracted value Units Definition
α -0.239 mV/oC normalized temperature
coefficient
n 1.1 mV/dec subthreshold slope
β 3.33e-4 transconductance coefficient
VT0 0.265 V threshlod voltage
IS 460 nA specific current
Table 2.4:Technology parameters values extracted from device with W/L = 1.
2.3 Implementation
Based on the circuit described in Section 2.1, the final implementation is derived as described here.
Fig. 2.5 shows the definitive circuit implementation. Extra transistors are added to compensate side effects due to the small dimensions of the technology or to achieve good performance and satisfy the target spec-ifications, which can be listed as follows:
• Area as small as possible.
• PSRR: > |40|dB.
• Power consumption: in the order of µW. • Start-up time: < 1µs.
• Minimum supply voltage: < 0.8V. However, this is not a key requirement for the final application.
• Main parameters mismatch deviations: < 10%. First of all, as stated in Section 2.1.1, to achieve min-imum technology mismatching effects, it is necessary to use a very high P value.
Obviously it is not possible to increase so much this value, which could lead to an excessive growth of oc-cupied area. Therefore, to obtain a good result, M21 is added.
In this way M21 and M22 can be considered as a
sin-gle MOS transistor with dimension 2LW. This allows to use half of transistors needed in parallel, to constitute M11 and to obtain the ratio wanted, between M11 and M21− M22. Thus, with15 M11 transistors, the obtained
ratio P is 30.
The same principle is applied for M91 and M92, where
using only one M91 and one M92 transistors, the ef-fect is the same as using Y = 0.5 and easily achieving q
QX
M81 X M51M M411 M82 X M52M M421 MS1 1 MS21 MS3 1 MS6 1 MS4 1 MS5 1 M31 1 M32 1 M22 1 M23 1 M21 1 M11 P M12 1 M6 N M7 1 M91 Y M92 Y Mdummy 3 Vref MS7 1 MS8 1 Ibias Ibias Ibias MIbias XIbias MI1 1 MI2 1 On On Xon Xon Vptat Vbias
Figure 2.5:Final Schematic Circuit. Dashed Boxes show match-ing groups. Blue box matchmatch-ing applied only in p-MOS de-vices.
Besides, the so-called start-up circuit is added.
It is composed by the transistors in the blue dashed box plus the inverter (MI1-MI2) in Fig. 2.5.
As previously anticipated in section 1.3.1, its aim is to assure that the current mirror, composed by M31 − M32 and M41− M42, turns on not reaching a metastable state, providing a very low current path from the PMOS
gates node to M23 drain node.
Furthermore in order to provide at least a small de-coupling, transistor MS2 configured as a MOS capacitor is also added.
Finally, cascode-stages are incorporated to increase PSRR either at PMOS and NMOS blocks.
Regarding layout completion and helping its symme-try, some extra dummy transistors Mdummy are used.
Transistors final dimensions are obtained after differ-ent parametric simulations, evaluating all the figures of merit (FOM) as presented in Chapter 3.
They are chosen taking into account the circuit spec-ifications.
In Table 2.5, these dimensions are classified in differ-ent colours for each matching group of Fig. 2.5, while Table 2.6 summarizes the used ratios.
Colour Red Blue Pink Green Yellow Units W L 0.2 4 0.2 0.6 1 0.5 0.2 4 2 1 µm µm
Table 2.5:Fig. 2.5 transistors dimensions distributed according to the matching group colours
P M N X Y
30 4 1 6 0.5
Table 2.6: Fig. 2.5 ratios values
Table 2.6 concrete values are presented and discussed in Section 3.3 while the impact of this factors on layout area will be clearly observed in Chapter 4.
Simulations at Schematic Level
This chapter presents and explains all the performed sim-ulations, and their results discussed. These are focused on the study of each FOM presented in Section 1.2.
3.1 Simulations Setup
Fig. 3.1 shows the schematic circuit used for the elec-trical simulations. A symbol for the designed circuit in Fig. 2.5 is created in order to simplify the analysis.
Regarding the Cadence simulator accuracy, it is set to the "conservative" option, the absolute tolerance values for voltages and currents at 10−6 and 10−12 respectively, and the minimal transconductance value at 10−12.
3.1.1 DC Simulation
The DC simulations are carried out in order to obtain the temperature dependence of Ibias and Vre f.
DUT
Reference
Circuit
Supply
Source
Ibias
Vref
Input
Source
On
Vdd
Figure 3.1: Simulation setup circuit including the DUT and the required voltage sources.
The sweep parameter in Cadence is set to temperature in a range between −20oC to 100oC (that is an extra-wide range when compared to the temperature range at which the X-Ray Imager usually works). The input source of Fig. 3.1 is set to 1.2 V, i.e ON state of the start-up circuit, as well as the supply source.
Another key study is the behaviour of Vre f and Ibias with the supply voltage. Therefore, with input source always set to 1.2V, the supply source voltage becomes the swept parameter (between 0 V and 1.2 V), to obtain the minimum supply voltage for which the Vre f value is higher than the 90% of its nominal value (at T = 27oC).
DC simulations can also be used to calculate the power dissipation, setting input and supply voltage sources to
1.2V.
3.1.2 AC Simulation
The AC simulation is done sweeping the supply source frequency from 0.1Hz to 1GHz and with input source set to 1.2V in order to obtain the PSRR of Vre f.
3.1.3 Transient Simulation
It is important to evaluate the time needed to turn on the reference circuit as said in Section 1.2. This is done by using input source as a voltage step with a delay time (changing its state from 0 to 1.2V).
The extracted start-up time is the time needed for Vre f to reach the 90% of its final value.
3.1.4 Montecarlo Simulation
Montecarlo simulations are done to study the mismatch effects, due to the statistical variability of transistor pa-rameters, on Vre f, Ibias, start-up time and temperature sensitivity values.
Both the main values and standard deviation values are extracted.
It must be remarked that, in this technology Cadence software kit, regular MOS devices must be replaced by their cell counterparts that include the mismatch models
(called "mac" transistors) at the schematic in order to be able to perform Montecarlo simulations, leading to an arduous design methodology.
3.1.5 Corners Simulation
In order to evaluate the process variations effects on Vre f, Ibias and the rest of key parameters such as start-up time or PSRR, different process corners are defined and these main parameters are resimulated under these different conditions:
• typical (typ): both NMOS and PMOS devices fol-lowing the so-called typical model and temperature and supply voltage taking the nominal values (27oC and 1.2V respectively).
• fast-fast (ff): both NMOS and PMOS devices fol-lowing the so-called fast model and temperature and supply voltage taking the nominal values (27oC and 1.2V respectively).
• slow-slow (ss): both NMOS and PMOS devices fol-lowing the so-called slow model and temperature and supply voltage taking the nominal values (27oC and 1.2V respectively).
• fast-best (fb): both NMOS and PMOS devices fol-lowing the so-called fast model but temperature set
at −25oC and supply voltage set at 1V.
• slow-worst (sw): both NMOS and PMOS devices following the so-called slow model but temperature set at 75oC and supply voltage set at 1.4V.
3.2 Results
All the simulations results are described and discussed in this section.
In all cases, it has been verified that the transistors operating regions coincide with the ones expected for the analysis presented in Section 2.1.1.
3.2.1 Sensitivity
One of the most important aspects in a reference cir-cuit for the given application is sensitivity. In particular thermal and supply sensitivities.
THERMAL SENSITIVITY
The thermal sensitivity shows the dependence on tem-perature of the voltage reference.
In this case, not only the behaviour of Vre f is studied, but also of Ibias, which affects the power consumption dependence on temperature.
-20 0 20 40 60 80 100 T [°C] 603 604 605 606 607 608 609 610 Vref [mV] 604.3 mV
Figure 3.2: Simulation results of Vre f dependence on
tempera-ture.
As it is possible to see in Fig. 3.2 , in a large range of temperature, the voltage reference Vre f changes from a minimum of Vre f−MI N = 603.4 mV to a maximum
Vre f−MAX = 609.8 mV with a total excursion of∆Vre f =
6.4 mV.
The value at T = 27oC of V
re f is 604.3 mV, meaning
that ∆Vre f (in this temperature range) is around 1.6% of Vre f nominal value.
Taking a temperature range between 0oC and 80oC, which are the worst case, the obtained sensitivity is around 123.7 ppm/oC, achieving the target specifications
(re-view Section 2.3). -20 0 20 40 60 80 100 T [°C] -125 -120 -115 -110 -105 -100 -95 Ibias [nA] -106 nA
Figure 3.3: Simulation results of Ibias dependence on
tempera-ture.
In the case of Ibias, represented in Fig. 3.3, in the same range of temperature, the minimum value is Ibias−MI N =
−122.22 nA and the maximum Ibias−MAX = −95.5 nA, with an excursion of ∆Ibias = −26.72 nA.
The value at T = 27oC is Ibias = −106 nA.
Here, ∆Ibias is around25% of the nominal value, which is a high percentage. However, it is not influential, since, as verified from the simulations, all the devices operat-ing points are not changed among these values range, allowing the circuit analysis exposed in Section 2.1.1.
SUPPLY VOLTAGE SENSITIVITY 0 0.2 0.4 0.6 0.8 1 1.2 Vdd [V] 0 100 200 300 400 500 600 700 Vref [mV] Vref-MIN = 543.87 mV Vdd-MIN = 777.9 mV
Figure 3.4: Simulation results of Vre f dependence on supply
voltage.
The supply voltage sensitivity is studied in order to assure a correct operation mode of the reference circuit, in this case under fluctuations of the supply voltage.
Fig. 3.4 shows the behaviour of Vre f vs. Vdd. In this analysis, the minimum acceptable value for Vre f is 90% of the typical value, i.e. 543.87 mV. Therefore, the min-imum supply voltage usable in this topologies that guar-antees a good behaviour is Vdd−MI N = 777.9 mV.
The same considerations are used studying Ibias. In Fig. 3.5 is evident that the 90% of Ibias is Ibias−MI N =
−95.4 nA and its corresponding Vdd value isVdd−MI N = 851.5 mV. 0 0.2 0.4 0.6 0.8 1 1.2 Vdd [V] -120 -100 -80 -60 -40 -20 0 Ibias [nA] Ibias-MIN = -95.4 nA Vdd-MIN = 851.5 mV
Figure 3.5: Simulation results of Ibias dependence on supply
voltage.
From this simple analyses, it is clear that Vdd−MI N
should be851.5 mV. However, using Vdd = 777.9 mV, it
has been checked that, for the corresponding Ibias value, the operating regions of the devices are the expected ones.
3.2.2 Power Supply Rejection Ratio
The PSRR is an important parameter to evaluate the ca-pability of an electronic circuit to suppress any power supply variations to its output signal.
It is defined as follows:
PSRRdB = 20log10Re f erenceRipple
SupplyRipple (3.1)
The PSRR is studied performing AC simulations and the result is shown in Fig. 3.6.
100 102 104 106 108 freq [Hz] -50 -45 -40 -35 -30 -25 -20 -15 PSRR [dB] -47.69 dB
Figure 3.6:Simulation results of the PSRR in Vre f.
It is important to notice that the same value, i.d. −47.69 dB, is constant up to frequencies in the order of 10 KHz, and it is satisfactory compared to the whole system spec-ifications, in which the reference circuit should be in-cluded.
3.2.3 Start-up Time
It is necessary to quantify the needed time to turn-on the whole reference circuit, influenced mainly by the capac-itances at the circuit nodes and the presence of the start-up circuit. 0 0.5 1 1.5 2 2.5 t [ s] 150 200 250 300 350 400 450 500 550 600 650 Vref [mV] 266.9 ns
Figure 3.7: Simulation results of Vre f during the turn-on phase
A transient simulation is done with a step from 0 to 1.2 V as input source, as specified in Section 3.1.3.
The time interval studied is between 0 and 5 µs with a delay of 10 ns for input source step.
Fig. 3.7 shows the Vre f curve only until 2.5 µs, for a more accommodated visualization, since it is clear that the signal becomes stable after about 1.5 µs.
The value of TON results equal to 266.9 ns, which accomplishes the target specification of Section 2.3.
560 570 580 590 600 610 620 630 640 0 50 100 150 200 250 300 Values Vref27 C [mV] No. of samples 560 570 580 590 600 610 620 630 640 0 50 100 150 200 250 300 mean = 603.59 mV std = 8.95 mV
Figure 3.8: Vre f at 27oC distribution obtained from 1000
Monte-carlo simulations. Mean (mean) and standard deviation (std dev) values are included.
3.2.4 Mismatch analysis
Montecarlo simulations are repeated for each of the pre-vious analysis.
In particular, a number of 1000 samples processed taking into account the mismatch models of the tech-nology devices in order to study the deviations on:
−1300 −125 −120 −115 −110 −105 −100 −95 −90 −85 50 100 150 200 250 300
Values Ibias27C [nA]
No. of samples −1300 −125 −120 −115 −110 −105 −100 −95 −90 −85 50 100 150 200 250 300 mean = -105.6 nA std = 5.86 nA
Figure 3.9: Ibias at 27oC distribution obtained from 1000
Monte-carlo simulations. Mean (mean) and standard deviation (std dev) values are included.
• Vre f at 27oC. Results are shown in Fig 3.8. • Ibias at 27oC. Results are shown in Fig 3.9.
• TON at 27oC. Results are shown in Fig 3.11. 50 100 150 200 0 50 100 150 200 250
Values Thermal Sensitivity [ppm/C]
No. of samples 50 100 150 200 0 50 100 150 200 250 mean = 126.08 ppm/°C std = 23.8 ppm/°C
Figure 3.10: Thermal sensitivity distribution obtained from 1000 Montecarlo simulations. Mean (mean) and standard de-viation (std dev) values are included.
Standard deviation and mean values of the studied pa-rameters are summarized in Table 3.1.
Parameter mean std dev Units
Vre f(27oC) 603.59 8.95 mV
Ibias(27oC) -105.6 5.86 nA
Thermal Sensitivity 126.07 23.80 ppm/oC
TON 266.9 27.77 ns
Table 3.1: Montecarlo simulations results summary.
All parameters extracted mean values are certainly close to the values extracted in each case using the
sim-180 200 220 240 260 280 300 320 340 360 380 0 50 100 150 200 250 Values Ton[nsec] No. of samples 180 200 220 240 260 280 300 320 340 360 380 0 50 100 150 200 250 mean = 276.9 ns std = 27.77 ns
Figure 3.11: TON at 27oC distribution obtained from 1000
Mon-tecarlo simulations. Mean (mean) and standard deviation (std dev) values are included.
ulations reported in previous Sections.
In the case of Vre f, a standard deviation of 8.95mV corresponds to about1.48% of the mean value (603.59mV), clearly comply with the required specifications.
The same happens regarding the standard deviation of Ibias, of 5.86nA corresponding to 5.55% of its mean value (−105.6nA).
On the other hand, a standard deviation of 23.80 ppm/
oC, corresponds to about 18.88% of the thermal
sensi-tivity mean value.
specification, this does not indicate an issue since the thermal sensitivity (in contrast to the absolute values for Vre f and Ibias) is a parameter with a restriction referring to its maximum value.
As can be checked in Fig 3.10, even taking into ac-count the mismatching effects, the specification on the thermal sensitivity (which should be < 200ppm/oC) is properly satisfied.
The same argument can be used when analyzing the Montecarlo simulation results on TON. With a standard deviation of 10.40% of its mean value, it confirms in Fig 3.11 that the target specification of a start-up time < 1µs is generously met.
Therefore, these results complete the verification that the main requirement regarding the robustness against PVT variations together with the conclusions extracted in previous sections 3.2.1 and the next section.
3.2.5 Technology corners analysis
The proposed design is also simulated under different process corners (as defined in Section 3.1.5) in order to evaluate its main parameters under these conditions.
Obtained results are summarized in Table 3.2.
From these results, it is clear that Vre f and Vdd−MI N
Parameter typ ff ss fb sw Units Vre f 604.3 545.5 660.1 546.1 667 mV Ibias -106 -104.3 -104.1 -118.9 -96.67 nA Temperature 123.7 -20.47 154.9 -20.47 143.9 ppm/oC Sensitivity PSRR @100 Hz -47.69 -51.9 -42.52 -44.89 -53.63 dB Vdd−MI N 777.9 665.6 903.3 723.6 851.8 mV Power 1.669 1.707 1.63 1.893 1.507 µW Consumption TON 266.9 235.9 289.7 379.6 197.2 ns Table 3.2: Simulation results of technology corners.
level but also on the technology corners.
Per contra, Ibias, power consumption and TON present low dependence on the technology corners.
The main reason of these parameters dependence on the technology corners can be explained taking into ac-count the variations of the technology parameters (such asVT0, n, α or β) on the defined corners, whose relations were stated in Section 2.1.1.
Following the same kind of reasoning as in the mis-matching analysis, it can be concluded that tempera-ture sensitivity, PSRR, Vdd−MI N, power consumption
and TON parameters remain within the margins marked by the target specifications detailed in Section 2.3.
3.3 Summary of Results
All the results obtained and presented in the previous sections are summarized in Table 3.3, which also
in-cludes the power consumption and Vptat extracted
val-ues.
Parameter Value Units
Vre f 604.3 mV Ibias 106 nA Vptat 93.58 mV Temperature sensitivity 123.7 ppm/oC Vdd−MI N 777.9 mV PSRR (@100Hz) −47.69 dB TON 266.9 ns Power consumption 1.669 µW
Vre f deviation 1.48 % of its nominal value Ibias deviation 5.86 % of its nominal value Temperature sensitivity deviation 18.87 % of its nominal value TON deviation 10.04 % of its nominal value
Table 3.3: Results summary.
The first and most important conclusion viewing these results is that the target specifications of Section 2.3 are achieved.
On the other hand, these results, obtained from sim-ulations of the circuit, can be compared to the expected theoretical values from the circuit analysis of Section 2.1.1 using design and technology parameters of Tables 2.4, 2.5 and 2.6 in Section 2.3.
These theoretical values are summarized in Table 3.4. It is evident that there are noticeable differences be-tween some parameters. While
q
QX
Y final value, based
only on design parameters Q, X and Y, is extracted from parametric simulations until required results are obtained, 2n1 α
param-Parameter Value Units Equation Vptat 88.02 mV 2.10: Vptat =Utln P Q 2.89 - 2.17: Q= lnP 2(M+1) q M N + q M N +M+1 2 Ibias 70.90 nA 2.16: Ibias =QIS7 Vre f (theoric 1) 600.3 mV 2.38: Vre f =2n q QX Y Ut +VT0 Vre f (theoric 2) 504 mV 2.40: Vre f =α+VT0(T0) q QX Y 5.89 - 2.41: q QX Y = 2n1 α Ut(T0) 1 2nUαt 4.19 - 2.41: q QX Y = 2n1 Ut(αT0) IS 490.67 nA 2.5: IS =2nβU2t Table 3.4: Theoretical results
eters extracted in Section 2.2.
In the latter, values are for a single given squared tran-sistor and has been proved not to be scalable while the simulations are performed on a much more complex cir-cuit using different devices with different dimensions.
Furthermore, the equality given by eq.(2.41) is based on a theoretical analysis without taking into account sec-ond order effects.
Exactly the same (and as a consequence of the pre-vious reasoning) happens when comparing Vre f in the
two theoretical cases and in Ibias value which, in turn, is calculated after various steps using IS together with technology and design parameters.
However, the (prior to the schematic design stage) manually and theoretical analysis and calculations shown in Section 2.1.1 are a robust starting point to begin the schematic design in order to reach the desired
specifica-tions, through a limited (and as low as possible) number of adaptations of the design parameters (and their corre-sponding simulations and results analysis), which takes time.
Layout Implementation
The main focus for the layout implementation is the circuit area while maintaining the target specifications listed in section 2.3 and achieved in the design phase as reported in section 3.2.
In this case, Calibre is used for the design rules vio-lation checking while Assura is used for the LVS com-parison.
Nevertheless, in the following list some design rule topics are discussed.
• minimum width and length of the geometries, spac-ing, enclosure, and extension imposed from the technology design kit have been respected but also squeezed.
• antenna effect is unnecessary to be verified because the used area for this design is very small. There-fore issues related to this problem are automatically avoided.
