Design and Simulation of 2 Gb/s short range transceiver with integrated antenna.

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Within the past years, wireless communications in the worldwide unlicensed 60 GHz band has become increasingly popular. Even though the precise frequency allocation is different in each country, all bands share a common 5 GHz of continuous bandwidth centered at 60 GHz, enabling multi Gb/s links in local networks. These networks aim to achieve a wireless transfer of video/audio signals and large files between electronic devices at a data rate of a few Gb/s. We remind that conventional RF solutions such as Bluetooth or WLAN can typically provide a data rate of hundreds of Mbps at most. Operating at mm-wave frequencies also makes possible the implementation of On-Chip antennas an transmission lines, thus determining the possibility to fabricate fully integrated transceivers, with evident benefits like reduced power overhead, reduced size and costs. Another emerging scenario for 60 GHz communication is Wireless Network on Chip (WiNoC) in modern multi-core processors. The single cores could access the network via RF nodes providing wireless links substituting traditional metal-interconnects for long/global links, improving both latency and power performances with data rate of tens Gb/s and efficiencies around 1 pJ/bit. This scenario is also viable for a more efficient clock distribution. This work, that constitutes a continuation and development of precedent theses, is subdivided into two main parts. In the first one, a simplified model of the Back End of Line of technology ST FDSOI 28 nm (courtesy of STMicroelectronics) was designed in software HFSS, and electromagnetic simulations of integrated antennas, inductors, baluns and transmission lines were performed and compared with the results for technologies UMC CMOS 65nm and ST SOI 65nm of precedent theses. This analysis evidenced minor differences for passives and antennas implementation in the technologies inspected, and the possibility to optimize a bow tie antenna for achieving a bandwidth of more than 10 GHz was verified . On-chip antennas can be both used for inter-chip and intra-inter-chip communication and the choice of the target application is partially related to the technology used. In fact WiNoCs are expected to become more popular in more scaled technology nodes, (e.g. FDSOI 28 nm) where the problem of multi-core communication overhead is more important and the increased cutoff frequency of active devices makes possible to satisfy the tight specifications imposed by a WiNoC. For a CMOS bulk 65nm the optimal target application is represented by a Wireless short range transceiver. In this work a fully integrated Wireless short range OOK transceiver with 2 Gb/s data rate was designed and simulated. The feasibility study of the front end was made more realistic by importing in the schematic passive components designed in HFSS that demonstrated that passive losses cannot be neglected for an accurate design. Eventually a link budget and high level considerations were presented, evidencing the necessity to use a high coding gain technique to reliably extend the communication distance to more than one meter reducing the effective data rate respect to the maximum possible data rate (3.5 Gb/s) to 2 Gb/s.

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CHAPTER 1 WIRELESS mm-WAVE APPLICATIONS

Motivations of communication in the 60 GHz Band and beyond.

Within the past years, wireless communications in the worldwide unlicensed 60 GHz band (Figure 1) has become increasingly popular. Even though the precise frequency allocation is different in each country, all bands share a common 5 GHz of continuous bandwidth centered at 60 GHz, enabling multi Gbps links in local networks.

Figure 1: Unlicensed 60 GHz frequency bands in various countries.

As illustrated in Figure 2, the Ft increase in the ultra-scaled technology nodes is generating a growing interest for mm-wave ICs, for a wide range of applications that go from 60 GHz WPAN, 77 GHz Automotive Long Range Radar (LRR) systems, active and passive imaging systems for security, medical applications.

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While SiGe or other technologies are in general more performing for mm-wave applications, as they provide higher speed active devices and lower substrate losses in passives, conventional CMOS is a viable, low cost alternative, and cutoff frequencies up to 1 THz are predicted for the end of this decade.

The present thesis is focused on the 60 GHz range and different technologies were examined and compared. Before discussing the possible applications fields for the devices designed in this work, it's necessary to provide a brief overview of the thesis organization.

Organization of the Thesis

CHAPTER 2 covers the challenges that are faced in the design, simulation and measurements of mm-wave passive components and antennas. An in depth description of the design flow in the finite element EM solver HFSS is given, and the choices for the settings applied in the simulations are justified.

in CHAPTER 3 The state of the art in mm-wave antennas is discussed, with special emphasis on antenna measurement techniques. Three recent works with interesting and experimentally backed results, and original experimental techniques were selected.

In CHAPTER 4 the HFSS modeling and simulations of integrated antennas, inductors, baluns and transmission lines are presented. The devices specifically simulated in this work were designed in a simplified model of the BEOL (Back End of Line) of the technology ST SOI 28 nm. These simulations were performed in the same conditions of previous theses where UMC CMOS 65nm and ST SOI 65nm had been studied. A comparative analysis of the results in different technologies was thus possible, evidencing minor differences for passives and antennas implementation. Automatic synthesis methods were also investigated and a theoretical background for the results was searched.

In CHAPTER 5 the state of the art in 60 GHz transceivers for Wireless short range is reported. An OOK transmitter in technology UMC CMOS 65nm was designed. The transmitter is composed by a cross-coupled oscillator, an OOK (On-Off Keying) modulator and a PA, and each of these blocks was separately characterized in detail. Power combining through a two and four way On-chip Wilkinson combiner was also evaluated to increase the output power of the transmitter extending the maximum communication distance. All these simulations were made more realistic importing the inductors and transmission lines from the library designed in HFSS for the same technology, RF MOM (Metal-On-Metal) capacitors models were already present in the DK libraries.

CHAPTER 6 puts together the results of CHAPTER 5 and [1], where a LNA in technology UMC (United Microelectronics Corporation) CMOS 65 nm had been designed, to conduct a link budget analysis on a fully integrated transceiver for wireless short range applications. The same On-chip dipole antenna co-designed for the CMOS 65 nm LNA was considered for the TX and the RX, allowing to use an antenna switch for a TDD .Other high level considerations are done and the opportunity to use a high coding gain method is considered, to reliably extend the communication distance reducing the effective data rate.

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It's clear that the thesis is approximately subdivided into two main parts:

The first part includes CHAPTER 2 , CHAPTER 3 and CHAPTER 4 while the second CHAPTER 5 and CHAPTER 6. While for the second part the object and target application is quite evident ( a 60 GHz transceiver for wireless short range), the On-chip antennas can be both used for inter-chip and intra-chip communication. In the following paragraphs these two possible scenarios are exemplified.

Wireless Networks-on-Chip (WiNOC) for Multicore Chips

Network-on-chips (NoCs) have emerged as communication backbones to enable a high degree of integration in multi-core systems on-chip (SoCs) [2]. Despite their advantages, an important performance limitation in traditional wire NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between two far apart blocks (distance > 1 cm) causes high latency and power consumption as evident in Figure 3:

Figure 3: Latency and power consumption for different interconnect paradigms.

According to the International Technology Roadmap for Semiconductors (ITRS), material innovation with traditional scaling down will no longer satisfy the performance requirements in the long term and radically new interconnect paradigms are needed. Different approaches such as 3-D metal NOCs, photonic NoCs and WiNoC are thus being studied to bridge the gap between the increasing performance of logic gates and processors, and the limits of existing interconnects that constitute the main bottleneck in modern systems. Pros and Cons of the three approaches are summarized in Table 1. Despite the advantages of first two paradigms, wireless NoCs are clearly the only viable solution if we don't want to face the problem of completely restructuring the technology process.

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3D NOC Photonic NOC Wireless NOC

Stacking of Multiple active Layers Manufacturability issues

Low yield

Temperature increase for power density problems

Ultra high bandwidth photonic links

On chip integration of photonic switches and components

High bandwidth Reduced latency and energy dissipation No revolutionary technology required

Table 1: Possible new interconnect paradigms.

The WiNOC scenario in Table 1 is an hybrid mesh-topology based NoC in which the single cores access the network via RF nodes providing both wireless and wired RF links. RF links become attractive for substituting long/global interconnects, while traditional wire communication should take place within a subnet. Radically different topologies have been proposed by network engineers for the subnets and the global network architecture to match different optimization goals. Regardless from the subnet topology each subnet will have a wireless base station composed of an antenna and a RF transceiver.

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The specification on the antenna and the transceiver for a wireless NoC application are thus totally different with respect to traditional wireless short range applications. In a wireless NoC the system dimension and power consumption should be minimized while the maximum bandwidth should represent one of the main goals, to achieve ultra high data rate at distances of a few millimeters. The differences between WiNoCs and wireless short range specifications are clearly explained in [3] from which Table 2 was taken:

WiNoCs Wireless short range

Link distance 1mm to 0.1m >1m

Channel Loss 28 to 48 dB >48dB

Data Rate > 4 Gbps <4 Gbps

BER < 10-12 < 10-3

Energy per Bit ≈10 pJ/bit ≈10 nJ/bit

Table 2: Different design criteria for WiNoC and conventional Wireless Short Range applications

in the same paper [3], a prototype of a WiNOC OOK transceiver implemented in a CMOS 65nm is presented with the results below:

frequency node antenna modulation Transmission range

Data Rate BER Energy/bit

63GHz CMOS

65nm

On-Chip Folded

OOK <1 cm 7.25 Gbps >10-10 8pJ/bit

Table 3: Results for WiNoC transceiver prototype in 65nm CMOS.

These data demonstrate the feasibility of a WiNoC but several issues should be addressed. The transmission distance needs to be increased up to a few centimeters since modern multi-core processors reach areas of 200÷600 mm2, with maximum distances within the same chip (approximately equal to the diagonal of a square with the same area) of 21÷ 35 mm.

As CMOS technology continues scaling down, exploiting the same circuit topologies with increased bandwidth, higher efficiency or lower power consumption becomes feasible, occupying less silicon area. For all these reasons, and also for the fact that multi-core architectures will be more frequent for nodes beyond CMOS 65nm, in CHAPTER 5 and CHAPTER 6 we decided to use the available Design Kit of UMC CMOS 65nm to design circuits for wireless short range. For a prototype of a WiNoC it would be more appropriate to use a more scaled technology like FDSOI 28 nm.

On the other hand in CHAPTER 2, CHAPTER 3 and CHAPTER 4 we decided to use the (confidential) information on the BEOL of process ST SOI 28 nm (Courtesy of STMicroelectronics) for an antenna design oriented to a WiNoC application. The dimensioning of the antenna was thus oriented to a reduced area occupation and ultra wide bandwidth. Instead the antenna selected for the wireless short range transceiver in CHAPTER 6 in the 65nm CMOS was simply the half-wavelength dipole, which, among the antennas examined, was the one presenting the better compromise between gain and bandwidth, and proved to be the most suitable to meet the constraints in Table 2.

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60 GHz Wireless Short Range

The 60-GHz Wireless Short range is one of the main candidates for high-speed indoor RF link owing to its 7-GHz available bandwidth (North America) . The interest for fully integrated transceiver as in CHAPTER 6 is therefore understood . Also the on chip integration of the antenna (CHAPTER 4) plays a key role for low-cost and low-power compact Wireless Short Range systems. There are numerous applications that may require such systems:

uncompressed video of high definition multimedia interface (HDMI)

High-speed file transfer among electronic devices and laptops, and fast movie or video game download.

wireless personal area networks (WPANs)

These networks aim to achieve a wireless transfer of video/audio signals and large files between electronic devices at a data rate of a few Gb/s. We can note that conventional RF solutions such as Bluetooth or WLAN can typically provide a data rate of hundreds of Mbps at most.

Bluetooth WLAN RFID mmW

Frequency 2.5 GHz 2.5/5.2 GHz 13.56 MHz 60 GHz

Data Rate <24 Mbps <0.2 Gbps 100 Kbps 3.5 Gbps

Energy/bit 0.42nJ 1nJ 1nJ < 100pJ

Table 4: mm Wave communication vs. lower frequency solutions

The scenario for Wireless Short Range interconnects is the one depicted in Figure 5. Both board to board and device to device communication should be possible. Obviously there is a trade-off between power consumption and maximum distance for a specified BER.

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In one of the most recent works (2013) [4] a CMOS 90nm transceiver with on-board antenna was successfully tested in a Video streaming demonstration (Figure 6). A full HD video signal was transmitted from a mobile phone to an HD Display over a distance up to one meter with a transceiver power consumption lower than 100mW.

Figure 6: wireless HD video transmission from mobile phone.

Obviously if we are intentioned to design a fully integrated transceiver, an antenna gain greater than 0 dBi (as we have for traditional On-board antennas) is very unlikely because of the low resistivity of Bulk CMOS substrates, and a higher output power at the transmitter will be required for comparable performance, resulting in a higher power dissipation.

We finally consider (regardless from the antenna choice) that the baseband circuitry for a Wireless Short range system are operating at several GHz. Consequently the DSP and ADC power consumption could be the bottleneck for a low-power design.

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CHAPTER 2 OVERVIEW OF mm-WAVE SIMULATIONS WITH HFSS

Experimental Setup

HFSS is a high-performance EM field simulator for arbitrary 3D devices; in the specific, in the present work, the software was used to design and simulate integrated transmission lines, lumped components and antennas [5].

The simulation technique used to calculate the full 3D electromagnetic field inside a structure is based on the finite element method. In this procedure a structure is subdivided into many smaller sub-domains called finite elements.

The finite elements used by HFSS are tetrahedra, and the entire collection of tetrahedra is called a mesh. A solution is found for the fields within the finite elements, and these fields are interrelated so that Maxwell’s equations are satisfied across inter-element boundaries, yielding a field solution for the entire original structure. Once the field solution has been found, the generalized S-matrix solution is determined.

The adaptive solution process

HFSS automatically performs an adaptive analysis, that is a solution process in which the mesh is iteratively refined. Refinement of the mesh is localized to regions where the electric field solution error is higher. This adaptive refinement increases the solution’s accuracy with each adaptive pass. The user sets the criteria that control mesh refinement during an adaptive field solution. The entire design Flow with the solution loop is shown in detail in Figure 7.

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Figure 7: HFSS solution process with ite

The convergence of the algorithm can be monitored during simulation thanks to a real time plot showing the maximum delta S versus iterative pass. Delta S is the magnitude of the change of the S

between two consecutive passes. Figure dipole designed in this work.

We can easily understand that the target delta S (i.e. the horizontal line in the plot) can be reached after a non monotonic transient in the first iterations, resulting in a completely erroneous solution. In order to prevent this mistake the standard settings of the simulator were partially modified

The target delta S was set to 0.01 (rather than 0.05) that corresponds to

matrix elements below 1%. This value guarantees a better accuracy without an unacceptable increase of the simulation time.

The number of consecutive passes that is required to ach to 1). This setting is extremely useful to avoid

where numerical errors are predominant.

12

: HFSS solution process with iterative mesh refinement.

The convergence of the algorithm can be monitored during simulation thanks to a real time plot showing the maximum delta S versus iterative pass. Delta S is the magnitude of the change of the S

Figure 8 shows the convergence plot of the CPS

We can easily understand that the target delta S (i.e. the horizontal line in the plot) can be reached after a nic transient in the first iterations, resulting in a completely erroneous solution. In order to prevent this mistake the standard settings of the simulator were partially modified:

The target delta S was set to 0.01 (rather than 0.05) that corresponds to

matrix elements below 1%. This value guarantees a better accuracy without an unacceptable increase of the simulation time.

The number of consecutive passes that is required to achieve convergence is set to 3 s setting is extremely useful to avoid an undesired convergence in the where numerical errors are predominant.

The convergence of the algorithm can be monitored during simulation thanks to a real time plot showing the maximum delta S versus iterative pass. Delta S is the magnitude of the change of the S-parameters shows the convergence plot of the CPS (Coplanar Stripline) fed

We can easily understand that the target delta S (i.e. the horizontal line in the plot) can be reached after a nic transient in the first iterations, resulting in a completely erroneous solution. In order to

The target delta S was set to 0.01 (rather than 0.05) that corresponds to an absolute error on S matrix elements below 1%. This value guarantees a better accuracy without an unacceptable

ieve convergence is set to 3 (rather than convergence in the initial transient

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Figure

Solution type

The two main solution types available in HFSS are listed and described in

Figure

Driven Modal

•Fields based transmission line interpretation • Port’s signal decomposed into incident and

reflected waves

• Excitation’s magnitude described as an incident power

•Energy propagates in a set of orthogonal modes

•Modes can be TE, TM and TEM w.r.t. the port’snormal

•Mode’s field pattern determined from entire port geometry

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Figure 8: Maximum error versus iterative pass.

ble in HFSS are listed and described in Figure 9:

Figure 9: HFSS solution types most commonly used.

Fields based transmission line interpretation Port’s signal decomposed into incident and Excitation’s magnitude described as an Energy propagates in a set of orthogonal Modes can be TE, TM and TEM w.r.t. the Mode’s field pattern determined from entire

Driven Terminal

• Circuit Based transmission line interpretation

• Excitation’s magnitude described as either a total voltage or an incident voltage

• Supports Differential S-Parameters •Each conductor touching the port is

considered a terminal or a ground

•Energy propagates along each terminal in a single TEM mode

Driven Terminal

Circuit Based transmission line

Excitation’s magnitude described as either a total voltage or an incident voltage

Parameters Each conductor touching the port is considered a terminal or a ground

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In the greatest part of the simulations performed in this work the driven terminal Unless otherwise specified we refer to this solution type in the following analysis. It’s quite obvious from the solution type characteristics listed above that f doesn’t matter which solution type is

In practice the rule of thumb contained in

hollow waveguides (metallic rectangular, circular…etc) condition is applied, while the Driven Terminal

This justifies the choice of using a driven terminal solutions, being conscious that a quasi TEM approximation is being used, that might be a partially inaccurate model for the innovative integrated transmission lines proposed in this work, whose actual field distribution and higher order modes are not yet well documented and supported by theoretical models in technical literatur

Boundary conditions

Among the several boundary conditions that can be set in HFSS, the radiation boundary was used since it simulates continued propagation beyond

to place the radiation boundary box

weakly radiating structures. Following this indications a quarter wavelength distance was always respected for any of the structures designed including passive components .

Excitations

There are two possible options to provide a stimulus to the structure: Lumped Ports and Wave ports

Coherently with the choice performed for the solution type, lumped ports were adopted . In man

components designed there is the need to provide the stimulus inside the geometrical model, that is not possible with a wave port excitation.

Wave ports

• Represent 2D Cross Section of a transmission line

• Can handle multiple modes or terminals • Defined on planar surface or face • Must encompass all fields that impact

transmission line behavior • Computes these TL quantities

Characteristic Impedance Propagation Constant Field Configurations

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In the greatest part of the simulations performed in this work the driven terminal Unless otherwise specified we refer to this solution type in the following analysis.

It’s quite obvious from the solution type characteristics listed above that for single mode TEM excitations it ter which solution type is used and identical results are obtained.

In practice the rule of thumb contained in [5] specifies that the Driven modal solution should be used for ollow waveguides (metallic rectangular, circular…etc) and any problem where

riven Terminal for microstrips, striplines, coplanar waveguide

This justifies the choice of using a driven terminal solutions, being conscious that a quasi TEM that might be a partially inaccurate model for the innovative integrated transmission lines proposed in this work, whose actual field distribution and higher order modes are not yet well documented and supported by theoretical models in technical literature.

Among the several boundary conditions that can be set in HFSS, the radiation boundary was used since it continued propagation beyond the boundary plane for radiating structures. The manual suggests

boundary box at least λ/4 from strongly radiating structures and

s. Following this indications a quarter wavelength distance was always respected for any of the structures designed including passive components .

are two possible options to provide a stimulus to the structure: Lumped Ports and Wave ports

Figure 10: HFSS available excitations.

Coherently with the choice performed for the solution type, lumped ports were adopted . In man

components designed there is the need to provide the stimulus inside the geometrical model, that is not possible with a wave port excitation.

Represent 2D Cross Section of a

Can handle multiple modes or terminals Defined on planar surface or face

Must encompass all fields that impact Computes these TL quantities

Characteristic Impedance Propagation Constant Field Configurations

Lumped Ports

• Represents a voltage source placed between conductors

• Can only handle a single TEM mode or terminal

• Defined on planar surface or face • Must be placed between conductor • User must specify characteristic

Impedance

In the greatest part of the simulations performed in this work the driven terminal solution was chosen.

or single mode TEM excitations it

specifies that the Driven modal solution should be used for a symmetry boundary coplanar waveguides, antennas. This justifies the choice of using a driven terminal solutions, being conscious that a quasi TEM that might be a partially inaccurate model for the innovative integrated transmission lines proposed in this work, whose actual field distribution and higher order modes are not

Among the several boundary conditions that can be set in HFSS, the radiation boundary was used since it for radiating structures. The manual suggests s and at least λ/10 from s. Following this indications a quarter wavelength distance was always respected

are two possible options to provide a stimulus to the structure: Lumped Ports and Wave ports:

Coherently with the choice performed for the solution type, lumped ports were adopted . In many of the components designed there is the need to provide the stimulus inside the geometrical model, that is not

Lumped Ports

Represents a voltage source placed Can only handle a single TEM mode or Defined on planar surface or face Must be placed between conductor

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The single TEM mode , with a driven terminal solution type, doesn’t imply further limitations except the approximation already discussed. Using a wave port would require a port dimensioning with the appropriate size to encompass all fields at the port and a user defined integration line for each mode; as a consequence of this increased complexity simulation time grows considerably. The main advantage of using wave ports is that the parameters that describe a transmission line (i.e. the characteristic impedance Z0 and the propagation constant γ) are automatically calculated.

We are certainly interested to evaluate Z0 for the structures examined even if this quantity is not directly available from a lumped port excitation setup. For this purpose the formula used in [6] was applied:

0 =

∙

1 + 11 ∙ 1 + 22 − 12 ∙ 21

_{1 − 11 ∙ 1 − 22 − 12 ∙ 21}

Equation 1: approximated formula for Z0 calculation.

Where Zref is the user specified characteristic impedance that needs to be set manually (50 Ohm).

Analysis

Figure 11 clearly shows the different operations performed by HFSS for the initial solution and the adaptive meshing loop. The initial mesh captures the geometrical details of the model, every vertex in the model is represented in the mesh. Seeding is an advanced capability inside HFSS which allows the user to control the mesh. In this work seeding was not used. Port solution uses a 2D FEM method on the port while Full volumetric solution uses the 3D FEM algorithm throughout the entire 3D volume calculating fields and S-matrix.

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Figure

In the Adaptive mesh loop an automatic mesh refinement takes place. The density of tetrahedral elements is higher in areas where a finer mesh is needed to accurately represent field behavior

radiating elements and transmission lines. On the other hand the mesh will be coarser increasing the distance from the antenna, where the target ΔS requirement can be met without increasing the mesh density and consequently, simulation time. As an example the mesh plot for the CPS

fed bow tie antenna is given in Figure

Figure 12: Mesh Plot for the

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Figure 11: Initial solution and frequency sweep in HFSS.

In the Adaptive mesh loop an automatic mesh refinement takes place. The density of tetrahedral elements mesh is needed to accurately represent field behavior

nsmission lines. On the other hand the mesh will be coarser increasing the distance from the antenna, where the target ΔS requirement can be met without increasing the mesh density and consequently, simulation time. As an example the mesh plot for the CPS

Figure 12 .

: Mesh Plot for the Bow tie antenna designed in this work.

In the Adaptive mesh loop an automatic mesh refinement takes place. The density of tetrahedral elements mesh is needed to accurately represent field behavior, in our case the nsmission lines. On the other hand the mesh will be coarser increasing the distance from the antenna, where the target ΔS requirement can be met without increasing the mesh density and consequently, simulation time. As an example the mesh plot for the CPS (Coplanar Stripline)

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Once the target accuracy required for the S

to add a frequency sweep to the solution setup. There are again three different options that need to be understood and evaluated.

Figure

Except in the case of a discrete frequency sweep, that would prove to be remarkably time demanding, neither an adaptive mesh refinement, nor a full volumetric solution is obtained for each frequency of the sweep. Instead interpolation ad extrapo

the interpolating and Fast sweeps. The reason why a Fast frequency sweep is preferable for our goals is that it generates the Fields for every frequency of the sweep enabling a post processin

and far fields parameters can be plotted versus frequency.

Mathematical description of the solution process

The mathematics involved in the solution process is fully independent from

it can be quite interesting and useful to have an idea of how the fields and the scattering matrix are produced in HFSS simulator and of how the linearization occurs

Once the structure is subdivided into tetrahedral elements a basis function Wn is defined for each tetrahedron. From Maxwell equations

Discrete Frequency Sweep

• Solves using adaptive mesh at every frequency. • Matrix Data and Fields

at every frequency in sweep.

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Once the target accuracy required for the S-Matrix has been reached the loop terminates. It’s now possible to add a frequency sweep to the solution setup. There are again three different options that need to be

Figure 13: Typologies of frequency sweep in HFSS.

Except in the case of a discrete frequency sweep, that would prove to be remarkably time demanding, neither an adaptive mesh refinement, nor a full volumetric solution is obtained for each frequency of the sweep. Instead interpolation ad extrapolation techniques from center frequency are used respectively in the interpolating and Fast sweeps. The reason why a Fast frequency sweep is preferable for our goals is that it generates the Fields for every frequency of the sweep enabling a post processin

and far fields parameters can be plotted versus frequency.

Mathematical description of the solution process

The mathematics involved in the solution process is fully independent from user interaction

nteresting and useful to have an idea of how the fields and the scattering matrix are and of how the linearization occurs.

Once the structure is subdivided into tetrahedral elements a basis function Wn is defined for each edron. From Maxwell equations Equation 2 is obtained, containing only E field dependency:

1

μr k

Equation 2: solution process step1

Interpolating Frequency Sweep

• The calculation of wide-band s-parameters in HFSS is achieved using the interpolating sweep.

This method fits s-parameter data to a

rational polynomial transfer function using a

minimum number of discrete finite element method (FEM) solutions. • Matrix Data at every

frequency in the sweep.

Fast Frequency Sweep

• Uses an Adaptive Sweep to extrapolate the field

solution across the requested frequency range from the center frequency field solution. • Matrix Data and Fields at

every frequency in has been reached the loop terminates. It’s now possible to add a frequency sweep to the solution setup. There are again three different options that need to be

Except in the case of a discrete frequency sweep, that would prove to be remarkably time demanding, neither an adaptive mesh refinement, nor a full volumetric solution is obtained for each frequency of the lation techniques from center frequency are used respectively in the interpolating and Fast sweeps. The reason why a Fast frequency sweep is preferable for our goals is that it generates the Fields for every frequency of the sweep enabling a post processing in which near fields

interaction. Nevertheless nteresting and useful to have an idea of how the fields and the scattering matrix are

Once the structure is subdivided into tetrahedral elements a basis function Wn is defined for each field dependency:

Fast Frequency Sweep

Uses an Adaptive Sweep to extrapolate the field

solution across the requested frequency range from the center frequency field solution. Matrix Data and Fields at

every frequency in sweep.

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If we weigh the first member of Equation 2 for the basis function of each tetrahedron and integrate over the entire volume, Equation 3 results:

Wn ∙ _μr1 − k #$ =

This procedure yields thousands of equations as many as the numbers of tetrahedra (i.e. n) produced by the adaptive meshing. Using Green’s theorem Equation 4 can be derived :

Wn ∙ _μr1 − k %& #$ = ' ()*+,-./ 01.23 #

If we put:

4 = 5 67%7 &

7

The new unknown is now Xm vector. We can rewrite Equation 4 as:

5 67 Wn ∙ _μr1 W8 − k %& %7 #$ = ' ()*+,-./ 01.23 #

Equation 6 has the form of:

5 679&,7= ;&

Or equivalently:

96 = ;

In the linear matrix equation, A is a nxn matrix that includes any applied boundary condition terms, while b contains the port excitations. It’s now possible to calculate the electric field from Equation 5. Since E is known it’s now possible to derive the Scattering Matrix with the conventional definition after having calculated the incident and reflected power at the ports.

<==_{?@ A ?};> B = 0 C>Dℎ F ≠ @

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CHAPTER 3 STATE OF THE ART FOR mm-WAVE ON CHIP ANTENNAS AND

MEASUREMENTS

In the following three previous works ( [7], [8], [9]) are presented, not only to provide an overview about the state of the art of On-chip antennas, and validate the present work with further material, but also to demonstrate that HFSS or CST simulations can be a reliable tool to successfully implement real world devices with experimental performances that show an excellent accordance with simulated results. The selection of these papers, was therefore oriented to examine works validated by a real On-Silicon implementation, with special emphasis on measurements methodologies and techniques to prevent artifacts.

A 60-GHz Millimeter-wave CMOS RFIC-on-Chip Triangular Monopole Antenna for

WPAN Applications.

In the first paper [7] a 60-GHz CMOS On-chip triangular monopole antenna is presented. The monopole is fed through a CPW (Coplanar Waveguide) and the software used is HFSS. The chip was fabricated in 0.18-μm bulk CMOS process.

Figure 14: HFSS geometry for the triangular monopole antenna designed in [7].

The top view of the structure and the 3D HFSS model are depicted in Figure 14 (a) and (b). In the paper the authors explain that the height of the triangular monopole (La) was set to a quarter wavelength of the operating frequency. It was found that the geometrical parameters that play a key role in determining the antenna bandwidth are the feeding gap (s) and the flare angle alpha (α). An optimization of bandwidth was

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studied in the simulations, showing an optimal flare angle around 60°. In the real dimensioning a smaller value of 30° was selected to save area on silicon. In this way the overall chip size including the CPW length is very reduced: 1x0.81 mm2. (the feeding gap value is not declared in the paper).

Figure 15: (a) micrograph of the triangular monopole in CMOS 0.18um (b) simulated and measured VSWR vs. frequency.

The triangular monopole was implemented and tested to verify the accordance of the most important parameters with the simulations.

In The 55-65 GHz range both the simulated and measured VSWR keep below the conventional threshold of 2 corresponding to a reflection coefficient of -10dB, testifying a good matching. In the simulations two main lobes in broadside directions were found in the Y-Z plane (refer to Figure 14 (b) for axis orientation), while the X-Y plane exhibits a nearly omnidirectional pattern. Although the complete radiation pattern can be very challenging to be experimentally traced (a technique is described in [9] and discussed later), a simpler on-wafer measurement can be set up to measure the actual power gain of the antenna in the direction of maximum gain.

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Figure 16: Experimental equipment used in [7] to measure maximum antenna gain.

In Figure 16 two identical antennas are placed side-by-side separated with a known distance R. An antenna will be used in transmission while the other receives. If the R distance satisfies the far field condition, Friis power transmission formula can be considered valid:

Prx #JK = LD6 #JK + MD6 #J> + M 6 #J> − 20 log Q|FK ∙ |MST − 92.4

Equation 10: Friis Power transmission formula

In Equation 10 transmitted power (Ptx) is known as well as R and f. With the RF probe and the VNA it's possible to directly measure S21, that is

X

YZ[

Y\[

X .

Once Prx is measured the gain of the antenna can be easily calculated. The paper indicates a simulated gain of -7.2dBi and an experimental gain of -9.4 dBi

An On-chip W-Band Bow tie Slot Antenna in Silicon

In this paper [10] a On-chip bow tie slot antenna over a low resistivity silicon substrate was designed and fabricated in a 180 nm BiCMOS process. The thickness and conductivity of the substrate are respectively 275 um and 12.5 S/m (this values are similar to the ones found for the more advanced technology nodes examined in our simulations). The geometry and dimensions are shown in Figure 17, as in [7] the overall area occupation is around 1mm2:

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Figure 17: micrograph of the bow tie antenna described in [10].

The authors state that the corners of the bow tie are optimized to improve current flowing around the edges. This technique is used to further increase the bow tie bandwidth. The antenna is realized in the top metal layer (M6). This is a common feature of many implementations since it generally allows the use of larger and thicker geometries. A CPS (Coplanar Stripline) is used as antenna feed and it's 50Ω matched. The reflection coefficient was simulated and tested with the results plotted in Figure 18 :

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As expected the bow tie slot antenna shows a very wide -10 dB input bandwidth covering the entire 70-110 GHz frequency range. The experimental reflection coefficient was measured with a RF probe, and to minimize artifacts due to pad effects and parasitic elements, an Open-Short calibration technique was conducted before the experiment. This technique is one of the many De-embedding methodologies that can be found in literature and are summarized in [11] . Figure 19 Graphically describes the procedure, that requires two extra structures (a) and (b), to be used as "dummy" test configurations. In this approach it's assumed that all parallel parasitic elements are taken into account in the OPEN configuration, while all series elements in the SHORT test. Once the measurements on the two dummy structures are available the PAD and RF probe influence can be eliminated (reduced) through Equation 11:

]^_` ₁ 1

]abcd− ]efbg−

1

]dhei`− ]efbg

Equation 11: Open-Short calibration formula.

Figure 19: (a) OPEN test (b) SHORT test (c) DUT test.

Finally the paper reports a measured broadside gain of -1dBi (estimated with the setup previously discussed), which is one of the highest values found in literature for On-chip antennas with low resistivity substrates.

On-Chip Integrated Antenna Structures in CMOS for 60 GHz WPAN Systems

This last paper [9] besides discussing a wide variety of integrated antennas topics, also introduces an experimental test apparatus that was implemented to perform advanced measurements. We will focus on this last topic.

The apparatus is an automated measurement system including a rotating conical horn antenna, a probe station and a VNA for frequencies up to 67GHz. Since the minimum far field distance is assumed to be :

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24 Q 2j_k

Equation 12: conventional minimum distance for Far-field approximation.

With a free-space wavelength around 5mm R is only 10mm. Hence an anechoic chamber is not required for a far field measurement and a distance of 10cm reasonably satisfies Equation 12 or any other far-field definition such as the ones in [12]. The other side of the coin is that an extremely expensive HF equipment is necessary (the total cost of the apparatus is around 106 US $).

The rotating receiving horn antenna is shown in Figure 20:

Figure 20: Receiving antenna. and computer controlled rotation angles. θ sets the vertical angle φ the horizontal.

φ and θ angles are incrementally stepped by computer controlled motors, while received power is measured and stored, enabling a program to construct the complete 3D far field pattern with high resolution. The receiving antenna is a conical antenna that guarantees high directivity and broad bandwidth [12]. It's also crucial that artifacts introduced by the probe station are minimized. For this reason the probe station should be covered with radio-adsorbing substances, and calibration of cables and probes is mandatory.

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CHAPTER 4 ANTENNAS AND PASSIVE STRUCTURES DESIGN IN DIFFERENT NANOSCALE

TECHNOLOGIES.

Introduction

In this chapter the results of EM simulations of On-chip antennas, lumped components and TLs (Transmission Lines) for different technologies at millimeter wave frequencies are discussed and compared. For each technology the same passive structures were studied and a different antenna topology was designed and optimized for a specific goal. Several methodologies to investigate the effect of EM interference on antenna performances were also proposed with the object to individuate the minimum spacing between radiating elements and other components as a possible future design rule.

The technologies that were considered in this work are: ST SOI 65nm, UMC BULK 65nm and ST FDSOI 28nm. More specifically ST SOI 65nm was analyzed in [13], and UMC BULK 65nm in [1], while the present work was focused on ST FDSOI 28nm and on the comparison with the results obtained in the previously studied technologies.

BEOLs and simplified models

In order to perform the 3D EM analysis with ANSOFT HFSS, the BEOL (Back End Of Line) of the aforementioned processes was simplified and a stack of equivalent layers were created using the formula in Equation 13 [14].

εeq opεqrs+_tq_{+ tqrs}tq ∙ (pεq pεqrs)u

Equation 13: Equivalent dielectric constant for two adjacent layers.

This formula substantially creates an equivalent layer from two adjacent layers, using as weights thicknesses and dielectric constants of the original layers. The formula can be iteratively used to model the entire BEOL with a few equivalent layers, reducing computational load.

ST SOI BEOL (schematically represented in Figure 21) is composed by 6 copper metal layers, an encapsulated aluminum metal layer (Alucap) and a Passivation. The active layer is separated from the high resistivity substrate by a thick buried oxide layer.

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UMC BULK 65nm (Figure 22) and FDSOI ST 28nm both use 10 metal levels, and the materials used for the metallization are respectively aluminum and copper. In BULK 65nm alucap was not used.

Besides these differences the two technologies obviously present different thicknesses and dielectric constants for all the layers, but if we consider their BEOL with the purpose of implementing antennas and passive structures, no relevant benefits result from adopting FDSOI ST 28nm rather than UMC BULK 65nm.

Figure 21: BEOL of ST SOI 65nm .

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27 This is fundamentally due to the following reasons:

The dielectrics surrounding the Metals and VIAs are not subjected to radical variations in more advanced technology nodes.

The ultra thin buried oxide (UTBOX), that is the main feature distinguishing FDSOI from a conventional CMOS process, presents a thickness of only 25nm with an equivalent dielectric constant of 3.9, since its purpose is just to reduce the leakage to the substrate confining the electrons in the channel. Reasonably this thin layer will not be able to provide an highly increased isolation from the substrate. For this reason if we choose this aspect as figure of merit, conventional CMOS and FDSOI are expected to show similar performances.

After these considerations Equation 13 has to be applied to form the simplified equivalent models for the three BEOLs. Since the amount of data to be used as input for Equation 13 is considerable a LabView VI was created to iteratively run the formula and automatically generate the model.

Figure 23: VI implementing Equation 13. The results are exported in a spreadsheet.

The procedure described leads to Table 5:

ST FDSOI 28nm UMC BULK 65 nm ST SOI 65 nm

LAYER NAME

Teq [um] ϵeq LAYER

NAME

Teq [um] ϵeq LAYER

NAME

Teq [um] ϵeq

passivation 3.75 3.76 passivation 2.17 4.79 passivation 0.54 5.49

alucap 1.45 4.54

alucap 1.2 5.49

dielM10 0.88 3.79 dielM10 0.8 3.84 dielM6 0.9 4.47

Diel_eq 4.2 3.52 Diel_eq 6.28 3.76 Diel_eq 2.76 3.46

BOX 0.145 4

T[um] ρ [Ω∙cm] T[um] ρ [Ω∙cm] T[um] ρ [Ω∙cm]

Substrate 279 20 Substrate 279 20 Substrate 350 10k

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In the following paragraphs it will be evident that the choice of a different technology, although being important for some parameters, plays a relatively minor role compared to the substrate, whose properties crucially influence the performances for the applications of our interest, as far as antennas and passives are the major concern.

Substrates Information

In Table 5 we evidence that for UMC BULK 65nm and FDSOI ST 28nm the same low-resistivity substrate (20Ω ∙ cm) with the same thickness was used (279 um); this makes possible to conduct a fair comparison between the two analyses.

The substrate used in ST SOI 65nm is totally different presenting an extremely high resistivity (10KΩ ∙ cm) and an increased thickness (350 um). For this reason, and for different boundary conditions that were set in [13], simulations data relative to ST SOI 65nm cannot be easily compared with the ones extracted from the other two technologies. Nevertheless where possible ST SOI 65nm will be included in the comparative analysis.

We remark that the substrate properties were selected considering realistic values generally associated to each technology. Detailed information about FDSOI substrate properties can be found in [15]. They are summarized in Figure 24 and Table 6.

Figure 24: SOITEC substrate for FDSOI technologies.

Wafer Diameter 300mm

Doping type P (Boron)

Resistivity 8÷22 Ω cm

Top silicon thickness 10÷30nm

BOX thickness 10÷145nm

Substrate thickness 120÷700um

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Some of the properties in Table 6 can be customized. Substrate thickness can be adjusted by the wafer "back grinding" performed before chip packaging.

In the following paragraph a short and qualitative description of active devices for technology ST SOI 65nm is given for completeness.

Active devices in technology ST FDSOI 28nm.

While in a conventional Bulk process the source and the drain are built in the silicon substrate, In technologies smaller than 28nm new solutions are required in order to increase performance, reduce complexity, still exploiting the benefits of reduced geometry.

Fully depleted silicon on insulator (FDSOI) is a planar approach that allows these benefits, without dramatically complicating the manufacturing process.

Unlike other 3D technologies (e.g. FinFet) FDSOI doesn't change the fundamental geometry of the transistor. In FDSOI the main innovation [16] is introduced by adding a thin layer of insulator called "buried oxide" positioned just below the channel and eliminating the need to add dopants to the channel, thus making it fully depleted.

Figure 25: FDSOI Transistor.

Another key innovative step, versus previous techniques, is that the silicon on the oxide layer is very thin. Together with the thin body channel layer, this technology is called ultra thin body and buried oxide (UTBB). On the same technology node (28nm) the FDSOI transistor has a shorter effective channel compared to a bulk silicon implementation. The shorter channel reduces the time necessary for the electron to flow from the source to the drain leading to a faster transistor.

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In order to improve the transistor speed or power performance a voltage can be applied to the substrate. This method is called back body biasing

switching of the transistor.

Thanks to the ultra thin insulator

making FDSOI acting like a vertical double gate transistor. In the FDSOI transistor the efficiently confines the electrons when flowing in the channel, drastically reducing the leaka

substrate. The increased performance versus conventional Bulk technology, for the typical digital applications is shown in Figure 26 and

These pictures refer to a Ericsson Smartphone speed (Max frequency [GHz] in Figure

power (i.e. the portion of total power consumed because of the sub threshold leakage current) becomes a significant portion of the total power

towards the substrate and other phenomena. the buried oxide layer dramatically reduces in Figure 27 which refer to the same processor of

For the same leakage power budget (20 mW), FDSOI provides 30% increase in frequency, or 1,32 GHz At the same frequency (1.2 GHz), approximately

10 mW for 28nm FDSOI compared with 100 m

Figure 26: Comparison between FDSOI and standard CMOS performance for standard digital applications

30

istor speed or power performance a voltage can be applied to the substrate. body biasing and facilitates the creation of the channel

layer, in FDSOI, the biasing creates a buried gate below the channel like a vertical double gate transistor. In the FDSOI transistor the

efficiently confines the electrons when flowing in the channel, drastically reducing the leaka

The increased performance versus conventional Bulk technology, for the typical digital and Figure 27.

es refer to a Ericsson Smartphone [17] (January 2013) processor and testify an improvement of Figure 26) and leakage power. In modern CMOS technologies leakage . the portion of total power consumed because of the sub threshold leakage current) becomes a significant portion of the total power, due to tunneling current through the gate oxide

and other phenomena. While substrate leakage greatly affects 28nm Bulk, in FDSOI the buried oxide layer dramatically reduces these losses determining the outstanding results documented

which refer to the same processor of Figure 26.

For the same leakage power budget (20 mW), FDSOI provides 30% increase in frequency, or 1,32 GHz approximately one order of magnitude difference in leakage power, with FDSOI compared with 100 mW for 28nm Low Power.

Comparison between FDSOI and standard CMOS performance for standard digital applications

istor speed or power performance a voltage can be applied to the substrate. facilitates the creation of the channel resulting in faster

eates a buried gate below the channel like a vertical double gate transistor. In the FDSOI transistor the insulator layer efficiently confines the electrons when flowing in the channel, drastically reducing the leakage to the The increased performance versus conventional Bulk technology, for the typical digital

testify an improvement of In modern CMOS technologies leakage . the portion of total power consumed because of the sub threshold leakage current) becomes a , due to tunneling current through the gate oxide, electrons leaking rate leakage greatly affects 28nm Bulk, in FDSOI

the outstanding results documented

For the same leakage power budget (20 mW), FDSOI provides 30% increase in frequency, or 1,32 GHz. one order of magnitude difference in leakage power, with

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Actually we remind that we are not interested in standard digital applications like a processor. As a consequence for our aim it's more meaningful to inspect the influence of FDSOI on cutoff frequency exploiting the data contained in [18] and plotted in Figure 28.

Figure 28: ITRS cutoff frequency data for conventional CMOS (square marker) FDSOI (triangle marker) and 3D (double triangle) MOSFETs. Data beyond 2011 are based on predictions.

These data reveal that FDSOI and conventional CMOS performances are nearly equal in terms of cutoff frequency. The major improvements will be obviously dictated by a reduced channel length.

Figure 27: leakage power vs. frequency for 28CMOS LP (VDD=1V), 28CMOS (VDD=0.85V) and 28FDSOI (VDD=0.9V) in a Ericsson Smartphone processor.

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Finally a significant plus of FDSOI is that the quantity of dopants is greatly reduced thereby limiting the process spread.

Transmission Lines Design

A great variety of TLs exist, however coplanar TLs (Coplanar Stripline (CPS) in Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b). (a) and Coplanar Waveguide (CPW) in Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b). (b) ) and microstrip TLs are the most appropriate to be integrated on silicon [19]. Microstrip TLs can be realized by using the top metal layer for the signal line and the lowest metal layer as the ground plane. The main drawback of this configuration is that the distance between the metal layers is fixed and the only degree of freedom is the signal trace width that mainly affects the line losses [19]. Since we are interested in dimensioning the characteristic impedance of the TLs, CPS and CPW were preferred over microstrip lines. In fact coplanar TLs entirely reside on the top metal layer and their Z0 can be efficiently controlled by varying the spacing between the conductors (in CPS) or between the conductor and the lateral ground planes (CPW). The HFSS geometry for both the TL is detailed in Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b). , where the degrees of freedom utilized in the dimensioning of the structures are highlighted with red arrows.

Figure 29: (a) geometry of the CPS (b) geometry of the CPW. The picture shows the stacking of the last metal (grey) and alucap (light blue). In UMC BULK 65nm this option is not available and only the last metal layer is present. Between the two layers a lateral offset (0.7um) was considered.

For the sake of clarity the association between the colors used in Figure 29 (a) and (b), layers in the stack and ports is summarized in Table 7 , which also clarifies which layers were hidden to make the 3D view understandable.

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Air Box passivation

Alucap Light Blue Diel

Alucap

M10 Grey Diel M10 Lumped

Ports Green PEC sheet Blue Diel_eq Substrate

Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b).

For the TLs a comparison between all the three technologies was considered meaningful since the same simulation configuration had been applied both in [13] and [1]. In Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b). only the metal geometry is visible for better clarity; These structures were designed inside the layer stacks described in Table 5. Lumped ports excitations (visible in green in Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b). (a) and (b)) were set. This introduces a Quasi-TEM approximation as discussed in CHAPTER 2.

The dimensioning (nominal dimensions) of the TLs in the technologies examined is reported in Table 8. The dimensions are compliant with the most relevant design rules for all the technologies (maximum metal width, minimum metal spacing).

FDSOI ST 28nm UMC BULK65nm ST SOI 65nm

C P S L_CPS [um] 610 550 552 W_CPS [um] 12 12 12 CPS_GAP [um] 1.2 1.1 1.1 C P W L_CPW [um] 610 550 552 W_CPW [um] 12 12 12 CPW_GAP [um] 6.2 4.5 12.2 W_GND [um] 120 120 120 METAL STACKING

Table 8: Nominal dimensions of the TL .

Coplanar Stripline: CPS

The CPS is a differential TL. Its length (L_CPS in Table 7: Hidden Layers (X) and color legend for Figure 29 (a) and (b). (a)) was tuned to form a quarter wavelength transformer. Tuning was necessary for each technology because it's necessary to consider the effective wavelength in the dielectric (not in air) interposed between the two conductors as shown in Equation 14:

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v_xL y

4 ∙ ∙ p z{{

Equation 14: dimensioning of L_CPS as a quarter wavelength transformer in an equivalent dielectric.

For the conductors width (W_CPS), the value of 12um was arbitrarily chosen for all the technologies. The Gap between the conductors (CPS_GAP) proved to be the parameter that mostly influences the characteristic impedance Z0 of the transmission lines. As we explained in CHAPTER 2, lumped ports prevent the possibility to automatically calculate Z0 in HFSS. For this reason an approximated formula is necessary. Equation 15 gives Z0 as a function of S parameters and can be used for both CPS and CPW as stated in [6].

0 ∙ (1 + 11 ∙ 1 + 22 − 12 ∙ 21_{1 − 11 ∙ 1 − 22 − 12 ∙ 21}

Equation 15: Approximated formula for Z0 calculation.

In Figure 30 the real and imaginary part of the CPS Z0 at 60GHz, in FDSOI 28nm are plotted for a sweep of the conductors gap. The nominal gap for both the TL in all the technologies was set imposing a value of 50Ω for the real part of Z0 in plots analogous to the one in Figure 30.

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Figure 30: Real part (red) and imaginary part (blue) of Z0 [Ω] @ 60 GHz for FDSOI ST 28nm for a sweep of the conductor gap from 0.5 to 6um.

If we are intentioned to use the TLs described in a multi-Gbps transceiver, the frequency behavior has to be studied to make sure the value of Z0 we set keeps fairly constant in a wide bandwidth, guaranteeing a good matching. In Figure 31 we observe that the value of Z0 which was set with the previous dimensioning for the central solution frequency of 60 GHz is not subjected to great variations in a wide range of frequencies, keeping its value in a range of ± 2Ω from the nominal value. Figure 31 also shows a sweep of L_CPS values for small variations from the nominal length. Similar plots were also found in the other technologies.

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Figure 31: FDSOI ST 28nm Re(Z0) vs. frequency for small variations of L_CPS from the nominal length.

Coplanar Waveguide :CPW

This TL is single ended and it’ optimal to feed antenna topologies where a ground plane is already present (e.g. the PIFA). For the dimensioning the same procedure used for the CPS was applied. The value for W_GND was set with:

%|g^ 10 ∙ %_xL%

Equation 16: lateral ground Planes approximation.

so that the ground planes width can be considered much greater than the conductor's. As a consequence the width of the ground plane will be ten times greater than the maximum metal width we set to ourselves as a limit. To overcome the design rules limit, in a physical implementation a grid structure may be used . From Figure 32 a nominal CPW_GAP of 6.2um is extracted for 28nm technology while CPS_GAP was 1.2um. Table 8 confirms that the spacing required for the CPW are significantly greater than those required for the CPS for all the technologies under test. Also for the CPW a frequency sweep demonstrates a good matching over a wide bandwidth. Rather than studying a plot as Figure 31, the voltage standing wave ratio (VSWR) can be equivalently plotted.

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Figure 32: Real part (red) and imaginary part (blue) of Z0 [Ω] @ 60 GHz for FDSOI ST 28nm for a sweep of the conductor gap from 1 to 10um.

The VSWR defined as:

$ %Q 1 + | 11|_{1 − | 11|}

Equation 17: VSWR definition.

The smallest the VSWR is, the better the antenna is matched to the transmission line and the more power is delivered to the antenna. The ideal VSWR is obviously 1 that is a null reflection coefficient. Also in this case the three technologies exhibit similar values close to unity as in Figure 33 for ST FDSOI 28nm.

Figure 33: FDSOI ST 28nm VSWR versus frequency for nominal dimensions.

1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 W_CPW_gap [um ] -10.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Y 1 CPW Re(Z0)_vs_gap_CPW ANSOFT

Curve Info XAtYVal(50)

im(Z0) Setup1 : LastAdaptive

Freq='60GHz' L_CPW='610um' W_CPW='12um' nan re(Z0)

Setup1 : LastAdaptive

Freq='60GHz' L_CPW='610um' W_CPW='12um' 6.2263

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Inductors and Baluns

Figure 34: (a) octagonal inductor (b) stacked balun (c) planar balun. The blue structure is a PEC ground ring.

The colors used in Figure 34 (a) and (c) have to be interpreted according to the legend given in Table 7 except for the fact that the dark blue layer is not a bi-dimensional sheet but a 3D ground ring (PEC) with the same thickness of the M10 and alucap layers put together. For Figure 34 (b) the same legend applies except for the red layer, which corresponds to the second winding (M9-M1). Also the ground ring was thickened accordingly. Obviously there is a VIA9 hidden layer separating the first and second winding which is not clearly visible in the 3D view due to the reduced dimension.

Design and Simulation of 2 Gb/s short range transceiver with integrated antenna.

CONTENTS

INTRODUCTION

CHAPTER 1

WIRELESS mm-WAVE APPLICATIONS

Motivations of communication in the 60 GHz Band and beyond.

Organization of the Thesis

Wireless Networks-on-Chip (WiNOC) for Multicore Chips

60 GHz Wireless Short Range

CHAPTER 2

OVERVIEW OF mm-WAVE SIMULATIONS WITH HFSS

Experimental Setup

0 =

∙

1 + 11 ∙ 1 + 22 − 12 ∙ 21

_{1 − 11 ∙ 1 − 22 − 12 ∙ 21}

CHAPTER 3

STATE OF THE ART FOR mm-WAVE ON CHIP ANTENNAS AND

MEASUREMENTS

A 60-GHz Millimeter-wave CMOS RFIC-on-Chip Triangular Monopole Antenna for

WPAN Applications.

X

X .

An On-chip W-Band Bow tie Slot Antenna in Silicon

On-Chip Integrated Antenna Structures in CMOS for 60 GHz WPAN Systems

CHAPTER 4

ANTENNAS AND PASSIVE STRUCTURES DESIGN IN DIFFERENT NANOSCALE

TECHNOLOGIES.

Introduction

BEOLs and simplified models

Transmission Lines Design

Inductors and Baluns