Appendice A. Il codice VHDL

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Appendice A. Il codice VHDL

spada_emulator.vhd

--- -- Title : FPGA design top module

-- Project : Spada_Emulator -- File : spada_emulator.vhd -- Author : Anna Cicciù -- Last update: 2004/12/12

-- Description: Spada_Emulator design top module

--- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- synopsys translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- synopsys translate_on entity spada_emulator is generic(

ENABLE_DMPORT_IP_INSTANCE : boolean := false;

ENABLE_EMUL_INSTANCE : boolean := true; TESTING_MODE : boolean := true;

OUT_NUMBER : integer := 1 );

port (

-- DSP EMIF

CPU_D_PAD: inout std_logic_vector(31 downto 0); CPU_CE0n_PAD: in std_logic;

CPU_CE1n_PAD: in std_logic; CPU_CE2n_PAD: in std_logic; CPU_CE3n_PAD: in std_logic;

CPU_A_PAD: in std_logic_vector(21 downto 2); CPU_BE0n_PAD: in std_logic;

CPU_BE1n_PAD: in std_logic; CPU_BE2n_PAD: in std_logic; CPU_BE3n_PAD: in std_logic; CPU_ECLKIN_PAD: out std_logic; CPU_ECLKOUT_PAD: in std_logic; CPU_AOEn_PAD: in std_logic; CPU_AREn_PAD: in std_logic; CPU_AWEn_PAD: in std_logic;

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CPU_ARDY_PAD: out std_logic; CPU_HOLDn_PAD: out std_logic; CPU_HOLDAn_PAD: in std_logic; CPU_BUSREQ_PAD: in std_logic; -- DSP HPI

CPU_HD_PAD: inout std_logic_vector(15 downto 0); CPU_HASn_PAD: out std_logic;

CPU_HRWn_PAD: out std_logic; CPU_HCSn_PAD: out std_logic; CPU_HDS1n_PAD: out std_logic; CPU_HDS2n_PAD: out std_logic; CPU_HRDYn_PAD: in std_logic; CPU_HINTn_PAD: in std_logic; CPU_HCNTL0_PAD: out std_logic; CPU_HCNTL1_PAD: out std_logic; CPU_HHWIL_PAD: out std_logic; CPU_EXT_INT4_PAD: out std_logic; CPU_EXT_INT5_PAD: out std_logic; PLD_EXT_INT6_PAD: out std_logic; PLD_EXT_INT7_PAD: out std_logic; CPU_NMI_PAD: out std_logic; -- DSP clock signals CPU_CLKOUT2_PAD: in std_logic; CPU_CLKOUT3_PAD: in std_logic; --*************************** -- micro-line connectors --***************************

-- connector A : used as output of spada_emulator ML_PIN_A1_PAD: out std_logic;

ML_PIN_A2_PAD: out std_logic; ML_PIN_A3_PAD: out std_logic; ML_PIN_A4_PAD: out std_logic; ML_PIN_A5_PAD: out std_logic; ML_PIN_A6_PAD: out std_logic; ML_PIN_A7_PAD: out std_logic; ML_PIN_A8_PAD: out std_logic; ML_PIN_A9_PAD: out std_logic; ML_PIN_A10_PAD: out std_logic; ML_PIN_A11_PAD: out std_logic; ML_PIN_A12_PAD: out std_logic; ML_PIN_A13_PAD: out std_logic; ML_PIN_A14_PAD: out std_logic; ML_PIN_A15_PAD: out std_logic; ML_PIN_A16_PAD: out std_logic; ML_PIN_A17_PAD: out std_logic; ML_PIN_A18_PAD: out std_logic; ML_PIN_A19_PAD: out std_logic;

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ML_PIN_A20_PAD: out std_logic; ML_PIN_A21_PAD: out std_logic; ML_PIN_A22_PAD: out std_logic; ML_PIN_A23_PAD: out std_logic; ML_PIN_A24_PAD: out std_logic; ML_PIN_A25_PAD: out std_logic; ML_PIN_A26_PAD: out std_logic; ML_PIN_A27_PAD: out std_logic; ML_PIN_A28_PAD: out std_logic; ML_PIN_A29_PAD: out std_logic; ML_PIN_A30_PAD: out std_logic;

ML_PIN_A31_PAD: inout std_logic; --inout std_logic; -- classic usage: ML_D30

ML_PIN_A32_PAD: inout std_logic; --inout std_logic; -- classic usage: ML_D31

-- connector B: classic usage: address bus

ML_PIN_B1_PAD: inout std_logic; -- classic usage: ML_A0 ML_PIN_B2_PAD: inout std_logic; -- classic usage: ML_A1 ML_PIN_B3_PAD: inout std_logic; -- classic usage: ML_A2 ML_PIN_B4_PAD: inout std_logic; -- classic usage: ML_A3 ML_PIN_B5_PAD: inout std_logic; -- classic usage: ML_A4 ML_PIN_B6_PAD: inout std_logic; -- classic usage: ML_A5 ML_PIN_B7_PAD: inout std_logic; -- classic usage: ML_A6 ML_PIN_B8_PAD: inout std_logic; -- classic usage: ML_A7 ML_PIN_B9_PAD: inout std_logic; -- classic usage: ML_A8 ML_PIN_B10_PAD: inout std_logic; -- classic usage: ML_A9 ML_PIN_B11_PAD: inout std_logic; -- classic usage: ML_A10 ML_PIN_B12_PAD: inout std_logic; -- classic usage: ML_A11 ML_PIN_B13_PAD: inout std_logic; -- classic usage: ML_A12 ML_PIN_B14_PAD: inout std_logic; -- classic usage: ML_A13 ML_PIN_B15_PAD: inout std_logic; -- classic usage: ML_A14 ML_PIN_B16_PAD: inout std_logic; -- classic usage: ML_A15 ML_PIN_B17_PAD: inout std_logic; -- classic usage: ML_A16 ML_PIN_B18_PAD: inout std_logic; -- classic usage: ML_A17 ML_PIN_B19_PAD: inout std_logic; -- classic usage: ML_A18 ML_PIN_B20_PAD: inout std_logic; -- classic usage: ML_A19 ML_PIN_B21_PAD: inout std_logic; -- classic usage: ML_A20 ML_PIN_B22_PAD: inout std_logic; -- classic usage: ML_A21 ML_PIN_B23_PAD: inout std_logic; -- classic usage: ML_A22 ML_PIN_B24_PAD: inout std_logic; -- classic usage: ML_A23 -- connector BB: classic usage: HPI

ML_PIN_BB1_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D0 ML_PIN_BB2_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D1 ML_PIN_BB3_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D2 ML_PIN_BB4_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D3

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ML_PIN_BB5_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D4 ML_PIN_BB6_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D5 ML_PIN_BB7_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D6 ML_PIN_BB8_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D7 ML_PIN_BB9_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D8 ML_PIN_BB10_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D9 ML_PIN_BB11_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D10 ML_PIN_BB12_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D11 ML_PIN_BB13_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D12 ML_PIN_BB14_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D13 ML_PIN_BB15_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D14 ML_PIN_BB16_PAD: inout std_logic;--out std_logic; -- classic usage: HPI_D15 ML_PIN_BB17_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HA0 ML_PIN_BB18_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HA1 ML_PIN_BB19_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HA2 ML_PIN_BB20_PAD: inout std_logic;--out std_logic; -- classic usage: reserved (ML_HA3)

ML_PIN_BB21_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HRWn

ML_PIN_BB22_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HCSn ML_PIN_BB23_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HSTRB1n

ML_PIN_BB24_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HSTRB2n

ML_PIN_BB25_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HRDY

ML_PIN_BB26_PAD: inout std_logic;--out std_logic; -- classic usage: ML_HINTn

ML_PIN_BB27_PAD: inout std_logic;--out std_logic; ML_PIN_BB28_PAD: inout std_logic;--out std_logic; ML_PIN_BB29_PAD: inout std_logic;--out std_logic; ML_PIN_BB30_PAD: inout std_logic;--out std_logic; ML_PIN_BB31_PAD: inout std_logic;--out std_logic; ML_PIN_BB32_PAD: inout std_logic;--out std_logic; --connector C: used as output of spada_emulator ML_PIN_C1_PAD: out std_logic;

ML_PIN_C2_PAD: out std_logic; ML_PIN_C3_PAD: out std_logic; ML_PIN_C4_PAD: out std_logic; ML_PIN_C5_PAD: out std_logic; ML_PIN_C6_PAD: out std_logic; ML_PIN_C7_PAD: out std_logic; ML_PIN_C8_PAD: out std_logic; ML_PIN_C9_PAD: out std_logic; ML_PIN_C10_PAD: out std_logic; ML_PIN_C11_PAD: out std_logic;

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ML_PIN_C12_PAD: out std_logic; ML_PIN_C13_PAD: out std_logic; ML_PIN_C14_PAD: out std_logic; ML_PIN_C15_PAD: out std_logic; ML_PIN_C16_PAD: out std_logic; ML_PIN_C17_PAD: out std_logic; ML_PIN_C18_PAD: out std_logic; ML_PIN_C19_PAD: out std_logic; ML_PIN_C20_PAD: out std_logic; ML_PIN_C21_PAD: out std_logic; ML_PIN_C22_PAD: out std_logic; ML_PIN_C23_PAD: out std_logic; ML_PIN_C24_PAD: out std_logic; ML_PIN_C25_PAD: out std_logic; ML_PIN_C26_PAD: out std_logic; ML_PIN_C27_PAD: out std_logic; ML_PIN_C28_PAD: out std_logic; ML_PIN_C29_PAD: out std_logic; ML_PIN_C30_PAD: out std_logic;

ML_PIN_C31_PAD: inout std_logic; -- classic usage: ML_STR_D30 ML_PIN_C32_PAD: inout std_logic; -- classic usage: ML_STR_D31 --connector D: classic usage: ML peripheral interface

ML_PIN_D10_PAD: inout std_logic; -- classic usage: ML_CS1n ML_PIN_D11_PAD: inout std_logic; -- classic usage: ML_CS2n ML_PIN_D12_PAD: inout std_logic; -- classic usage: ML_CS3n ML_PIN_D13_PAD: inout std_logic; -- classic usage: ML_CS4n ML_PIN_D14_PAD: inout std_logic; -- classic usage: ML_CS5n ML_PIN_D15_PAD: inout std_logic; -- classic usage: ML_CS6n ML_PIN_D16_PAD: inout std_logic; -- classic usage: ML_CS7n ML_PIN_D17_PAD: inout std_logic; -- classic usage: ML_INT0n ML_PIN_D18_PAD: inout std_logic; -- classic usage: ML_INT1n ML_PIN_D19_PAD: inout std_logic; -- classic usage: ML_INT2n ML_PIN_D20_PAD: inout std_logic; -- classic usage: ML_INT3n ML_PIN_D21_PAD: inout std_logic; -- classic usage: ML_NMIn ML_PIN_D22_PAD: inout std_logic; -- classic usage: ML_IORDn ML_PIN_D23_PAD: inout std_logic; -- classic usage: ML_IOWRn ML_PIN_D24_PAD: inout std_logic; -- classic usage: ML_RWn ML_PIN_D25_PAD: inout std_logic; -- classic usage: ML_IOSTRBn ML_PIN_D30_PAD: inout std_logic; -- classic usage: ML_RDY ML_PIN_D31_PAD: inout std_logic; -- classic usage: ML_HOLDn ML_PIN_D32_PAD: inout std_logic; -- classic usage: ML_HOLDAn --connector E -- classic usage: a) streaming port

-- b) board specific

ML_PIN_E1_PAD: inout std_logic; -- classic usage: ML_ISO_PAEn ML_PIN_E2_PAD: inout std_logic; -- classic usage: ML_ISO_PAFn

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ML_PIN_E3_PAD: inout std_logic; -- classic usage: ML_ISO_FCLKn ML_PIN_E4_PAD: inout std_logic; -- classic usage: ML_ISO_ROEn ML_PIN_E5_PAD: inout std_logic; -- classic usage: ML_ISO_RENn ML_PIN_E6_PAD: inout std_logic; -- classic usage: ML_ISO_WENn ML_PIN_E7_PAD: inout std_logic; -- classic usage: ML_ISO_TSYNC ML_PIN_E8_PAD: inout std_logic; -- classic usage: ML_ISO_RSYNC ML_PIN_E9_PAD: inout std_logic; -- classic usage: ML_ISO_PKT_ID ML_PIN_E31_PAD: inout std_logic; -- classic usage: ML_EMIF_CLK ML_PIN_E32_PAD: inout std_logic; -- classic usage: ML_SHZn --connector X

ML_PIN_X1_PAD: inout std_logic; ML_PIN_X2_PAD: inout std_logic; ML_PIN_X3_PAD: inout std_logic; ML_PIN_X4_PAD: inout std_logic; ML_PIN_X5_PAD: inout std_logic; ML_PIN_X6_PAD: inout std_logic; ML_PIN_X7_PAD: inout std_logic; ML_PIN_X8_PAD: inout std_logic; ML_PIN_X9_PAD: inout std_logic; ML_PIN_X10_PAD: inout std_logic; --IEEE1394 LLC

LL_DMD_PAD: inout std_logic_vector(15 downto 0); LL_DMCLK_PAD: in std_logic;

LL_DMRW_PAD: in std_logic; LL_DMDONE_PAD: in std_logic; LL_DMREADY_PAD: out std_logic; LL_DMPRE_PAD: in std_logic; LL_DMERROR_PAD: in std_logic; LL_PKTFLAG_PAD: in std_logic; LL_CYCLEIN_PAD: out std_logic; LL_CYSTART_PAD: in std_logic; LL_STAT1_PAD: in std_logic; -- bus driver control

DRV_DIR_DATA_TO_DSP_PAD: out std_logic; DRV_EN_DATA_0_15n_PAD: out std_logic; DRV_EN_DATA_16_31n_PAD: out std_logic; DRV_DIR_ADDR_TO_DSP_PAD: out std_logic; DRV_EN_ADDR_0_7n_PAD: out std_logic; DRV_EN_ADDR_8_15n_PAD: out std_logic; DRV_DIR_HPI_TO_HOST_PAD: out std_logic; DRV_EN_HPI_0_7n_PAD: out std_logic; DRV_EN_HPI_8_15n_PAD: out std_logic; -- LED control

LED_REDn_PAD: out std_logic; LED_GREENn_PAD: out std_logic; --UART clock from PLD

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-- physically unconnected pads

UNUSED_PAD: out std_logic_vector(22 downto 0) );

end spada_emulator;

architecture behaviour of spada_emulator is -- don't flatten hierarchy directive

attribute dont_flatten : string;

-- at least needed for connecting unused inputs (avoiding warnings) component IBUF

port (I: in std_logic; O: out std_logic); end component;

-- XST black box declaration attribute box_type : string;

attribute box_type of IBUF: component is "black_box";

-- at least needed for connecting unused inouts (avoiding warnings) component IOBUF

port (I, T: in std_logic; O: out std_logic; IO: inout std_logic); end component;

-- XST black box declaration --attribute box_type : string;

attribute box_type of IOBUF: component is "black_box"; --clock_manager declaration

component clock_manager is port (

RST_IN : in std_logic; CLKIN_IN : in std_logic; LOCKED_OUT : out std_logic; CLK0_OUT : out std_logic); end component;

--DM_PORT declaration component DMPORT port(

DMPORT_RST_I : IN std_logic;

DMPORT_ADDR_I : IN std_logic_vector(3 downto 0); DMPORT_DATA_I : IN std_logic_vector(31 downto 0);

DMPORT_DATA_O : OUT std_logic_vector(31 downto 0); DMPORT_RD_I : IN std_logic;

DMPORT_RDSTRBN_I : IN std_logic;

DMPORT_WR_I : IN std_logic;

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DMPORT_INT_O : OUT std_logic; DMPORT_16_32 : IN std_logic;

LLC_DMD : INOUT std_logic_vector(15 downto 0);

LLC_DMCLK : IN std_logic;

LLC_DMDONE : IN std_logic;

LLC_DMRW : IN std_logic;

LLC_DMREADY : OUT std_logic;

LLC_DMPRE : IN std_logic;

LLC_DMERROR : IN std_logic;

LLC_PKTFLAG : IN std_logic;

LLC_CYCLESTART : IN std_logic;

DMPORT_SD_DATA_O : OUT std_logic_vector(31 downto 0); DMPORT_SD_DATA_OEN : OUT std_logic;

DMPORT_SD_DATA_I : IN std_logic_vector(31 downto 0); DMPORT_SD_CLK_I : IN std_logic;

DMPORT_SD_WEN_FEN_I : IN std_logic;

DMPORT_SD_REN_LEN_I : IN std_logic;

DMPORT_SD_DATA_REQN_O : OUT std_logic; DMPORT_SD_BLOCK_REQN_O : OUT std_logic;

DMPORT_SD_PKT_ID : OUT std_logic;

DMPORT_SD_TSYNC : IN std_logic;

DMPORT_SD_RSYNC : OUT std_logic);

end component;

-- XST black box declaration. XST :Xylinx Synthesis Technology --attribute box_type : string;

attribute box_type of DMPORT: component is "black_box"; -- Emulator_core declaration

component emulator_core is port(

EMUL_CLK : in std_logic;

EMUL_RST : in std_logic;

EMUL_ADDR : in std_logic_vector(18 downto 0); --2MB EMUL_DATA_I : in std_logic_vector(31 downto 0);

EMUL_WR : in std_logic; --acts like a chip select EMUL_WR_STRBn : in std_logic;

EMUL_SIGNAL : out std_logic_vector(59 downto 0);

EMUL_GREENn_LED : out std_logic;

EMUL_REDn_LED : out std_logic;

EMUL_DATA_O : out std_logic_vector(31 downto 0);

EMUL_RD : in std_logic; --acts like a chip select

EMUL_RD_STRBn : in std_logic

); end component;

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-- signal for unused inputs

signal UNUSED_INPUT: std_logic_vector (47 downto 1); -- signal for unused bidirectional pads

signal UNUSED_INOUT: std_logic_vector (271 downto 48); -- global system reset

signal GSR: std_logic;

-- we use EMIF ECLKOUT as system clock at value :90 MHz

signal SYSTEM_CLK: std_logic;

-- EMIF data multiplexer

signal CPU_DATA_O: std_logic_vector(31 downto 0); --******** streaming core signals ******************* -- streaming core register data bus

signal DM_REG_DATA_O: std_logic_vector(31 downto 0); signal DM_REG_DATA_I: std_logic_vector(31 downto 0); -- streaming core select

signal DM_CS : std_logic; signal DM_CS_RD : std_logic; signal DM_CS_WR : std_logic; --*************************** -- **** EMUL signals ******* --*************************** -- EMUL registers data bus

signal EMUL_REG_DATA_O: std_logic_vector(31 downto 0); --EMUL output data

signal EMUL_REG_DATA_I: std_logic_vector(31 downto 0); --EMUL input data

-- EMUL chip select and write/read enable signal EMUL_CS : std_logic;

signal EMUL_CS_RD : std_logic; signal EMUL_CS_WR : std_logic;

signal CPU_AREn_PAD_C : std_logic; -- clock path (fast) signal CPU_AWEn_PAD_C : std_logic; -- clock path (fast) signal CPU_AREn_PAD_B : std_logic; --normal path

signal CPU_AWEn_PAD_B : std_logic; --normal path -- EMUL spada input signals vector

signal EMUL_SPADA_SIGNAL : std_logic_vector(59 downto 0); signal DCM_IS_LOCKED : std_logic; -- make vhdl analizer happy!!! -- internal registers

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begin -- architecture behaviour -- set unused outputs to 'Z'

-- this avoids warnings about unused pads

-- note: the board hardware has pull-up resistors where necessary, -- so the outputs may remain at 'Z'.

CPU_ECLKIN_PAD <= 'Z'; CPU_ARDY_PAD <= 'Z'; CPU_HOLDn_PAD <= 'Z'; CPU_HASn_PAD <= 'Z'; CPU_HRWn_PAD <= 'Z'; CPU_HCSn_PAD <= 'Z'; CPU_HDS1n_PAD <= 'Z'; CPU_HDS2n_PAD <= 'Z'; CPU_HCNTL0_PAD <= 'Z'; CPU_HCNTL1_PAD <= 'Z'; CPU_HHWIL_PAD <= 'Z'; CPU_EXT_INT4_PAD <= 'Z'; CPU_EXT_INT5_PAD <= 'Z'; PLD_EXT_INT6_PAD <= 'Z'; PLD_EXT_INT7_PAD <= 'Z'; CPU_NMI_PAD <= 'Z'; LL_DMREADY_PAD <= 'Z'; LL_CYCLEIN_PAD <= 'Z'; --************************************************ --******* connect unused inputs to an IBUF*********

--******this avoids warnings about unused pads*******

U1: IBUF port map (I => CPU_CE0n_PAD, O => UNUSED_INPUT(1)); U2: IBUF port map (I => CPU_CE1n_PAD, O => UNUSED_INPUT(2)); U6: IBUF port map (I => CPU_BE0n_PAD, O => UNUSED_INPUT(25)); U7: IBUF port map (I => CPU_BE1n_PAD, O => UNUSED_INPUT(26)); U8: IBUF port map (I => CPU_BE2n_PAD, O => UNUSED_INPUT(27)); U9: IBUF port map (I => CPU_BE3n_PAD, O => UNUSED_INPUT(28));

U14: IBUF port map (I => CPU_HOLDAn_PAD, O => UNUSED_INPUT(33));

U15: IBUF port map (I => CPU_BUSREQ_PAD, O => UNUSED_INPUT(34)); U16: IBUF port map (I => CPU_HRDYn_PAD, O => UNUSED_INPUT(35)); U17: IBUF port map (I => CPU_HINTn_PAD, O => UNUSED_INPUT(36));

U18: IBUF port map (I => CPU_CLKOUT2_PAD, O => UNUSED_INPUT(37));

U19: IBUF port map (I => CPU_CLKOUT3_PAD, O => UNUSED_INPUT(38));

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U21: IBUF port map (I => LL_DMRW_PAD, O => UNUSED_INPUT(40)); U22: IBUF port map (I => LL_DMDONE_PAD, O => UNUSED_INPUT(41));

U23: IBUF port map (I => LL_DMPRE_PAD, O => UNUSED_INPUT(42));

U24: IBUF port map (I => LL_DMERROR_PAD, O => UNUSED_INPUT(43));

U25: IBUF port map (I => LL_PKTFLAG_PAD, O => UNUSED_INPUT(44));

U26: IBUF port map (I => LL_CYSTART_PAD, O => UNUSED_INPUT(45));

U27: IBUF port map (I => LL_STAT1_PAD, O => UNUSED_INPUT(46)); U28: IBUF port map (I => PLD_UART_CLK_PAD,O => UNUSED_INPUT(47));

U30_loop: for bit in 15 downto 0 generate

U30: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(bit + 80), IO => CPU_HD_PAD(bit));

end generate U30_loop;

--***************************

--******CONNECTOR A****

--***************************

U61: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(126), IO => ML_PIN_A31_PAD);

U62: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(127), IO => ML_PIN_A32_PAD); --*************************** --******CONNECTOR B***** --****************************

U63: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(128), IO => ML_PIN_B1_PAD);

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--*****************************

--******CONNECTOR BB*****

--*****************************

U87: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(152), IO => ML_PIN_BB1_PAD);

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--*****************************

--******CONNECTOR C*******

--*****************************

U149: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(214), IO => ML_PIN_C31_PAD);

U150: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(215), IO => ML_PIN_C32_PAD);

--******************************

--******CONNECTOR D*******

--******************************

U151: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(216), IO => ML_PIN_D10_PAD);

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--******CONNECTOR E*******

U170: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(235), IO => ML_PIN_E1_PAD);

--******CONNECTOR X*******

U181: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(246), IO => ML_PIN_X1_PAD);

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--IEEE1394 LLC U191_loop: for bit in 15 downto 0 generate begin -- generate U191_loop

U191: IOBUF port map (I => '0', T => 'Z', O => UNUSED_INOUT(bit + 256), IO => LL_DMD_PAD(bit));

end generate U191_loop;

-- FPGA pins that aren't available UNUSED_PAD <= (others => 'Z');

--******** LOCK HPI TRANSCEIVERS DRIVING SIGNALS *********************

DRV_DIR_DATA_TO_DSP_PAD <= '0'; --dir from dsp to ext pins DRV_EN_DATA_0_15n_PAD <= '1'; --driver enabled

DRV_EN_DATA_16_31n_PAD <= '1'; --driver enabled

DRV_DIR_ADDR_TO_DSP_PAD <= '0'; --dir from dsp to ext pins

DRV_EN_ADDR_0_7n_PAD <= '1'; --driver disabled

DRV_EN_ADDR_8_15n_PAD <= '1'; --driver disabled

DRV_DIR_HPI_TO_HOST_PAD <= '0'; --abilita bassi dir from dsp to ext pins

DRV_EN_HPI_0_7n_PAD <= '1'; --abilita alti driver disabled DRV_EN_HPI_8_15n_PAD <= '1'; --driver disabled

--********** streaming core instance ************************** dmport_instance: if (ENABLE_DMPORT_IP_INSTANCE) generate

streaming_core : DMPORT

port map(

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DMPORT_ADDR_I => CPU_A_PAD(5 downto 2), DMPORT_DATA_I => DM_REG_DATA_I, DMPORT_DATA_O => DM_REG_DATA_O, DMPORT_RD_I => DM_CS_RD, DMPORT_RDSTRBN_I => CPU_AREn_PAD, DMPORT_WR_I => DM_CS_WR, DMPORT_WRSTRBN_I => CPU_AWEn_PAD, DMPORT_INT_O => CPU_EXT_INT4_PAD, DMPORT_16_32 => '1', LLC_DMD => LL_DMD_PAD, LLC_DMCLK => LL_DMCLK_PAD, LLC_DMDONE => LL_DMDONE_PAD, LLC_DMRW => LL_DMRW_PAD, LLC_DMREADY => LL_DMREADY_PAD, LLC_DMPRE => LL_DMPRE_PAD, LLC_DMERROR => LL_DMERROR_PAD, LLC_PKTFLAG => LL_PKTFLAG_PAD, LLC_CYCLESTART => LL_CYSTART_PAD, DMPORT_SD_DATA_I => x"00000000", DMPORT_SD_CLK_I => '0', DMPORT_SD_WEN_FEN_I => '1', DMPORT_SD_REN_LEN_I => '1', DMPORT_SD_TSYNC => '0' ); end generate; --***************************************************************** -- **************** EMUL instance ******************************* --***************************************************************** EMUL_instance: if (ENABLE_EMUL_INSTANCE) generate

data_proc_module : emulator_core

port map(

EMUL_CLK => SYSTEM_CLK , EMUL_RST => GSR,

EMUL_ADDR => CPU_A_PAD(20 downto 2),

EMUL_DATA_I => EMUL_REG_DATA_I, EMUL_DATA_O => EMUL_REG_DATA_O, EMUL_RD => EMUL_CS_RD, EMUL_RD_STRBn => CPU_AREn_PAD, EMUL_WR => EMUL_CS_WR, EMUL_WR_STRBn => CPU_AWEn_PAD, EMUL_SIGNAL => EMUL_SPADA_SIGNAL, EMUL_GREENn_LED => LED_GREENn_PAD, EMUL_REDn_LED => LED_REDn_PAD ); end generate;

(18)

-- **************** dsp data multiplexer ************************

EMIF_DATA_MUX: process (DM_CS, CPU_DATA_O, DM_REG_DATA_O(31 downto 0),

EMUL_CS, EMUL_REG_DATA_O(31

DOWNTO 0)) begin

if EMUL_CS = '1' then -- EMUL module is selected

CPU_DATA_O <= EMUL_REG_DATA_O(31 downto 0); elsif DM_CS = '1' then -- streming core is selected

CPU_DATA_O <= DM_REG_DATA_O(31 downto 0);

else

CPU_DATA_O <= (others => '-');

end if;

end process;

-- *************** dsp data tristate buffer *****************

EMIF_READ_DATA_DRIVER: process (CPU_AREn_PAD, DM_CS, CPU_DATA_O,

EMUL_CS) begin

if(CPU_AREn_PAD = '0' and EMUL_CS = '1') then CPU_D_PAD <= CPU_DATA_O;

elsif(CPU_AREn_PAD = '0' and DM_CS = '1') then CPU_D_PAD <= CPU_DATA_O;

else

CPU_D_PAD <= (others => 'Z');

end if;

end process;

--**********CPU_emif-dmport core connections*************-- DM_REG_DATA_I <= CPU_D_PAD(31 downto 0);

DM_CS <= (not CPU_CE3n_PAD and not CPU_A_PAD(21)

and not CPU_A_PAD(20)

and not CPU_A_PAD(19)

and not CPU_A_PAD(18)); DM_CS_RD <= DM_CS and not CPU_AOEn_PAD;

DM_CS_WR <= DM_CS and CPU_AOEn_PAD;

--******************************************************** --**********CPU_emif-EMUL core connections**************** --******************************************************** EMUL_REG_DATA_I <= CPU_D_PAD(31 downto 0);

EMUL_CS <=((not CPU_CE2n_PAD) and (CPU_A_PAD(21)));

(19)

EMUL_CS_WR <= EMUL_CS and CPU_AOEn_PAD;-- cpu is writing] --************************** dcm_instance: clock_manager port map ( RST_IN => GSR, CLKIN_IN => CPU_ECLKOUT_PAD, LOCKED_OUT => DCM_IS_LOCKED, CLK0_OUT => SYSTEM_CLK ); --************************** GSR <= '0';

--****connect output to microline pad************ ML_PIN_A1_PAD <= EMUL_SPADA_SIGNAL(0); ML_PIN_A2_PAD <= EMUL_SPADA_SIGNAL(1); ML_PIN_A3_PAD <= EMUL_SPADA_SIGNAL(2); ML_PIN_A4_PAD <= EMUL_SPADA_SIGNAL(3); ML_PIN_A5_PAD <= EMUL_SPADA_SIGNAL(4); ML_PIN_A6_PAD <= EMUL_SPADA_SIGNAL(5); ML_PIN_A7_PAD <= EMUL_SPADA_SIGNAL(6); ML_PIN_A8_PAD <= EMUL_SPADA_SIGNAL(7); ML_PIN_A9_PAD <= EMUL_SPADA_SIGNAL(8); ML_PIN_A10_PAD <= EMUL_SPADA_SIGNAL(9); ML_PIN_A11_PAD <= EMUL_SPADA_SIGNAL(10); ML_PIN_A12_PAD <= EMUL_SPADA_SIGNAL(11); ML_PIN_A13_PAD <= EMUL_SPADA_SIGNAL(12); ML_PIN_A14_PAD <= EMUL_SPADA_SIGNAL(13); ML_PIN_A15_PAD <= EMUL_SPADA_SIGNAL(14); ML_PIN_A16_PAD <= EMUL_SPADA_SIGNAL(15); ML_PIN_A17_PAD <= EMUL_SPADA_SIGNAL(16); ML_PIN_A18_PAD <= EMUL_SPADA_SIGNAL(17); ML_PIN_A19_PAD <= EMUL_SPADA_SIGNAL(18); ML_PIN_A20_PAD <= EMUL_SPADA_SIGNAL(19); ML_PIN_A21_PAD <= EMUL_SPADA_SIGNAL(20); ML_PIN_A22_PAD <= EMUL_SPADA_SIGNAL(21); ML_PIN_A23_PAD <= EMUL_SPADA_SIGNAL(22); ML_PIN_A24_PAD <= EMUL_SPADA_SIGNAL(23); ML_PIN_A25_PAD <= EMUL_SPADA_SIGNAL(24); ML_PIN_A26_PAD <= EMUL_SPADA_SIGNAL(25); ML_PIN_A27_PAD <= EMUL_SPADA_SIGNAL(26); ML_PIN_A28_PAD <= EMUL_SPADA_SIGNAL(27); ML_PIN_A29_PAD <= EMUL_SPADA_SIGNAL(28); ML_PIN_A30_PAD <= EMUL_SPADA_SIGNAL(29);

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ML_PIN_C1_PAD <= EMUL_SPADA_SIGNAL(30); ML_PIN_C2_PAD <= EMUL_SPADA_SIGNAL(31); ML_PIN_C3_PAD <= EMUL_SPADA_SIGNAL(32); ML_PIN_C4_PAD <= EMUL_SPADA_SIGNAL(33); ML_PIN_C5_PAD <= EMUL_SPADA_SIGNAL(34); ML_PIN_C6_PAD <= EMUL_SPADA_SIGNAL(35); ML_PIN_C7_PAD <= EMUL_SPADA_SIGNAL(36); ML_PIN_C8_PAD <= EMUL_SPADA_SIGNAL(37); ML_PIN_C9_PAD <= EMUL_SPADA_SIGNAL(38); ML_PIN_C10_PAD <= EMUL_SPADA_SIGNAL(39); ML_PIN_C11_PAD <= EMUL_SPADA_SIGNAL(40); ML_PIN_C12_PAD <= EMUL_SPADA_SIGNAL(41); ML_PIN_C13_PAD <= EMUL_SPADA_SIGNAL(42); ML_PIN_C14_PAD <= EMUL_SPADA_SIGNAL(43); ML_PIN_C15_PAD <= EMUL_SPADA_SIGNAL(44); ML_PIN_C16_PAD <= EMUL_SPADA_SIGNAL(45); ML_PIN_C17_PAD <= EMUL_SPADA_SIGNAL(46); ML_PIN_C18_PAD <= EMUL_SPADA_SIGNAL(47); ML_PIN_C19_PAD <= EMUL_SPADA_SIGNAL(48); ML_PIN_C20_PAD <= EMUL_SPADA_SIGNAL(49); ML_PIN_C21_PAD <= EMUL_SPADA_SIGNAL(50); ML_PIN_C22_PAD <= EMUL_SPADA_SIGNAL(51); ML_PIN_C23_PAD <= EMUL_SPADA_SIGNAL(52); ML_PIN_C24_PAD <= EMUL_SPADA_SIGNAL(53); ML_PIN_C25_PAD <= EMUL_SPADA_SIGNAL(54); ML_PIN_C26_PAD <= EMUL_SPADA_SIGNAL(55); ML_PIN_C27_PAD <= EMUL_SPADA_SIGNAL(56); ML_PIN_C28_PAD <= EMUL_SPADA_SIGNAL(57); ML_PIN_C29_PAD <= EMUL_SPADA_SIGNAL(58); ML_PIN_C30_PAD <= EMUL_SPADA_SIGNAL(59); end architecture behaviour;

clock_manager.vhd

-- Module clock_manager library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- synopsys translate_off Library UNISIM; use UNISIM.Vcomponents.all;

(21)

-- synopsys translate_on entity clock_manager is port (

RST_IN : in std_logic; CLKIN_IN : in std_logic; LOCKED_OUT : out std_logic; CLK0_OUT : out std_logic); end clock_manager;

architecture STRUCT of clock_manager is signal CLKIN_IBUFG : std_logic; signal CLKFB_IN : std_logic; signal CLK0_BUF : std_logic; signal CLKDV_BUF : std_logic; signal GND : std_logic;

component DCM generic(

DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE; CLKIN_DIVIDE_BY_2 : boolean := FALSE;

CLK_FEEDBACK : string := "1X";

CLKOUT_PHASE_SHIFT : string := "NONE"; DSS_MODE : string := "NONE";

FACTORY_JF : bit_vector := X"C080"; STARTUP_WAIT : boolean := false; PHASE_SHIFT : integer := 0; CLKFX_MULTIPLY : integer := 4; CLKFX_DIVIDE : integer := 1; CLKDV_DIVIDE : real := 2.0; CLKIN_PERIOD : real := 0.0;

DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS" ); port ( CLKIN : in std_logic; CLKFB : in std_logic; RST : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSCLK : in std_logic; DSSEN : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic;

(22)

CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic;

STATUS : out std_logic_vector (7 downto 0); LOCKED : out std_logic;

PSDONE : out std_logic ); end component; component IBUFG port ( I : in std_logic; O : out std_logic ); end component; component BUFG port ( I : in std_logic; O : out std_logic ); end component; begin DCM_INST : DCM Generic map ( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 11.1111, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map ( CLKIN => CLKIN_IBUFG, CLKFB => CLKFB_IN, RST => RST_IN, PSEN => GND, PSINCDEC => GND, PSCLK => GND,

(23)

DSSEN => GND, CLK0 => CLK0_BUF, CLKDV => CLKDV_BUF, LOCKED => LOCKED_OUT); CLKIN_IBUFG_INST : IBUFG port map ( I => CLKIN_IN, O => CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map ( I => CLK0_BUF, O => CLKFB_IN); CLK0_OUT <= CLKFB_IN; GND <= '0'; end STRUCT;

Emulator_core.vhd

--- -- Project : SPADA EMULATOR --- LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity emulator_core is port( EMUL_CLK : in std_logic; EMUL_RST : in std_logic;

EMUL_ADDR : in std_logic_vector(18 downto 0); --2MB EMUL_DATA_I : in std_logic_vector(31 downto 0);

EMUL_WR : in std_logic; --acts like a chip select EMUL_WR_STRBn : in std_logic;

EMUL_SIGNAL : out std_logic_vector(59 downto 0);

EMUL_GREENn_LED: out std_logic;

EMUL_REDn_LED : out std_logic;

EMUL_DATA_O : out std_logic_vector(31 downto 0);

(24)

EMUL_RD_STRBn : in std_logic );

end entity;

architecture behavioural of emulator_core is

type std_logic_vector_32_matrix is array (natural range <>) of std_logic_vector(31 downto 0);

signal CLK : std_logic;

signal RST : std_logic;

signal ADDR : std_logic_vector(18 downto 0); signal DATA_I : std_logic_vector(31 downto 0);

signal WR_I : std_logic;

signal WRSTRBn_I : std_logic;

signal SPADA_SIGNAL: std_logic_vector(29 downto 0); signal GREEN_LED_n : std_logic;

signal RED_LED_n : std_logic; signal RDSTRBn_I : std_logic; signal RD_I : std_logic;

signal DATA_O : std_logic_vector(31 downto 0); signal WRITE_VALID_DFF : std_logic ;

signal WR_VAL_DFF_RST : std_logic ; signal CFG_REG_LOAD: std_logic; signal LOAD_NEW_PERIOD: std_logic;

signal CFG_REG_MATRIX : std_logic_vector_32_matrix ( 29 downto 0 ) ; signal CFG_REG_MATRIX_FF : std_logic_vector_32_matrix ( 29 downto 0 ) ;

signal CFG_REG: std_logic_vector( 31 downto 0 ); signal CFG_REG_FF: std_logic_vector(31 downto 0 ); signal CFG_REG_SEL: std_logic_vector(1 downto 0 ); signal CFG_REG_SEL_FF: std_logic_vector(1 downto 0 ); signal CFG_REG_EN : std_logic_vector(31 downto 0); signal CFG_REG_EN_FF : std_logic_vector(31 downto 0); signal SEL : std_logic_vector(1 downto 0);

signal EN : std_logic_vector(29 downto 0);

--******************component declaration*************************

component spad is

port ( clk : in std_logic ; reset : in std_logic;

(25)

en : in std_logic ;

sel : in std_logic_vector(1 downto 0) ;

sp_word_in : in std_logic_vector (31 downto 0); wave : out std_logic );

end component ;

component write_valid is port( CLK : in std_logic;

RST : in std_logic;

WV_VALID_BIT: in std_logic;

WV_CLEAR_VALID_BIT: out std_logic; WV_DATA_ENABLE : out std_logic

);

end component;

--********************************************************* begin

--**** connecting pins with internal signals **************

CLK <= EMUL_CLK; RST <= EMUL_RST; ADDR <= EMUL_ADDR; DATA_I <= EMUL_DATA_I; WR_I <= EMUL_WR; WRSTRBn_I <= EMUL_WR_STRBn; RD_I <= EMUL_RD; RDSTRBn_I <= EMUL_RD_STRBn; EMUL_DATA_O <= DATA_O;

EMUL_SIGNAL ( 59 downto 30) <= SPADA_SIGNAL ;

EMUL_SIGNAL ( 29 downto 0) <= SPADA_SIGNAL ; --************* connecting leds signals ********************

EMUL_GREENn_LED <= GREEN_LED_n ; EMUL_REDn_LED <= RED_LED_n ;

RED_LED_n <= not CFG_REG_FF(1);

GREEN_LED_n <= not CFG_REG_FF(0);

--****************register write process*********************** register_write : process(RST, WRSTRBn_I, WR_VAL_DFF_RST) begin

(26)

CFG_REG <= x"00000000"; CFG_REG_SEL <= "11"; CFG_REG_EN <= x"FFFFFFFF"; for i in 0 to 29 loop CFG_REG_MATRIX (i) <= x"FFFFFFFF"; end loop ; WRITE_VALID_DFF <= '0';

elsif (WR_VAL_DFF_RST ='1') then

CFG_REG <= CFG_REG;

CFG_REG_SEL <= CFG_REG_SEL ;

CFG_REG_EN <= CFG_REG_EN ;

CFG_REG_MATRIX <= CFG_REG_MATRIX ;

WRITE_VALID_DFF <= '0'; elsif (rising_edge(WRSTRBn_I)) then

if (WR_I = '1') then case ADDR is when "0000000000000000000" => CFG_REG <= DATA_I ; when "0000000000000000001" => CFG_REG_MATRIX(0) <= DATA_I ; when "0000000000000000010" => CFG_REG_MATRIX(1) <= DATA_I ; when "0000000000000000011" => CFG_REG_MATRIX(2) <= DATA_I ; when "0000000000000000100" => CFG_REG_MATRIX(3) <= DATA_I ; when "0000000000000000101" => CFG_REG_MATRIX(4) <= DATA_I; when "0000000000000000110" => CFG_REG_MATRIX(5) <= DATA_I ; when "0000000000000000111" => CFG_REG_MATRIX(6) <= DATA_I ; when "0000000000000001000" => CFG_REG_MATRIX(7) <= DATA_I ; when "0000000000000001001" => CFG_REG_MATRIX(8) <= DATA_I ; when "0000000000000001010" => CFG_REG_MATRIX(9) <= DATA_I ; when "0000000000000001011" => CFG_REG_MATRIX(10) <= DATA_I ; when "0000000000000001100" => CFG_REG_MATRIX(11) <= DATA_I ; when "0000000000000001101" => CFG_REG_MATRIX(12) <= DATA_I ; when "0000000000000001110" => CFG_REG_MATRIX(13) <= DATA_I ; when "0000000000000001111" =>

(27)

CFG_REG_MATRIX(14) <= DATA_I ; when "0000000000000010000" => CFG_REG_MATRIX(15) <= DATA_I ; when "0000000000000010001" => CFG_REG_MATRIX(16) <= DATA_I ; when "0000000000000010010" => CFG_REG_MATRIX(17) <= DATA_I ; when "0000000000000010011" => CFG_REG_MATRIX(18) <= DATA_I ; when "0000000000000010100" => CFG_REG_MATRIX(19) <= DATA_I ; when "0000000000000010101" => CFG_REG_MATRIX(20) <= DATA_I ; when "0000000000000010110" => CFG_REG_MATRIX(21) <= DATA_I ; when "0000000000000010111" => CFG_REG_MATRIX(22) <= DATA_I ; when "0000000000000011000" => CFG_REG_MATRIX(23) <= DATA_I ; when "0000000000000011001" => CFG_REG_MATRIX(24) <= DATA_I ; when "0000000000000011010" => CFG_REG_MATRIX(25) <= DATA_I ; when "0000000000000011011" => CFG_REG_MATRIX(26) <= DATA_I ; when "0000000000000011100" => CFG_REG_MATRIX(27) <= DATA_I ; when "0000000000000011101" => CFG_REG_MATRIX(28) <= DATA_I ; when "0000000000000011110" => CFG_REG_MATRIX(29) <= DATA_I ; when "0000000000000011111" => CFG_REG_EN <= DATA_I ; when "0000000000000100000" =>

CFG_REG_SEL(1 downto 0) <= DATA_I (1 downto 0) ;

when "0000000000000111101" =>

WRITE_VALID_DFF <= DATA_I(0);

when others => null;

end case;

end if;

end process;

(28)

--**************load configuration register*****************

cfg_reg_load_process : process(EMUL_CLK, CFG_REG_LOAD, RST) begin if (RST ='1') then CFG_REG_FF <= x"FFFFFFFF"; CFG_REG_SEL_FF <="11"; CFG_REG_EN_FF <= x"FFFFFFFF"; for i in 0 to 29 loop CFG_REG_MATRIX_FF(i) <= x"FFFFFFFF"; end loop ; elsif(rising_edge(EMUL_CLK)) then if (CFG_REG_LOAD = '1') then CFG_REG_MATRIX_FF <= CFG_REG_MATRIX; CFG_REG_FF <= CFG_REG ; CFG_REG_SEL_FF <= CFG_REG_SEL ; CFG_REG_EN_FF <= CFG_REG_EN ; else CFG_REG_MATRIX_FF <= CFG_REG_MATRIX_FF; CFG_REG_FF <= CFG_REG_FF ; CFG_REG_SEL_FF <= CFG_REG_SEL_FF ; CFG_REG_EN_FF <= CFG_REG_EN_FF; end if; end if; end process; --**************************************************** SEL <= CFG_REG_SEL_FF; EN <= CFG_REG_EN_FF(29 DOWNTO 0); --*************** register read process ****************-- register_read : process(RDSTRBn_I) begin if (falling_edge(RDSTRBn_I)) then if(RD_I = '1') then case ADDR is when "0000000000000000000" =>

DATA_O(31 downto 0) <= CFG_REG_FF ;

when "0000000000000000001" =>

DATA_O(31 downto 0) <= CFG_REG_MATRIX_FF(0) ;

when "0000000000000000010" =>

when "0000000000000000011" =>

when "0000000000000000100" =>

(29)

when "0000000000000000101" =>

DATA_O(31 downto 0) <= CFG_REG_MATRIX_FF(4);

when "0000000000000000110" =>

when "0000000000000000111" =>

DATA_O(31 downto 0) <= CFG_REG_MATRIX_FF (6) ; when "0000000000000001000" =>

DATA_O(31 downto 0) <= CFG_REG_MATRIX_FF (10) ;

when "0000000000000001100" =>

when "0000000000000001101" =>

when "0000000000000001110" =>

when "0000000000000001111" =>

when "0000000000000010000" =>

when "0000000000000010001" =>

when "0000000000000010010" =>

when "0000000000000010011" =>

when "0000000000000010100" =>

when "0000000000000010101" =>

when "0000000000000010110" =>

when "0000000000000010111" =>

when "0000000000000011000" =>

when "0000000000000011001" =>

when "0000000000000011010" =>

when "0000000000000011011" =>

(30)

when "0000000000000011110" =>

when "0000000000000011111" =>

DATA_O(1 downto 0) <= CFG_REG_SEL_FF ;

DATA_O(31 downto 2) <= (others => '0'); when "0000000000000100000" =>

DATA_O(31 downto 0) <= CFG_REG_EN_FF ; when others => null;

end case; end if; end if; end process; --*****************write_valid_machine instance***************** write_data_validation: write_valid port map ( CLK => CLK, RST => RST, WV_VALID_BIT => WRITE_VALID_DFF, WV_CLEAR_VALID_BIT=>WR_VAL_DFF_RST, WV_DATA_ENABLE => CFG_REG_LOAD );

--**************spad module instance************************ spad_inst_gen : for i in 0 to 29 generate

U0: spad port map (clk => CLK ,

reset => RST , en => EN(i), sel => SEL , sp_word_in=> CFG_REG_MATRIX_FF(i), wave => SPADA_SIGNAL(i) ); end generate; end behavioural;

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Write_valid.vhd

--Write_Valid_Machine module--- library ieee; use ieee.std_logic_1164.all; entity write_valid is port( CLK : in std_logic; RST : in std_logic; WV_VALID_BIT: in std_logic;

WV_CLEAR_VALID_BIT: out std_logic; WV_DATA_ENABLE : out std_logic

);

end entity;

architecture behavioural of write_valid is

type state_type is (W4_VALID,W4_VALID2,W4_VALID3, ENABLE_DATA); signal CURRENT_STATE : state_type;

signal NEXT_STATE : state_type; begin

next_state_process: process(CLK, RST) begin

if(RST = '1') then

CURRENT_STATE <= W4_VALID; elsif (rising_edge (CLK)) then

CURRENT_STATE <= NEXT_STATE; end if;

end process;

process (CURRENT_STATE, WV_VALID_BIT) begin case CURRENT_STATE is when W4_VALID => WV_CLEAR_VALID_BIT <= '0'; WV_DATA_ENABLE <= '0'; if (WV_VALID_BIT = '1') then NEXT_STATE <= W4_VALID2; else NEXT_STATE <= W4_VALID; end if; when W4_VALID2 => WV_CLEAR_VALID_BIT <= '0';

(32)

WV_DATA_ENABLE <= '0'; if(WV_VALID_BIT = '1') then NEXT_STATE <= W4_VALID3; else NEXT_STATE <= W4_VALID; end if; when W4_VALID3 => WV_CLEAR_VALID_BIT <= '0'; WV_DATA_ENABLE <= '0'; if(WV_VALID_BIT = '1') then NEXT_STATE <= ENABLE_DATA; else NEXT_STATE <= W4_VALID; end if; when ENABLE_DATA => WV_CLEAR_VALID_BIT <= '1'; WV_DATA_ENABLE <= '1'; NEXT_STATE <=W4_VALID; when others => NEXT_STATE <= W4_VALID; end case; end process; end architecture;

Spad.vhd

--Spad module--- LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity spad is port ( clk : in std_logic ; reset : in std_logic; en : in std_logic ;

sel : in std_logic_vector(1 downto 0) ;

sp_word_in : in std_logic_vector (31 downto 0); wave : out std_logic );

(33)

end entity;

architecture behav of spad is signal ena : std_logic;

signal word : std_logic_vector( 23 downto 0); signal gen_wave : std_logic ;

signal aux_wave : std_logic ; component modul1 is

sel_in : in std_logic_vector(1 downto 0) ; word_in : in std_logic_vector(31 downto 0 ); en_int : in std_logic;

data_out : out std_logic_vector( 23 downto 0 )); end component;

component single_count is port ( clk : in std_logic;

sel_in : in std_logic_vector(1 downto 0);

word_in : in std_logic_vector ( 23 downto 0);

reset : in std_logic;

rco : out std_logic );

end component ;

component monostable is port ( clk : in std_logic;

rst : in std_logic ; trigger : in std_logic ; pulse : out std_logic ); end component ;

begin

modul1_inst : modul1 port map ( clk => clk,

reset => reset,

sel_in => sel ,

word_in => sp_word_in,

en_int => ena,

data_out => word );

single_count_inst : single_count port map ( clk => clk ,

reset => reset ,

word_in => word ,

sel_in => sel ,

(34)

monostable_inst : monostable port map ( clk => clk , rst => reset,

trigger => ena ,

pulse => gen_wave );

--************* enable process ************************* process ( clk , reset, gen_wave )

begin

if ( reset = '1' ) then aux_wave <= '0';

elsif ( clk' event and clk ='1') then if ( en = '0' ) then aux_wave <= '0'; elsif ( en = '1') then aux_wave <= gen_wave ; else aux_wave <= aux_wave; end if; end if; end process; wave <= aux_wave ; end behav;

modul1.vhd

--Modul1 module LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity modul1 is port ( clk : in std_logic ; reset : in std_logic;

sel_in : in std_logic_vector(1 downto 0) ; word_in : in std_logic_vector(31 downto 0 ); en_int : in std_logic;

(35)

data_out : out std_logic_vector( 23 downto 0 )); end entity ;

architecture behav of modul1 is signal en_load_gen : std_logic ; signal en_prbs_gen : std_logic ; component en_assign is

en_sel : in std_logic_vector( 1 downto 0) ; en_count : in std_logic;

en_load : out std_logic; en_prbs : out std_logic); end component ;

component shift_reg2 is port ( clk : in std_logic; reset : in std_logic;

word_cfg_reg : in std_logic_vector ( 23 downto 0); cfg_reg : in std_logic_vector ( 7 downto 0);

en_load : in std_logic; en_prbs : in std_logic ;

sel : in std_logic_vector (1 downto 0);

data_out : out std_logic_vector( 23 downto 0)); end component;

begin

shf_reg_inst : shift_reg2 port map ( clk => clk ,

reset => reset ,

word_cfg_reg => word_in ( 23 downto 0),

cfg_reg => word_in ( 31 downto 24),

en_load => en_load_gen ,

en_prbs => en_prbs_gen ,

sel => sel_in ,

data_out => data_out );

en_assign_inst : en_assign port map ( clk => clk ,

reset => reset , en_sel => sel_in , en_count => en_int , en_load => en_load_gen , en_prbs => en_prbs_gen ); end behav ;

(36)

single_count.vhd

LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity single_count is port ( clk : in std_logic;

sel_in : in std_logic_vector(1 downto 0);

word_in : in std_logic_vector ( 23 downto 0);

rco : out std_logic); end single_count ;

architecture behav of single_count is signal load : std_logic ;

signal overf : std_logic ;

signal word_out : std_logic_vector(23 downto 0); signal en_count : std_logic ;

component n_count is port(clk : in std_logic;

nc_word_in : in std_logic_vector (23 downto 0); nc_load : in std_logic;

ena_n : in std_logic ;

nc_data_out : out std_logic_vector(23 downto 0);

nc_rco : out std_logic); end component;

begin

en_count <= sel_in(0);

n_count_inst : n_count port map ( clk => clk ,

reset => reset ,

nc_load =>load ,

ena_n => en_count,

(37)

nc_data_out => word_out , nc_rco => overf ); load <= overf; rco <= overf; end behav ;

monostable.vhd

--monostable module LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity monostable is port ( clk : in std_logic; rst : in std_logic ; trigger : in std_logic ; pulse : out std_logic ); end monostable;

architecture behav of monostable is signal conteggio : integer range 0 to 5 ; signal dd : std_logic ;

begin

process ( clk , rst, trigger, conteggio ) begin

if ( rst='1') then

conteggio <= 0;

dd <= '0';

elsif ( trigger = '1' ) then

if ( clk' event and clk ='1' ) then

dd <= trigger ;

conteggio <= 0 ;

end if;

elsif ( clk' event and clk ='1' ) then

case conteggio is

(38)

conteggio <= conteggio + 1; dd <= dd; when 1 => conteggio <= conteggio + 1 ; dd <= dd ; when others => conteggio <= 0; dd <= '0' ; end case; end if; end process; pulse <= dd; end behav;

shift_reg2.vhd

--shift_reg2 module LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity shift_reg2 is port ( clk : in std_logic; reset : in std_logic;

word_cfg_reg : in std_logic_vector ( 23 downto 0); cfg_reg : in std_logic_vector ( 7 downto 0);

en_load : in std_logic; en_prbs : in std_logic ;

sel : in std_logic_vector ( 1 downto 0);

data_out : out std_logic_vector( 23 downto 0)); end entity;

(39)

signal reg : std_logic_vector( 23 downto 0); signal reg_new : std_logic_vector ( 23 downto 0); signal data_new : std_logic_vector ( 23 downto 0); signal cfg_reg_new : std_logic_vector ( 7 downto 0); begin

process ( clk , reset, reg_new , cfg_reg_new , en_prbs ) variable lfsr_tap : std_logic;

begin

if ( reset ='1') then

reg <= ( others => '1') ; reg_new <= ( others => '1') ; cfg_reg_new <= ( others => '1') ;

elsif ( clk'event and clk = '1') then if ( sel= "00" ) then

reg <= reg;

reg_new <= reg_new ; cfg_reg_new <= x"00" ;

elsif ( en_load = '1' ) then

reg <= word_cfg_reg ;

reg_new <= word_cfg_reg ;

cfg_reg_new <= cfg_reg ;

elsif ( en_prbs = '1' ) then

reg_new <= reg_new (22 downto 0) & lfsr_tap;

cfg_reg_new <= cfg_reg ;

end if;

lfsr_tap := reg_new(23) xor (reg_new(22) xor( reg_new (20) xor ( reg_new (19))));

case cfg_reg_new is when x"00" =>

data_new <= reg ; when x"01" =>

data_new <= reg ( 23 downto 1 )& reg_new(0);

when x"02" =>

data_new <= reg ( 23 downto 2 )& reg_new(1 downto 0);

when x"03" =>

when x"04" =>

(40)

when x"05" =>

when x"06" =>

when x"07" =>

when x"08" =>

when x"09" =>

when x"0A" =>

when x"0B" =>

when x"0C" =>

when x"0D" =>

when x"0E" =>

when x"0F" =>

when x"10" =>

when x"11" =>

when x"12" =>

when x"13" =>

when x"14" =>

(41)

when x"15" =>

data_new <= reg ( 23 downto 21 )& reg_new(20 downto 0); when others => data_new <= reg_new ; end case; end process ; data_out <= data_new ; end behav;

en_assign.vhd

--en_assign module LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity en_assign is port (clk : in std_logic ; reset : in std_logic ;

en_sel : in std_logic_vector( 1 downto 0) ; en_count : in std_logic;

en_load : out std_logic; en_prbs : out std_logic); end entity;

architecture behav of en_assign is begin

process ( en_count , en_sel , clk , reset ) begin

if ( reset='1') then

en_load <= '0';

(42)

elsif ( rising_edge (clk )) then case en_sel is when "00" => en_load <= '0'; en_prbs <= '0'; when "01" => en_load <= '1'; en_prbs <= '0'; when "10" => en_load <= '0'; en_prbs <= en_count; when others => null; end case; end if ; end process; end behav;

n_count.vhd

--n_count modul LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity n_count is port(clk : in std_logic;

nc_word_in : in std_logic_vector (23 downto 0); nc_load : in std_logic;

ena_n : in std_logic;

nc_data_out : out std_logic_vector(23 downto 0);

nc_rco : out std_logic); end n_count;

(43)

signal conteggio : std_logic_vector (23 downto 0):=x"FFFFFA"; begin process ( clk, reset) begin if ( reset = '1' ) then conteggio <= x"FFFFF0";

elsif ( clk' event and clk = '1' ) then if ( ena_n = '0') then

if ( nc_load = '1' ) then

conteggio <= nc_word_in;

elsif ( nc_load = '0' ) then

conteggio <= conteggio + 1 ;

else

conteggio <= conteggio;

end if;

if conteggio = x"FFFFFE" then nc_rco <= '1';

else nc_rco <= '0'; end if; end if; end if; end process; nc_data_out <= conteggio; end behav;