Software Defined Radio

Chapter 2

Software Defined Radio

2.1 SDR concept

Over the last ten years, the improvement of semiconductor technologies in performance capability and cost has led to the emergence of the Software Defined Radio (SDR) technology. SDR is defined as a collection of hardware and software technologies that enable reconfigurable system architectures for wireless networks and user terminals. SDR provides an efficient and inexpensive solution to the problem of building multi-mode, multi-band, multi-functional wireless devices that can be adapted, upgraded or enhanced by using software upgrades [7].

The SDR concept has been applied to the military market, in United States of America, through the Joint Tactical Radio System (JTRS) specification that provides inter-operability among different radio architectures for war-fighters. Further, the civilian radio market has seen an influx of radio technologies like GSM, GPRS, CDMA, UMTS, WiMAX, LTE, WLAN, and Bluetooth. A single radio needs to support these different wireless technologies concurrently that have different requirements for throughput and bandwidth [9][8].

Considering a simplistic overview of a radio system. A signal to be transmitted would be modulated, amplified and applied to an antenna. The radio wave would propagate

through the air, and a signal would be received at the receiving antenna. This received signal would be subjected to amplification, filtering, and demodulation.

A software-defined radio system would implement as many using general computing software processing.

behind the SDR concept is that the software should operate as close the antenna as possible and this software should run on a general purpose c

to move the radio engineering problem

domain. Obviously, the software domain provides a flexible and accessible solution Of course, realizing an ideal SDR sy

following:

1. The antennae should operate at carrier frequencies of all radio signals 2. The analog-to-digital and digital

RF stage avoiding aliasing. 3. Computers should be a

management for all radio signal

Figure 2

In reality, antennas must be designed for operation within a particular frequ modern analog-to-digital converters (ADCs) and digital

are not fast enough to process a large portion of the occupied spectrum, and current general purpose computers are still not sufficient to handle the real

through the air, and a signal would be received at the receiving antenna. This received signal would be subjected to amplification, filtering, and demodulation.

defined radio system would implement as many of these tasks

using general computing software processing. However, it is clear that the philosophy behind the SDR concept is that the software should operate as close the antenna as possible and this software should run on a general purpose computer. The SDR goal is the radio engineering problem from the hardware domain to the software domain. Obviously, the software domain provides a flexible and accessible solution Of course, realizing an ideal SDR system, means overcoming some obstacles as

The antennae should operate at carrier frequencies of all radio signals

digital and digital-to-analog converters should sample directly at RF stage avoiding aliasing.

Computers should be able to handle real time processing and protocol management for all radio signal

2.1 Block diagram for ideal SDR system

In reality, antennas must be designed for operation within a particular frequ

digital converters (ADCs) and digital-to-analog converters (DACs) are not fast enough to process a large portion of the occupied spectrum, and current general purpose computers are still not sufficient to handle the real-time

through the air, and a signal would be received at the receiving antenna. This received

of these tasks as possible However, it is clear that the philosophy behind the SDR concept is that the software should operate as close the antenna as omputer. The SDR goal is from the hardware domain to the software domain. Obviously, the software domain provides a flexible and accessible solution[7].

stem, means overcoming some obstacles as

The antennae should operate at carrier frequencies of all radio signals

analog converters should sample directly at

ble to handle real time processing and protocol

In reality, antennas must be designed for operation within a particular frequency band, analog converters (DACs) are not fast enough to process a large portion of the occupied spectrum, and current time throughput

required by many applications.

simple applications such as AM and FM radio. However, many applications of interest cannot yet be realized using this configuration.

A common SDR system is shown in

This configuration employ

front end. The FPGA performs the computat

common to all SDRs. Examples of such processing includes digital down/up and decimation/interpolation filtering.

significantly affect system flexibility because it types[10].

Among all the possible SDR platform, the GNURadio project together with USRP board offers a unique, reliable

Tha aim of GNURadio is

a collection of software modules to perform the main operations for signal processing. It is interesting to note that the GNURadio paradigm currently gathers a very active worldwide community of developers bu

GNURadio framework is split in two wide areas. The first one makes use of the C++ programming language, while the latter one exploits the flexibility provided by the Python scripting language. The USRP is a dev

project and produced by Ettus Research . As a consequence, it perfectly fits the GNURadio framework considered for the software section.

many applications. The SDR of Figure 2.1 has been realized for some simple applications such as AM and FM radio. However, many applications of interest

yet be realized using this configuration. SDR system is shown in Figure 2.2.

Figure 2.2 SDR system

This configuration employs a FPGA ( Field-Programmable Gate A

front end. The FPGA performs the computationally expensive signal processing that is common to all SDRs. Examples of such processing includes digital down/up

and decimation/interpolation filtering. The introduction of the FPGA does not significantly affect system flexibility because its functionality is common to all radio

Among all the possible SDR platform, the GNURadio project together with USRP reliable other than low cost solution.

GNURadio is to develop SDR terminals. In particular, this project provides a collection of software modules to perform the main operations for signal processing. It is interesting to note that the GNURadio paradigm currently gathers a very active worldwide community of developers building their projects upon this platform. The GNURadio framework is split in two wide areas. The first one makes use of the C++ programming language, while the latter one exploits the flexibility provided by the Python scripting language. The USRP is a device designed within the GNURadio project and produced by Ettus Research . As a consequence, it perfectly fits the GNURadio framework considered for the software section.

has been realized for some simple applications such as AM and FM radio. However, many applications of interest

Array ) and the RF-ionally expensive signal processing that is common to all SDRs. Examples of such processing includes digital down/up-conversion The introduction of the FPGA does not s functionality is common to all radio

Among all the possible SDR platform, the GNURadio project together with USRP

terminals. In particular, this project provides a collection of software modules to perform the main operations for signal processing. It is interesting to note that the GNURadio paradigm currently gathers a very active ilding their projects upon this platform. The GNURadio framework is split in two wide areas. The first one makes use of the C++ programming language, while the latter one exploits the flexibility provided by the ice designed within the GNURadio project and produced by Ettus Research . As a consequence, it perfectly fits the

2.2The USRP

This section will focus on the Universal Software Radio Peripheral (USRP), taking a simplified look at how it works. Its purpose is to provide a physical layer solution to a wide range of primarily telecommunications applications that require the ability to transmit or receive radio frequency signals.

The Universal Software Radio Peripheral (USRP) is a hardware device developed by Ettus Research LLC that enables general purpose computers to be used as a platform for software radio (Figure 2.3). It serves as a generic radio frontend by providing a digital baseband and IF section for the radio system.

The USRP is comprised of the motherboard, which hosts a FPGA for high speed signal processing, and interchangeable daughterboards that cover different frequency ranges. The average cost of the USRP motherboard and a single daughterboard is US$1000.00. A computer host can be connected to the USRP via USB 2.0.

Figure 2.3 USRP board

The Cypress FX2 chip manages the USB protocol. The computer will flash firmware onto the FX2 chip when the USB cable is plugged. This will initiate setup

communications with the host computer to determine the link type, and what link settings the connected device will require. The USB transfer rate for host-USRP connection is set up for 32MB/second [11].

On the USRP, digital signal processing is performed within the Altera Cyclone FPGA. The signal paths are completed by 4 ADCs and DACs which are integrated on the two AD9860 chips physically located beside the FPGA.

In the transmitting path, these chips contain a Hilbert filter, an interpolator (maximum factor of 4), and a digital mixer. The AD9860 performs 14 bit D/A conversion at 128 M samples/sec and has a programmable gain amplifier on the output.

In the receiving path, the AD9860s have buffers and programmable gain amplifiers on the inputs. The ADC sample rate is 64 M samples/sec , each sample has 12 bits resolution.

The AD9860 chips provide the USRP with two complex transmit channels and two complex receive channels. They provide a theoretical unambiguous transmitter bandwidth of 64 MHz and a receiver bandwidth of 32 MHz according to the Nyquist theorem. Their clocks are synchronized to the USRP 64 MHz crystal oscillator.

The daughterboards provide the RF front-end needed to mix signals down to frequencies the ADCs can sample without aliasing, or up to frequencies beyond what the DACs can produce[11].

The basic setup of the USRP is as follows:

• 4 DACs, 14 bit, 128 MSamples/sec, interpolators and quadrature mixers • 4 ADCs, 12bit, 64 MSamples/sec.

• FPGA based Cascaded Integrator Comb (CIC) filters to perform interpolation and decimation.

• Numerically Controlled Oscillator, based on an implementation of the CORDIC algorithm.

The USRP FPGA transfers 16 bit complex samples at variable rates. The USB link sup ports up to 32 MB/sec transfers. Thus, using 16 bit ( i.e. 2 byte ) for real sample and 1 complex channel ( i.e. 2 real channels ), the link supports 8 MHz bandwidth.

Furthermore, using 4 byte per complex sample and 2 channels, the link supports 4 MHz bandwidth. Sample size at USB link can be halved to 8 bit samples, allowing to double the supported bandwidth.

2.2.1.Receiver Chain

The following receiver daughterboards are available for the USRP:

• Basic Rx: it contains no special RF components or functionality. It serves the same debugging purpose as the transmitter variant and has 16 debug IO pins that can be used to monitor selected signals within the FPGA, or to inject a digital signal into it.

• DBSRX: This receiver board is made specifically to receive signals between 800 MHz and 2.4 GHz. As with the RFX range, it has I-Q demodulation, IF down-conversion and gain control.

The receiver chain (Figure 2.4) will be detailed in the next sections.

2.2.2.AD9860

The USRP receive chain begins at the AD9860.On the receive side these chips contain a Programmable Gain Amplifier which can provide a 20 dB gain. The ADC runs at 64 Msamples/sec and delivers 12 bit samples to the FPGA. There is one ADC dedicated to each channel, though the user can choose whether they are connected or not, via the multiplexer within the FPGA. The channels in this case are representative of either 4 real channels, or 2 complex channels[11].

Once the interleaved samples reach the FPGA, they are adjusted to signed 16 bit sample streams. The sampled signal goes to the digital down-conversion (DDC) in the Rx chain module. Signal mixing is done by using a numerically controlled oscillator (NCO). The a CORDIC algorithm is used to implement the NCO module to calculate and generate the local oscillator signals. The mixed signal is then applied to a CIC decimator to reduce the sample rate. The limiting factor is the bandwidth that the USB link can support. The reduced sample rate is then sent to the Rx buffer module. Here the samples are interleaved and packed into a buffer to be transferred to the computer. In this module, it is also possible to reduce the sample size.

By reducing the samples from 16 bits to 8 bits, the effective bandwidth that the USB link can support is increased. This increase comes at the cost of ADC dynamic range.