Performance evaluation of III-V compound semiconductor n-MOSFETs employing calibrated multi-valley and Multi-Subband Monte Carlo transport models

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UNIVERSITÁ DEGLI STUDI DI UDINE

Dottorato di Ricerca in Ingegneria Industriale e dell’Informazione

Dipartimento Politecnico di Ingegneria e Architettura

Enrico CARUSO

Performance evaluation of III-V compound semiconductor n-MOSFETs

employing calibrated multi-valley and Multi-Subband Monte Carlo transport

models

Advisor: External reviewers:

Prof. Pierpaolo PALESTRI

Prof. Quentin RAFHAY

Prof. Gaudenzio MENEGHESSO

Co-advisor

Prof. David ESSENI

Prof. Luca SELMI

Ph.D. Thesis

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Abstract

For the last few decades, Si CMOS technology has been driven by device scaling to increase performance, as well as reduce cost and maintain low power consumption. However, as de-vices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. A paradigm shift has been occurring in the industry, where materials innovation, rather than scaling, is becoming the primary enabler for performance enhancement in CMOS technology.

To improve the drive current high electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability.

A realistic modeling approach of modern devices should be able to take into account the most relevant technological options to save development, implementation time and costs.

In this context, the aim of this PhD thesis is to calibrate and validate a state of the art Multi-Subband Monte Carlo (MSMC) simulator and employ it to investigate the performance of III-V nMOSFET.

We first validate the band structure calculation method used in the MSMC simulator, which is a key ingredient for accurate electrostatics and transport models. We cross check dif-ferent band structure methods and provides useful parameter sets for an accurate description of III-V MOS band-structures in nanoscale Ultra Thin Body (UTB) MOSFET architectures, also in presence of strain. The scattering parameter of III-V semiconductor used in the models implemented in the MSMC simulator have been calibrated against experimental results: for phonon scattering we have used bulk velocity-field curves, while for surface roughness and Coulomb scattering we have used inversion layer mobility experiment.

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ii

for ultra-thin-films.

We evaluate the digital and analog figures of merit at two future technology nodes of ultra-scaled gate length taking into account all the main physical mechanism of the device, such as surface roughness, interface states and series resistances, understanding how these effects affect the MOSFET performance.

Strain engineering is an established technology booster for high-performance silicon MOS-FETs. For III-V semiconductors, however, very little data on strain-induced performance improvement is available. For this reason, we analyze the effect of different strain configura-tion on an ideal III-V MOSFET, finding that none of them significantly improve the intrinsic performance of these devices.

Moreover, we have analyzed also the case of compressively strained (111) GaAs UTB MOSFET, which enable the transport in L-valleys providing a viable solution to the “DoS bottleneck”. Unfortunately, the results show that L-valley-enhanced transport most likely will not yield the Ionand switching time improvements observed in simple ballistic

simula-tions, even if considering the ideal material properties and purely phonon scattering limited transport. In fact, the increased DoS and inversion charge at the virtual source provided by the L-valleys in the strained material is counterbalanced by an increased phonon scattering rate and reduced carrier velocity.

Finally, we extracted interface trap densities (Dit) in the oxide/III-V gate stacks fitting

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List of figures

1.1 Moore’s Law: CPU transistor count has increased by 2X and feature size has decreased by 0.7X every two years. The same figure also reports the trend for other important parameters for CPU and related with MOSFET scaling challenges: the clock speed/frequency ( fck), the total power (Pdyn+ Pstat)

and the instruction level parallelism (perf/clock). The image is taken from Reference [sutter2005]. . . 2 1.2 Factors that allowed scaling improvements in CMOS devices. This image

consider the case of p-MOS, but similar trends are found also for n-MOS. The image is taken from Reference [kuhn2010]. . . 2 1.3 TEM images of MOSFET scaling over the years. (Adapted from Intel) . . . 3 1.4 Trend of the power density due to the inability of scaling down the supply

voltage. Image is taken from [kursun2006]. . . 4 1.5 (Left) Limit of silicon MOSFET for scaling the supply voltage. (right)

Transfer characteristics of MOSFETs to illustrate the advantage of higher mobility materials. . . 4 1.6 Effective virtual source velocity (νin j(1−r)/(1+r)) in III-V HEMTs [DelAlamo2011].

At short LGthe velocity approaches νin j. Picture taken from [DelAlamo2011].

5

2.1 Sketch of a double gate MOSFET as described inside the MSMC simulator. The dashed lines indicate the section where the 1D Schrödinger equation is solved. . . 17 2.2 Flow-chart of a Multi-subband Monte Carlo simulator. . . 18 2.3 Sketch of the Brillouin zone with ellipsoidal isoenergy surfaces belonging

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List of figures vii

3.1 Left: Brillouin zone for the fcc lattice. Right: Sketch of band structure for silicon [Chelikowsky1974]. The figures are based on files from Wikimedia Commons. . . 39 3.2 Bulk band-structures of (a) GaAs, (b) InAs, (c) In0.53Ga0.47As along the

[100]-[110] directions (X-Γ-L). . . 46 3.3 (a): In-plane E − k for a 7 nm In0.53Ga0.47As quantum well. Quantization

is along the [001] direction and the in-plane plotting directions are [100] and [110]. The three subbands of the NP-EMA located on the right side of the chart originate from L-valleys, whereas the ones in the center are the subbands originating from the Γ valley. (b): Energy at the Γ point for the lowest three sub-bands. . . 47 3.4 (a): In-plane E − k for a 5 nm InAs quantum well. Quantization is along

the [001] direction, in-plane directions are [100] and [110]. The three subbands of the NP-EMA located on the right and left edges of the graph are associated to L and X valleys respectively, whereas the ones in the center are the subbands originating from the Γ valley. (b): Energy at the Γ point for the lowest three subbands. . . 48 3.5 (a): In-plane E − k for a 3 nm GaAs quantum well. Quantization is along

the [001] direction, in-plane directions are [100] and [110]. The subbands of the NP-EMA that are appearing on the right and left edges of the graph are associated to L and X valleys respectively, whereas the ones in the center are the subbands originating from the Γ valley. (b): Energy at the Γ point for the lowest three subbands. . . 49 3.6 In-plane E − k for a 3 nm (a), 5 nm (b) and 10 nm (c) In0.53Ga0.47As quantum

well. Quantization is along the [001] direction, in-plane directions are [100] and [110]. . . 49 3.7 Effective mass (extracted from the second derivative of the energy dispersion

of the lowest subband at the Γ point) vs. well thickness for GaAs (a), InAs (b) and InGaAs (c). . . 50 3.8 NP coefficient of the lowest subband α2Dof GaAs (a), InAs (b) and InGaAs

(c) as extracted from the 2D energy dispersion over an energy range of 0.5eV from the bottom. For a 7 nm quantum well of In0.53Ga0.47As, the NP

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List of figures viii

3.9 Energy of the first subband as a function of the well thickness for GaAs (a), InAs (b) and InGaAs (c) slabs. The energy reference (E = 0) is the minimum of the Γ valley in the bulk crystal. This means that we have shifted the E − k obtained with the various models by the same amount used to align them in the bulk case. . . 51 3.10 Group velocity of the first subband for GaAs (a), InAs (b) and InGaAs (c)

QW of various thickness. . . 52 3.11 Group velocity of the first subband for a 3nm (a), 5 nm (b) and 10 nm (c)

In0.53Ga0.47As quantum well. . . 52

3.12 Simulated and experimental energy gap for unstrained In0.53Ga0.47As (a) and

strained In0.72Ga0.28As (b) quantum well on Al2O3. . . 53

3.13 (a): Sketch of the simulated device. (b): Ballistic current vs. gate voltage at a source-drain voltage of 0.2 V. The work functions of the metal gate are adjusted in order to have a 100nA/µm off-current, according to the ITRS high performance specification. . . 54 3.14 (a): Current vs. gate voltage for VDS=0.2 V. (b): In-plane E − k for a 2.35

nm InAs quantum well, calculated with NP-EMA model using the bulk parameters of DFT, TB and k·p reported in Tab. 3.1. . . 55 3.15 (a): Current vs. gate voltage for VDS=0.5 V. (b): In-plane E − k for a 5 nm

In0.53Ga0.47As quantum well, calculated with the NP-EMA model using the

bulk parameters from DFT, TB and k·p methods reported in Tab. 3.3. (c): Sketch of the simulated device. . . 56 4.1 Sketch of the IBM MOSFET used for performing the C-V measurements. . 66 4.2 Dit profiles considered for simulating the experimental C-V curve.

Logarith-mic scales (left) and linear scales (right). The labels [BRA09] and [BUF16] refer to [BrammertzAPL2009] and [BuflerDRC2016], respectively. . . . 67 4.3 Comparison between the experimental C-V characteristics measured on IBM

devices and the simulated ones using the Dit profiles in Fig. 4.2. . . 68

4.4 Comparison between the experimental C-V characteristics as in Fig. 4.3 and the ones calculated using the Dit profiles extracted in this work (black curves). Curves report also the capacitance due to the modulation of the free charge NINV (turquoise line) and the modulation of both free and trapped

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List of figures ix

4.5 Comparison QSCV characteristics for a p-type In0.53Ga0.47As MOSCAP

using MSMC (circle) and Sentaurus (triangles) simulators. Closed symbols results are obtained solving the Schrödinger equation, and thus taking into account properly the quantization. . . 70 4.6 Comparison between TCAD simulations that solve the Schrödinger equation

(circle) and the MLDA model (square) for a p-type MOSCAP with Tox=5

nm (left) and a n-type MOSCAP with Tox=20 nm (right). . . 71

4.7 Multi-frequency C-V analysis for a p-type In0.53Ga0.47As MOSCAP with

Tox=12 nm and without traps. The carrier lifetime used in the simulator is

24.4 ps. . . 71 4.8 (Left) Energy distribution of border traps w.r.t. of the energy of the

con-duction band of In0.53Ga0.47As. (Right) Simulation quasi-static C-V and

multi-frequency C-V for a n-type In0.53Ga0.47As MOSCAP with Tox=12 nm.

Closed symbols are simulations with border traps, open symbols instead simulations without border traps. . . 72 4.9 (Top left) Dit profiles considered for simulating multi-frequency C-V curves.

(Top right) Multi-frequency C-V obtained using the Ditin (Top left) and using

for donor traps σ (el)=σ (hl)=1 × 10−15cm2. (Bottom left) As in (Top right) but using σ (el)=1 × 10−15 cm2 and σ (hl)=1 × 10−20cm2. (Bottom right) As in (Top right) but using σ (el)=1 × 10−10cm2and σ (hl)=1 × 10−20cm2. For all the simulation, we use for acceptor traps σ (el)=σ (hl)=1 × 10−15cm2. 74 4.10 (Top left) Dit profiles used for simulations. (Top right) Experimental

multi-frequency C-V taken from [OConnorJAP2011]. (Bottom left) Simulated multi-frequency C-V. (Bottom right) Simulated carrier concentration at the interface. In all the simulations, the energy of the Fermi level is reported in order to understand at a certain gate voltage which part of the Dit is explored. 76

4.11 (Top left) Dit profiles used for simulations. (Top right) Experimental

multi-frequency C-V taken from [OConnorAPL2011]. (Bottom left) Simulated multi-frequency C-V. (Bottom right) Simulated carrier concentration at the interface. In all the simulations, the energy of the Fermi level is reported in order to understand at a certain gate voltage which part of the Dit is explored. 77

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List of figures x

5.2 Simulated steady-state electron drift velocity versus electric field in bulk zincblende GaAs. Green dashed line is the result obtaining using the param-eter listed in Tab. 5.5 and 5.4 (with D_Γ−L= 1.8 · 1010eV/m). Red dash-dot line is the result obtained using the TB band parameter reported in Tab. 3.2 and the phonon parameter of Tab. 5.4 (with D_Γ−L= 1.8 · 1010 eV/m). Blue solid line simulation is obtained using the parameter of Tab. 5.3 and 5.4. The experiments are taken from [HoustonSSE1977, Ashida1974, Braslau1970, Ruch1968]. . . 87 5.3 Simulated steady-state electron drift velocity versus electric field in bulk

zincblende In0.53Ga0.47As. Red dashed line is the result obtaining using

the parameter listed in Tab. 5.8 and 5.7 (with U_alloy=0.83 eV). Blue solid line simulation is obtained using the parameter of Tab. 5.6 and 5.7. The experiments are taken from [Balynas1990]. . . 89 5.4 Simulated steady-state electron drift velocity versus electric field in bulk

zincblende GaSb. The experiments are taken from [Jantsch1971]. . . 90 5.5 Percentage occupation of different valleys as a function of the electric field

for GaAs. . . 91 5.6 (Left) Percentage occupation of different valleys and scattering rate as a

function of the electric field. (Right) Group velocity of Γ valley calculated as a function of the the electric field. . . 92 5.7 Comparison between the simulated steady-state electron drift velocity versus

electric field in bulk zincblende InAs, GaAs, In0.53Ga0.47As and GaSb. . . 93

5.8 (Left) Steady-state electron drift velocity versus electric field in bulk zincblende In0.53Ga0.47As simulated using the parameters of “MSMC: final

calibra-tion”and changing the alloy scattering potential U_alloy. (Right) Steady-state electron drift velocity versus electric field in bulk zincblende GaAs simu-lated using the parameters of “MSMC: final calibration”and changing the intervalley deformation potential Γ ↔ L valley D_Γ−L. Experimental result are taken from [Ruch1968] and [Balynas1990]. . . 94 5.9 Comparison between the low-field mobility measured on IBM devices and

the MSMC simulations using the Dit profile extracted from C-V data in Fig.

4.3 (black curves). The parameters used to fit the experimental curves are Nf ix=1.5x1013 cm−2, ∆rms=0.3 nm and Λ=1.5 nm. Notice that for the curve

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List of figures xi

6.1 Simulated steady-state electron drift velocity versus electric field in InAs DG MOSFETs with thickness (Tw) of 4 and 7 nm. (Top Left): simulations that

in-clude only phonon scattering. (Top Right): Simulations that inin-clude phonon scattering and surface roughness scattering without screening. (Bottom left): Simulations that include phonon scattering and surface roughness scattering (SR) with screening. (Bottom right) Effect of different models applied in the case with Tw=4 nm and NINV= 5 · 1012 cm−3. Bulk simulation is reported

for comparison. . . 102 6.2 Same as Fig. 6.1, but for GaAs. The only difference is (bottom right), where

we report the case with Tw=7 nm and NINV= 1 · 1012cm−3. . . 104

6.3 Same as Fig. 6.1, but for In0.53Ga0.47As. The only difference is (bottom

right), where we report the case with Tw=4 nm and NINV= 1 · 1012 cm−3. . 105

6.4 Schematic view of the double gate UTB In0.53Ga0.47As nMOSFETs in line

with the ITRS specifications for the “production year 2018”. . . 106 6.5 Ballistic IDS-VGS simulation for the device sketched in Fig. 6.4 using

VDS=0.63 V (left) and VDS=0.05 V (right) without considering the effect of

the series resistance. . . 107 6.6 Ballistic IDS-VGSsimulation for the device sketched in Fig. 6.4 for VDS=0.63

V comparing abrupt and smooth S/D doping profiles. Effect of series resis-tance is not considered. . . 108 6.7 Ballistic IDS-VGS simulation for the device sketched in Fig. 6.4 using

VDS=0.63 V (left) and VDS=0.05 V (right), comparing the case with and

without 131 Ωµm series resistances (65.5 Ωµm+65.5Ωµm), as per the ITRS specification. . . 108 6.8 IDS-VGS characteristics for the device sketched in Fig. 6.4 using VDS=0.63

V (left) and VDS=0.05 V (right). We compare ballistic simulations (blue

circles), simulation with phonon and alloy scattering (green squares), simu-lations with interface traps and all the scattering mechanism activated (red diamonds curves) and simulation with interface traps, all the scattering mech-anism activated and including the series resistance of RSD=131 Ωµm (65.5

Ωµ m+65.5 Ωµ m) (black triangles). . . 110 6.9 Schematic view of the double gate UTB In0.53Ga0.47As nMOSFETs in line

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List of figures xii

6.10 IDS-VGScharacteristics for the device sketched in Fig. 6.9 using VDS=0.59 V

(left) and VDS=0.05 V (right). We compare ballistic simulations (circles blue

curves), simulations with interface traps and all the scattering mechanism activated (red diamonds curves) and simulation with interface traps, all the scattering mechanism activated and including the series resistance of RSD=104 Ωµm (52 Ωµm+52 Ωµm) (black triangles). . . 111

6.11 Band gap at Γ point of GaAs (left) and InAs (right) for biaxial strain of −2% ≤ εxx≤ 2% (see Eq. 6.2) along the x=(100) and z=(010) crystal axes. 113

6.12 Biaxial strain in bulk GaAs. The x=(100) and z=(010) crystal axes are biaxially strained with −2% ≤ εxx ≤ 2%. (Top) Electron effective mass

along the [100] (left) and [001] (right) crystal axis. (bottom) Non-parabolicity factor α along the [100] (left) and [001] (right) crystal axis. All the curves are plotted against the biaxial strain component εxx (see Eq. 6.2). . . 114

6.13 Biaxial strain in bulk InAs. The x=(100) and z=(010) crystal axes are biaxially strained with −2% ≤ εxx≤ 2%. (Top) Electron effective mass along the [100]

(left) and [001] (right) crystal axis. (bottom) Non-parabolicity factor α along the [100] (left) and [001] (right) crystal axis. All the curves are plotted against the biaxial strain component εxx(see Eq. 6.2). . . 115

6.14 Band gap at Γ point of GaAs (left) and InAs (right) for uniaxial strain of −2% ≤ εxx≤ 2% (see Eq. 6.3) along the (110) crystal axis. . . 116

6.15 Uniaxial strain in bulk GaAs. The x=(110) crystal axis is uniaxially strained with −2% ≤ εxx≤ 2%. (left) Electron effective mass m∗ and (right)

non-parabolicity factor α along the [110] (top), [-110] middle and [001] (bottom) crystal axis. All the curves are plotted against the uniaxial strain component εxx(see Eq. 6.3). . . 117

6.16 Uniaxial strain in bulk InAs. The x=(110) crystal axis is uniaxially strained with −2% ≤ εxx≤ 2%. (left) Electron effective mass m∗ and (right)

non-parabolicity factor α along the [110] (top), [-110] middle and [001] (bottom) crystal axis. All the curves are plotted against the uniaxial strain component εxx(see Eq. 6.3). . . 118

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List of figures xiii

6.18 Ballistic simulations of IDS versus VGSat VDS=VDD=0.59 V for the

UTB-DG template device having LG=10.4 nm and InAs channel material. Left:

analysis of the biaxial strain condition; Right: analysis of the uniaxial strain condition. . . 121 6.19 IDSversus VGSat VDS=VDD=0.59 V for the UTB-DG template device having

LG=10.4 nm and InAs channel material and in the presence of uniaxial strain.

Left: same simulations as in Fig. 6.18 (right) but including phonon and surface roughness scattering. Right: ballistic simulations performed using the effective masses reported in Fig. 6.16 and corresponding to either tight-binding (TB), or k·p bandstructure calculations. . . 122 6.20 Sketch of the constant energy curves corresponding to L-valleys in Bulk

crystals (left) and inversion layers with (111) surface orientation (right). The figure also indicates the first Brillouin zone (truncated octahedron) of the 3D crystal and of the 2D gas in the inversion layer (hexagon). . . 123 6.21 Simulated ballistic current for a (111)/[¯110] GaAs MOSFET with Tw=4

nm and EOT=1.0 nm (open symbols) or EOT=0.5 nm (closed symbols) in logarithmic (left) or linear (right) scales. Triangles: model of this work; squares: ToB calculations from [kim2011]. . . 124 6.22 Schematic view of the double gate UTB (111) GaAs n-FETs considered to

analyze the effects of strain. . . 126 6.23 Energy difference between the lowest Γ subband and the lowest subband of

the L [111] (black) and L¯111 valleys (red, see Fig. 6.20, right) computed as a function of compressive stress by means of the MSMC model (open symbols) or from the TB simulations of [Alam2014] (closed symbols) for the device of Fig. 6.22 (Tw=5 nm). . . 127

6.24 IDS vs VGS characteristics for the relaxed and strained channel (111) GaAs

MOSFET of Fig. 6.22 (Tw=5 nm). Open symbols are results of ballistic

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List of figures xiv

6.25 (Left) ON-state current (VGS=VDS=0.6V) versus stress for the (111) GaAs

MOSFET of Fig. 6.22 (Tw=5 nm): ballistic currents simulated with NEGF

(squares) [Alam2014]. Open triangles show results from MSMC ballistic simulations and filled triangles are the corresponding simulation including phonon scattering. (Right) ON-state current enhancement (for VGS=0.6V

and VDS=0.6V) versus stress. The dashed line is a post-processing of the on

currents in [Alam2014] obtained by matching the threshold voltage rather than the off-current when applying strain. . . 129 6.26 Percentage contribution of the different valleys to the inversion sheet density

NINV at the virtual source as a function of compressive stress for the ballistic

case (open symbols) and including phonon scattering (filled symbols). (111) GaAs MOSFET of Fig. 6.22 (Tw=5 nm). VGS=0.60V and VDS=0.60V . . . 129

6.27 Simulated electron carrier density NINV (left) and velocity (right) along the

transport direction for the (111) GaAs MOSFET of Fig. 6.22 (Tw=5 nm).

Circles indicate ballistic results while triangles indicate simulations including phonon scattering. Closed symbols shows simulations for a relaxed channel device, while open symbols refer to the -2.5 GPa strained channel device. . 130 6.28 As in Fig. 6.25, but for the device sketched in Fig. 6.22 with Tw=7 nm

(green squares) and Tw=3 nm (blue triangles). . . 131

6.29 As in Fig. 6.26, but for the device sketched in Fig. 6.22 with Tw=7 nm

(green open symbols) and Tw=3 nm (blue closed symbols). . . 132

A.1 Comparison between Jin and k·p models for calculating the eigenvalues and wave-functions in a 3 nm quantum well with different potential shapes. Left: simulations using an ideal square barrier of 3.5 eV. Right: simulations using a realistic potential barrier taken from [AlianIEDM2013]. Simulation result with the parabolic approximation are also reported for completeness. . . . 144 B.1 Schematic representation of the trap wave function inside the oxide, showing

the distance to the interface, d, of a trap state positioned in z0and the side

of the cube, zT. The overlap between trap wave function (constant inside a

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List of tables

3.1 band-structure parameters for bulk InAs. . . 45

3.2 band-structure parameters for bulk GaAs. . . 46

3.3 band-structure parameters for bulk In0.53Ga0.47As. . . 46

5.1 NP-EMA parameters used for InAs in velocity-field simulations. . . 84

5.2 Phonon scattering parameters used for InAs in velocity-field simulations. . 84

5.3 NP-EMA parameters used for GaAs in bulk velocity-field simulations labeled in Fig. 5.2 as “MSMC: final calibration”. . . 86

5.4 Phonon scattering parameters used for GaAs in velocity-field simulations. . 86

5.5 NP-EMA parameters used for GaAs in bulk velocity-field simulations labeled in Fig. 5.2 as “MSMC: old calibration”. . . 87

5.6 NP-EMA parameters used for In0.53Ga0.47As in velocity-field simulations. 88 5.7 Phonon scattering parameters used for In0.53Ga0.47As in velocity-field simu-lations. . . 88

5.8 NP-EMA parameters used for In0.53Ga0.47Asin bulk velocity-field simula-tions labeled in Fig. 5.3 as “MSMC: old calibration”. . . 89

5.9 NP-EMA parameters used for GaSb in velocity-field simulations. . . 89

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Chapter 1 Introduction

1.1 On the Scaling Limits of Planar Si MOS Devices

The microelectronics revolution might best be characterized by the motto “smaller is better” [1]. A unique attribute of the silicon metal-oxide-semiconductor field-effect transistor (MOSFET), the workhorse of the industry, is that its performance for digital circuits improve as its dimensions are reduced. When it comes to logic operations, a transistor behaves as a switch, and its most relevant figures of merit, beside its footprint, are the switching speed and the switching energy. Because MOSFETs have decreased in size following a geometrical law, switching speed and transistor density have increased exponentially during the past decades, while switching energy has decreased in a similar fashion.

These “triple dividends” of MOSFET scaling have fueled the microelectronics revolution. Scaling has not only technological benefits, but also economical benefits of reducing cost per transistor through increased device density.

For these reasons the semiconductor industry has been faithfully following Moore’s Law [3], which states that the number of transistors doubles every two years (Figure 1.1). As a result the transistor size have been continuously reducing for the last 5 decades. The boost of the performance was mainly related to the reduction of the device size, which is a technology challenge does not require big device design efforts. In fact during the years, the end of the scaling was still supposed to be caused by technological issue: in the seventies, the lithography resolution seemed to be the main concern [4, 5]; while in the nineties, tunneling through the gate insulator, and the resulting high gate leakage and oxide breakdown, was thought to be the ultimate restriction [6, 7].

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1.1 On the Scaling Limits of Planar Si MOS Devices 2

Fig. 1.1 Moore’s Law: CPU transistor count has increased by 2X and feature size has decreased by 0.7X every two years. The same figure also reports the trend for other important parameters for CPU and related with MOSFET scaling challenges: the clock speed/frequency ( f_ck), the total power (P_dyn+ Pstat) and the instruction level parallelism (perf/clock). The

image is taken from Reference [2].

technology [9]. In fact in all subsequent generations, just shrinking the transistor does not improve the performance [10]. Anyway transistor scaling didn’t end at the 130 nm node, but it continued adding “technology boosters” [9] (see Figure 1.2).

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Going down to the 90 nm and 65 nm technology nodes, the SiO2thickness couldn’t be

further reduced since there were only few atomic layers left (1.2 nm) [11]. Gate leakage could be huge due to the tunneling current through this thin oxide. Strained silicon technology was then introduced to enhance mobility and keep the momentum of performance improvement. At the 45 nm technology node, high-k/metal gate were developed, which replaced the silicon oxide and poly silicon gate stack [12] to reduce the gate leakage. Recently, the FinFETs architecture was introduced for the 22 nm node [13, 14, 15], in order to keep the short channel effects under control (see Figure 1.3).

Fig. 1.3 TEM images of MOSFET scaling over the years. (Adapted from Intel)

Recently, MOSFET scaling entered a phase of “power-constrained scaling” [16, 17, 1]: power density cannot increase without incurring in substantial packaging and cooling costs that make these chips impractical for most applications (see Figure 1.4).

Power dissipation is given by the contribution of the dynamic power Pdyn= CG· ngate·

f_ck· V2

DD (where ngate is the average number of gate switching events in a clock period

(1/ fck)) and static power (Pstat= IOFF·VDD). Consequently, the VDD lowering is the most

effective way for power reduction. After a steady decrease of VDD from 5 V in the ’80s

to 1.2 V in 2002, we have seen a plateau close to 1 V till 2010. In recent years, a lot of efforts have been put into reducing VDD, however, for conventional MOSFETs, to reduce

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Fig. 1.4 Trend of the power density due to the inability of scaling down the supply voltage. Image is taken from [18].

Since, VDD is not scaled anymore, in order to maintain an acceptable power consumption,

the clock frequency fckof the CMOS circuits cannot longer increase (see Fig. 1.1), even if

the circuit delay could be reduced, limiting in this way the performance improvement that would be possible due to device scaling.

VDD scaling Vth scaling SS=60 mV/dec IOFF I'OFF

V

_GS

log I

_D ION VDD scaling SS=60 mV/dec IOFF

V

_GS

log I

_D ION

High mobility materials

Fig. 1.5 (Left) Limit of silicon MOSFET for scaling the supply voltage. (right) Transfer characteristics of MOSFETs to illustrate the advantage of higher mobility materials.

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1.2 III-V compounds: Benefits and Challenges 5

different materials and structures including carbon nanotubes, silicon nanowires, graphene, Ge and III-V compound semiconductors are being considered. These materials, in general, have significantly higher intrinsic (p or n) mobility than silicon, and they have the potential for enabling future high speed digital applications at very low supply voltages (see Figure 1.5 (right)). However, among all these non-Si materials, III-V and Ge are the most mature and practical due to their top-down processing [19, 20], and they can be a valid option for continuing the scaling predicted by the Moore’s law [21, 1].

1.2 III-V compounds: Benefits and Challenges

Today, III-V CMOS technology is atracting a big share of semiconductor research and recently the role of III-V as channel materials for nanosclale MOSFET have been recognized by the International Technology Roadmap for Semiconductors [22]. The main advantage of III-V over Si is their extraordinary intrinsic mobility and high injection velocity. In InGaAs or InAs, the electron mobility is more than 10 times higher than in silicon at a comparable sheet density [1] and the injection velocity is more than twice that of comparable silicon MOSFETs at less than half the voltage (see data for short LGin Figure 1.6).

Fig. 1.6 Effective virtual source velocity (νin j(1 − r)/(1 + r)) in III-V HEMTs [1]. At short

LGthe velocity approaches νin j. Picture taken from [1].

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1.2 III-V compounds: Benefits and Challenges 6

ION= W CG(VDD−Vth) νin j

1 − r

1 + r (1.1)

where W is the device width, νin j is the injection velocity defined as the average electron

velocity at the virtual source (VS, the position of the maximum of the potential energy barrier at the source/channel), CGis the gate capacitance and r is the back-scattering coefficient.

Since Ion is proportional to νin j (see Eq. 1.1), in principle III-V channel nMOSFETs can

achieve performance enhancement due to their higher velocity compared to Si (see Fig. 1.6). On the other hand, the same current as in silicon can be achieved at a lower applied voltage for III-V materials reducing dynamic power consumption for a fixed performance level [24]. These advantages can bring tremendous benefits in terms of circuit and system performance due to the improved power/performance tradeoff and make III-V compounds attractive for both High-Speed and Low-Power Logic applications [22]. Beside the high νin j, also the

back-scattering coefficient r is expected to be lower in III-V thanks to the high mobility. Although high velocity may suggest high current, the associated low effective mass may cause drawbacks. The first issue is the the small inversion capacitance from the intrinsic low density of states (DoS). Inversion capacitance is composed of two capacitances in series: oxide capacitance and semiconductor inversion layer capacitance [25]. In Silicon, the latter is larger, and the oxide capacitance is dominant. With low DoS materials, the inversion capacitance becomes smaller which decreases the inversion charge density, inducing a so called “DoS bottleneck” that partly neutralizes the benefits that III-V nMOSFETs can deliver in terms of ON-current [26, 27, 28, 29, 30, 31]. Secondly, when smaller effective mass materials are selected for higher mobility, the band gap drops accordingly. For example, the high mobility material InAs has band gap of only 0.354 eV. With smaller band gap, the band to band tunneling can be a limiting factor for off-state leakage current. Moreover, small effective masses pose severe limits on the gate scaling due to the large Source to Drain tunneling [32].

III-V MOSFETs need to overcome many technical challenges before they will become viable for future high speed and low power digital applications.

First, III-V materials lack of a high quality, natural insulator like that available for the SiO2/Si

materials system [24], which makes it difficult to move the Fermi level into the conduction band, signifcant “Fermi level pinning” takes place [33, 34, 35, 36].

Significant progresses have been made in the past two decades in solving these problems: Atomic layer deposition (ALD) has been introduced to III-V MOSFETs to apply high-κ dielectrics such as Al2O3, HfO2, ZrO2 or LaAlO3 with a reasonable interface trap density

(Dit) [37, 38]. Another issue related with the interface quality is the presence of bulk-oxide

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1.3 Thesis Outline 7

semiconductor substrate through tunneling. This gives rise to a wide range of time constants due to the spreading of traps through the dielectric and generates large C-V dispersions [40]. The trap states are undesired since they significantly deteriorate device performance. For example, with slow device switching: both trap states act as additional capacitances to be charged/discharged during the switching behavior. Such additional capacitances increase the total capacitance but do not contribute to the current, making it hard to modulate the surface potential inside semiconductor; therefore, the off state current (IOFF) becomes larger

and Ion becomes smaller. Despite some progress in recent years, the problem of forming a

high quality gate insulator remains a significant barrier to implementing III-V for CMOS applications.

Second, III-V substrates are expensive, brittle and difficult to make in large sizes [24]. Furthermore, from an economics point of view, the success of any future CMOS technology with non-Si channels will depend on its compatibility with the existing Si manufacturing infrastructure. Therefore, methods need to be developed to integrate III-V channels on Si substrates, which can be possibly achieved through either wafer bonding [41] or epitaxial growth [42, 43]. However, both methods are quite challenging due to large thermal and lattice mismatch, and the formation of anti-phase domains [1, 24].

Third, III-V materials do not have a superior hole mobility compared to Si. Nevertheless, as suggested by the ITRS an integration scheme is to utilize III-V for the nFET and Ge for the pFET due to the high hole mobility of Ge, making difficult the integration of different material on the same Si wafer. Last, the external resistance of III-V devices is still much larger than that of Si devices. It is necessary to improve the contact resistance and sheet resistance of III-V S/D region and develop self-aligned process for both S/D junction and contacts [1, 44, 38].

Although we are far away from solving all the issues, III-V compounds could become the key for continuing Moore’s law. In the last two years incredible improvement have been done in III-V MOSFETs [38]: record III-V MOSFETs on-current of ∼0.5 mA/µm at VDD=0.5 V

and with IOFF=100nA/µm are presented in [45, 46], record transconductance of 3.45 mS/µm

is shown in [47] while [48, 49] demonstrates that III-V MOSFETs can scale to the sub-10-nm technology nodes.

1.3 Thesis Outline

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Our study is particularly aimed to the reliable simulation of the “technology boosters” for III-V semiconductors. To achieve this goal, a systematic calibration of a Multi-Subband Monte Carlo simulator is done.

The main goals of this work are:

1. The determination of accurate band structure parameter sets to use in the MSMC to describe properly the multi valley dispersion relation of the III-V materials.

2. The calibration of the sophisticated scattering models through comparison between simulations and experimental results.

3. The exploration of different design options and the performance prediction for some template devices relevant for next technology nodes.

The manuscript is structured as follows:

Chapter 2 In this chapter, the theoretical background of the Multi-Subband Monte Carlo transport models is summarized and the modeling ingredient needed for accurate simulations are identified.

Chapter 3 Different band structure calculation models are presented and they have been cross-checked for bulk material and quantum-wells with thickness ranging from 3 nm to 10 nm. The consistency between the band structure parameter sets obtained using different methods is checked using the MSMC simulator for a technology relevant case of a few nm thick In0.53Ga0.47As MOSFET.

Chapter 4 Information of the interface trap distribution of a In_0.53Ga0.47As MOSFET

fab-ricated by IBM inside the framework of the E.U. project III-V-MOS are extracted by experimental C-V measurements, using the 1D Schrödinger solver of the MSMC simulator. Moreover, a deeper study of the interface traps and its dynamic parameters are performed comparing the multi-frequency C-V measurements with the simulation performed by the TCAD AC simulations using the commercial tool Sentaurus. Chapter 5 The parameters for the phonon scattering have been calibrated against bulk

velocity-field curves, while surface roughness and Coulomb scattering models have been calibrated comparing the inversion layer mobility of the IBM MOSFET of Chapter 4 taking into account also the effect of the interface states.

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the bulk case and which is the impact of the main scattering mechanism models. We then investigate, the impact of the series resistance and scattering mechanism for two technology nodes of Ultra-Thin Body (UTB) MOSFET. Finally, we investigate the impact of the strain on (100) UTB InAs and (111) UTB GaAs MOSFETs.

Chapter 7 The main conclusions of this Thesis are summarized.

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Chapter 2 The Multi-subband Monte Carlo Method

The equation at the base of semi-classical transport is the Boltzmann’s transport equation (BTE). The workhorse simulator of today’s Technology Computer Aided Design (TCAD) tools is the drift-diffusion model, which can be easily derived from BTE [1], assuming that electrons are in thermal equilibrium with the lattice. However, driven by Moore’s law, the dimensions of modern semiconductor devices have entered into the deca-nanometer regime, leading to quasi-ballistic transport. In this situation, the carrier energy distribution function is quite different from an equilibrium distribution and the models based on the moments of the BTE become inadequate [2], asking for the exact solution of the BTE.

In this regard, the Monte Carlo approach (MC) [3, 4] can solve exactly the BTE using a stochastic technique without a-priori assumptions on the carrier distribution function. Since the BTE is a semi-classical equation, it includes both classic Newton mechanics and the quantum mechanical scattering operator. Semi-classic transport models are thus only valid when quantum effects like source to drain tunneling or band to band tunneling play a negligible role [5, 6, 7]. In order to study such phenomena more complex models must be adopted. Numerical solutions of the Schrödinger equation using the Non-equilibrium Green Function method result in a highly accurate solution, however the computational effort would be huge and can only be achieved for small geometries. Moreover, the inclusion of scattering is very complicated and increases the already high computational requirements. Monte-Carlo methods are between the drift diffusion and full quantum methods in terms of both speed and accuracy. These methods can be used as purely semi-classical methods, but quantum corrections can be included [8, 9, 10].

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2.1 Introduction to the Multi-subband Monte Carlo Method 17

S

Ch

D

V

_G1

V

_G2

V

_S

_V

_D

y

x

z

Fig. 2.1 Sketch of a double gate MOSFET as described inside the MSMC simulator. The dashed lines indicate the section where the 1D Schrödinger equation is solved.

this method quite demanding from a computational point of view [14] but still much less demanding than the NEGF.

2.1 Introduction to the Multi-subband Monte Carlo Method

The solution of the BTE equation using the MSMC method is achieved by simulating the motion of sample particles in the phase space either one by one (single particle MSMC simulator) or as an ensemble. Electrons are considered as classical particles in the transport plane, whereas the Schrödinger equation described their distribution along the quantization direction. The simulation time is divided into a discrete set of intervals called time steps. Each time step is composed by two main phases. During the first one, called “free fligh”, the electric field move ballistically the particle according to the generalized Newton’s law. The second phase begins when a scattering event ends the free flight. Scattering events change the momentum of the particle and are stochastic in nature, while the free flight are deterministic.

Assuming translational invariance in the device width direction, the transport plane is reduced to x direction (see Fig. 2.1), which is partitioned into N sections. The simulator solves the transport problem in several iteration of the flowchart reported in Fig. 2.2. Each iteration is composed by different time steps and consists in four main steps: Schrödinger equation, Scattering rate computation, Monte Carlo transport and Poisson equation.

In each section, the Schrödinger equation is solved along the quantization direction y in order to obtain the subband energies Eν ,n(x) and the respective wave-functions ψν ,n(x, y).

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2.2 Solution of the 1D Schrödinger Equation 18 Poisson Equation (2D) Schrödinger Equation Monte Carlo (BTE) Scattering Theory of 2D el. gas Potential E_C(x,y) Electron Density n(x,y) Eigenstates ,n(x,y), E ,n(x) Scatering Rates

Fig. 2.2 Flow-chart of a Multi-subband Monte Carlo simulator.

calculated at the previous step. During the Monte Carlo transport, the particles are driven by an effective electric field calculated as Eν ,n/dx and the statistics are collected in order to

obtain the subband particle distributions for each section. The total charge density is then calculated. The new charge distribution is used to solve the 2D Poisson equation and obtain a new potential energy profile, to be used as input of the Schrödinger equation at the next iteration. These four steps are carried out in sequence until convergence is reached.

2.2 Solution of the 1D Schrödinger Equation

In the envelope-function method [15, 12], the corresponding stationary single band effective mass equation is:

h ˆ E_cb(ν)(−i∇R) + EC(y) i Φν ,n(R) = E ′ ν ,nΦν ,n(R) , (2.1)

where E_{ν ,n}′ and Φν ,n(R) are the eigenvalue and the envelope wave function of the n-th

subband of the valley ν. EC(y) is the confining potential energy profile. R = (r, ry) =

((rx, rz) , ry) and ˆE_cb(ν) is the operator that accounts for the effects of the crystal potential.

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2.2 Solution of the 1D Schrödinger Equation 19 −¯h 2 2 1 m_x ∂2 ∂ x2+ 1 m_y ∂2 ∂ y2+ 1 m_z ∂2 ∂ z2 + E_C(y) Φν ,n(R) = E ′ ν ,nΦν ,n(R) . (2.2)

Since the confining potential does not depend on the in-plane coordinates r = (rx, rz), we

make the ansatz for the form of the eigenfunction:

Φν ,n(R) = ξν ,n(y)

exp (ik · r) √

A , (2.3)

where k is the wave vector on the transport plane (k = (kx, kz)) and A is the normalization

area. Plugging 2.3 into 2.2, the Schrödinger equation can be simplified to:

− ¯h 2 2my ∂2ξν ,n ∂ y2 + EC(y) = ε P ν ,nξν ,n(y) . (2.4)

The total energy of the electrons in the inversion layer is given by:

E_{ν ,n}P (k) = Eν 0+ εν ,nP + ¯h2 2 k2_x m_x+ k2_y m_y ! , (2.5)

where Eν 0 is the conduction band minimum for the valley ν. The eigenvalues given by

2.5 are correct only for energies close to the conduction band valley minimum, which can be well represented by an ellipsoidal constant-energy surface. For higher energies or for material with highly non-parabolic band structure, as III-V semiconductors, a more accurate approximation is obtained by applying a non-parabolicity correction to the eigenvalues in Eq. 2.4 as described in [16]: ε_{ν ,n}NP= Uν ,n+ q 1 + 4αν· εν ,nP −Uν ,n − 1 2αν , (2.6)

where αν is the non-parabolicity coefficient for the valley ν and Uν ,nis given by:

U_{ν ,n}=

Z

|ξν ,n(y)| 2

E_C(y) dy, (2.7)

which represents the expectation value of the total potential energy for the subband n of the valley ν. Since ε_{ν ,n}NP depends on EC, which is calculated solving the Poisson equation each

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2.2 Solution of the 1D Schrödinger Equation 20 E_{ν ,n}NP(k) = Eν ,0+εν ,nNP+ r 1 + 4αν· ¯h2 2 k2 x mx+ k2 z mz + εν ,nP −Uν ,n −q1 + 4αν· εν ,nP −Uν ,n 2αν . (2.8) This method provide a correction for the eigenvalues, but the wave-functions are unchanged with respect to the parabolic case. In Appendix A is presented an analytical model, which has not been implemented inside the MSMC simulator, but that it can correct both the eigenvalues and the wave-functions.

Crystal orientation

The case considered above assumes that the three axis of the ellipsoidal constant energy surfaces are aligned with the three main axis of the device coordinate system DCS (x, y and z). This condition is verified for the ∆ valleys in a (001) silicon MOSFET with the channel oriented along the [100] crystal direction. However, in the general case of arbitrary material and crystal orientation this alignment may not be guaranteed. To treat these cases, a new coordinates system is defined whose with its main axes are always aligned with the axis of the ellipsoidal constant energy surfaces (ellipsoidal coordinate system, ECS). The main axes of the ECS are kt1, kt2, kland mt1, mt2, mlare the three corresponding effective masses. In

unstrained cubic semiconductors mt1=mt2=mt. A sketch of the different coordinate systems

is shown in Fig. 2.3, while a more complete treatment of the coordinate system definition can be found in [17]. The transformation between DCS and ECS is given by:

kt1, kl,, kt2

T

= RD→E· (kx, ky, kz)T, (2.9)

where RD→E is a transformation matrix from DCS to ECS. In order to solve the Schrödinger

equation, we need the matrix:    w₁₁ w₁₂ w₁₃ w₂₁ w₂₂ w₂₃ w₃₁ w₃₂ w₃₃   = R T D→E·    1/mt1 0 0 0 1/ml 0 0 0 1/mt2   · RD→E. (2.10)

Consistent with [18], the envelope wave-function for a generic orientation is then given by:

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2.3 Derivation of the Scattering Rates 21 ky kx kz y x z DCS CCS ECS kt1 kl kt2 n+ n+ p Source Gate Drain

Bulk

y

x z

DCS

Fig. 2.3 Sketch of the Brillouin zone with ellipsoidal isoenergy surfaces belonging to L-valleys and the corresponding coordinate systems: device coordinate system (DCS), crystal coordinate system (CCS) and ellipsoidal coordinate system (ECS).

−¯h 2_w 23 2 ∂2ξν ,n ∂ y2 + EC(y) = ε P ν ,nξν ,n, (2.12)

where the quantization mass is now 1/w23.

2.3 Derivation of the Scattering Rates

Perturbations of the Hamiltonian used to calculate the band structure of a physical system produce electronic transitions (collisions) between the available states. These perturbations have different nature and are referred as “scattering mechanisms”.

When a system is driven out of equilibrium by an external stimulus, such as the source to drain electric field responsible for the drain current in a MOSFET, the scattering mechanisms tend to restore the equilibrium.

Let us now suppose that the perturbation of the Hamiltonian of Eq. 2.2 is given by a stationary scattering potential USC(R) that allows transitions from an initial state (n, k) to a final state

(n, k′). Here the index n indicates both the valley and the subband. The semi-classical approach is based on the Fermi golden rule [12, p. 2.5.4] for the calculation of the scattering rates, that is the number of transitions between two states per unit of time:

S k, k′ = 2π ¯h M_n,n′ k, k′ 2 δEn(k) − En′ k′ . (2.13)

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2.3 Derivation of the Scattering Rates 22

the electron energy and can be represented by a time-dependent scattering potential USC(R,t).

In this case, applying the Fermi golden rule the scattering rates are:

S k, k′ = 2π ¯h M (ab) n,n′ k, k′ 2 δEn(k) − En′ k′ + ¯hω +2π ¯h M (em) n,n′ k, k′ 2 δEn(k) − En′ k′ − ¯hω . (2.14)

The equation shows that during an emission or absorption process the final energy lose or gain an energy ¯hω. This kind of scattering mechanism are called inelastic.

The matrix M of the equations denotes the scattering matrix element that is is given by [12, p. 4.1.2]: M_n,n′ k, k′ = (2π) 2 A Z y

ξn(y) ξn′(y)U2T(−q, y) dy, (2.15)

where A is the normalization area, q = (k′− k) is the wave-vector variation produced by the scattering and U2T is the Fourier transform of the scattering potential USC(R,t) with the

respect to the coordinates r = (rx, rz):

U_2T(−q, y) =

Z

A

U_SC(R) exp i k − k′ r dr. (2.16) If the matrix element has a weak dependence on q, the mechanism is called isotropic. The matrix element depend on the type of scattering, which means that Fermi’s Golden Rule will produce different transition rates for the different scattering mechanisms. In order to obtain an overall scattering rate Sn(k) out of the state (n, k) produced by a given scattering

mechanism, we need to sum the scattering rates over all the possible final states (n′, k′). This sum is typically converted to an integral over all final states k′:

S_n(k) =

_∑

n′,k′ S_n,n′ k, k′ ≈ (2π) 2 A nsp

∑

n′ Z k′Sn,n ′ k, k′ dk′. (2.17)

Since the spin is not changed by a scattering event, the spin multiplicity factor nspis set to 1.

2.3.1 Screening

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The matrix element of Eq. 2.15, that is the unscreened matrix element, is related with the screened matrix element by:

M_m,m(unscr)′ (q) =

∑

n,n′ εn,n ′ m,m′(q) M (scr) m,m′(q) , (2.18)

where ε_m,mn,n′′ is called dielectric function and is given by [12, p. 4.2.2]:

εn,n ′ m,m′(q) = δn,mδn′,m′− e2 q(εS+ εOX) Πn,n′(q) Fn,n ′ m,m′(q) , (2.19)

where q = |q|, εS is the dielectric constant of the semiconductor and εOX is the dielectric

constant of the oxide. Π is the polarization factor and is given by [12, p. 4.2.2]:

Πn,n′(q) = 1

A

∑

k

f_n′(k + q) − f_n(k)

E_n′(k + q) − E_n(k), (2.20)

where f is the occupation function of the subband. F is the screening form factor given by:

F_m,mn,n′′(q) =

Z

dyξm(y) ξm′(y)

Z

dy₀ξn(y0) ξn′(y0) φpcN(q, y, y0) , (2.21)

where φpcN is given by:

φpcN(q, y, y0) =

q(εS+ εOX)

e φpc(q, y, y0) (2.22) and φpc is the potential produced by a point charge. The formulations given is know

as tensorial screening. When q is small we can employ an easier expression known as scalar screening. When transitions involve different subbands (inter-subbands), the scalar formulation is:

M_m,m(scr)′(q) ≈ M

(scr)

m,m′(q) , m̸= m

′_. _(2.23)

For transitions between the same subband (intra-subbands), the scalar screening is:

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Scalar screening is useful in case of bulk and single-gate SOI devices because it is an excellent approximation, but it becomes inaccurate for double-gate SOI devices [19]. For all the simulations of this work we employ the tensorial screening, unless differently specified.

2.3.2 Non-Polar Phonon Scattering

Crystal with finite temperature has atoms that vibrate with respect to the equilibrium lattice position. These vibrations perturb the perfectly periodic crystal potential causing scattering of the carriers in the semiconductor. The energy associated to an oscillation mode ν with propagation wave-vector Q = |Q| is quantized and equal to E = ¯hων ,Q(nQ+ 1/2). This

energy can be interpreted as the total energy of a group of nQ particles, called phonons,

whose energy is ¯hων ,Q. Differently from electrons, phonons are Bosons and do not obey

Pauli’s exclusion principle, so the number of phonons occupying state (ν, Q) is given by the Bose-Einstein statistics: n_{ν ,Q}= 1 exp _¯hω ν ,Q KBT − 1 (2.26)

and it depends only on the phonon energy ¯hων ,Qand on the lattice temperature T .

Solids exhibit two types of phonons: acoustic phonons and optical phonons. Acoustic phonons are collective movements of atoms of the lattice out of their equilibrium positions, while optical phonons are movements of the atoms in the lattice such that one atom moving to the left, and its neighbor to the right. For the acoustic phonons, the matrix element associated to the phonon absorption and emission is given by [12, p. 4.6.3]:

M (ab) n,n′ k, k′ 2 = δ_k′ ,(k+q) KBT D2ac 2ρ A ν2 s F_n,n′ (2.27a) M (em) n,n′ k, k′ 2 = δ_k′ ,(k−q) K_BT D2_ac 2ρ A ν2 s F_n,n′, (2.27b)

where Dacis the effective deformation potential, νsis the sound velocity and F_n,n′ is the form

factor given by:

F_n,n′ = Z y ξ_n′(y) ξ_n(y) 2 dy. (2.28)

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2.3 Derivation of the Scattering Rates 25 S_n,n′ k, k′= 2π KBT D 2 ac ρ A¯h ν_s2 Fn,n ′_δ h En(k) − E k′i. (2.29)

In the case of optical phonons one can express the matrix element associated to the phonon absorption and emission as [12, p. 4.6.3]:

M (ab) n,n′ k, k′ 2 = δ_k′ ,(k+q) ¯h D2_op 2ω0ρ A F_n,n′n_op (2.30a) M (em) n,n′ k, k′ 2 = δ_k′ ,(k−q) ¯h D2_op 2ω0ρ A F_n,n′(n_op+ 1) , (2.30b)

where Dop is the optical deformation potential and ρ is the volumetric mass density. Finally,

the scattering rate is:

S n,n′ k, k′= π D 2 op ω0ρ F n,n′nopδ h E_n(k) − Ek′+ ¯hω0 i +π D 2 op ω0ρ F_n,n′(n_op+ 1) δ h E_n(k) − E k′ − ¯hω0 i . (2.31)

2.3.3 Coulomb Scattering

Charged sites produce a perturbation potential which can act as scatter fot the carriers in a semiconductor device. An examples of such electrically charged centers in an MOS transistor are the ionized dopants and the fixed charges either in localized states at the semiconductor-dielectric interface or in the gate semiconductor-dielectric stack.

Several models of Coulomb scattering are proposed in literature [20, 10, 21], but in this thesis we use exclusively the remote model, which is quite general and applicable to a finite gate stack with a high-κ material lying between a metal gate and an optional interfacial layer. Let’s call respectively Nsemi, NHKand NIT Lthe number of Coulomb scattering centers per

Performance evaluation of III-V compound semiconductor n-MOSFETs employing calibrated multi-valley and Multi-Subband Monte Carlo transport models

UNIVERSITÁ DEGLI STUDI DI UDINE

Dottorato di Ricerca in Ingegneria Industriale e dell’Informazione

Dipartimento Politecnico di Ingegneria e Architettura

Enrico CARUSO

Performance evaluation of III-V compound semiconductor n-MOSFETs

employing calibrated multi-valley and Multi-Subband Monte Carlo transport

models

Prof. Pierpaolo PALESTRI

Prof. Quentin RAFHAY

Prof. Gaudenzio MENEGHESSO

Prof. David ESSENI

Prof. Luca SELMI

Ph.D. Thesis

Abstract

Table of contents

List of figures

List of tables

Chapter 1

Introduction

1.1

On the Scaling Limits of Planar Si MOS Devices

V

log I

V

log I

1.2

III-V compounds: Benefits and Challenges

1.3

Thesis Outline

References

Chapter 2

The Multi-subband Monte Carlo Method

S

Ch

D

V

G1

V

G2

V

S

V

D

y

x

z

2.1

Introduction to the Multi-subband Monte Carlo Method

2.2

Solution of the 1D Schrödinger Equation

2.3

Derivation of the Scattering Rates

∑

∑

2.3.1

Screening

∑

∑

2.3.2

Non-Polar Phonon Scattering

2.3.3

Coulomb Scattering

_G1

_G2

_S

_V

_D

_∑