We have the following project specifications:

5. Proposed circuits and simulation results

Our aim is to design an amplifier with multigain and multifrequency capabilities. We begin with our specification and a short description of our simulation software. Afterwards, we describe the problems in designing an LNA, considering the effect of the external pads, the external matching network, and examining two elementary topologies and finally proposing a complete circuit with its layout.

5.1. Specifications

We have the following project specifications:

• Frequency band 1800 MHz, 1900 MHz, 2100 MHz

• Differential I/O

• Supply voltage = 1 V

• Drained current = 10 mA

• Noise figure = 1.5 dB

• Gain 5 dB Low Gain ÷ 15 dB High Gain

• Input matching: S 11 < -15 dB

• Linearity: Input IP3 = -10 dBm and CP1 = -20 dBm

• Differential input impedance: 200 O (100 O between each input terminal and ground) 5.2. Simulation environment

We used the Cadence application suit to design and simulate our circuits. We designed the circuit schematics with Composer-Schematic Editing and simulated it with the Spectre simulator in the Analog Artist tool. The simulations are based on the “BSIM3v3” model, that was developed to simulate MOS devices with very short channel lengths. For example the traditional 5-capacitances model of the MOS was replaced with 9 “transcapacitances” defined as partial derivatives of charges with respect to voltages. This model is based on the principle of conservation of char. ¹

Below two captured images of these tools are reported (Fig. 5.1-5.2).

1

BSIM3v3 Modeling Package, Advanced Modeling Solution , Rev. 5.20, pp. 33-43, October 1998

Figure 5.1 Comp oser-Schematic Editing tool

Figure 5.2Analog Artist tool

With Analog Artist we performed different types of analysis: transient, AC, DC, S-parameters, noise, linearity. In addition, parametric analysis was made in order to find the optimal solution. The results were shown in the Waveform Window, like in Fig. 5.3.

Figure 5.3 Waveform Window: results of a parametric simulation

5.3. Effect of the pads and bond wires on the input impedance

5.3.1. Modeling of pads and wires

To simulate a circuit as close as possible to the actual one, we created some models describing the

paths from the external pins of the chip package to the internal pads, considering all the parasitic

effects, such as series inductance and resistance of the bond wires, capacitance towards the substrate

and mutual inductance and capacitance between the input signal paths. These lumped-elements

models are shown in Fig. 5.4 and Fig 5.5. The values of the components are calculated using the

known parameters of the technological process. It should be noted the lower values for the

parasitics in the wires connecting the ground pin with the substrate pad. This is obtained using many wires in parallel, minimizing in such a way the series resistances and inductances.

Gnd Pin

Ω m

200 300 pH

Sub Pad

Ω

1 1 . 5 nH

fF 500

Vdd Pin Vdd Pad

Sub Pad

(a) (b)

Figure 5.4 Models for pads: (a) ground pad, (b) supply voltage pad

Ω m 100

Ω m 100

fF 35

Ω 700

Ω 700

nH 1

nH 1

2 . 0

fF

60 250 fF 20 fF

Ω m

500 200 pH 200 m Ω

Ω m

500 200 pH 200 m Ω

fF

250 20 fF

fF 60

fF 60 fF

60

Figure 5.5 Model for the input signal pads and bond wires

5.3.2. Simplified circuit of the input pads

By considering the input pads as a pure capacitance we can estimate their effect on the input

impedance. In the single-ended case we can calculate Z IN as the parallel between the intrinsic

impedance of the LNA, typically capacitive with a real part larger than zero, represented as the

series of a resistor and a capacitor and the pad capacitance (Fig. 5.6). The differential case is

identical when we apply a differential signal because the circuit is symmetrical.

C

C

R

Z

Figure 5.6 Simplified model for the input pads

The input impedance with the simplified pad has the following expression:

) (

1

2

PAD LNA

PAD LNA LNA

LNA LNA I

IN

s R C C s C C

C Z sR

+ +

= + (5.1)

To better understand the effect we give now some sample values:

R LNA = 50 O, C LNA = 500 fF, C PAD = 300 fF

Applying the (5.1) we obtain:

Z

I = 19.3 – j 101.7 O

That clearly shows that the input resistance is less than one half the original one.

5.4. External LC adapting network

To compensate such an unwanted effect we realized an external network, made up with passive

components, i.e., one inductor in parallel to the inputs and two capacitors in series, that do not

introduce additional noise. We will use components whose size meets the E12 standard, widely

available on the market.

Z

Z

Z

L

C

C

Figure 5.7 External LC matching network, input Pads, LNA

We need the capacitors C B to eliminate the residual positive reactance of the circuit, due to L X . The function of the inductor is to enhance the real part of Z IN I

. We can explain its effect by considering the following scheme:

I

L

C R

II

Z

I

Z

Figure 5.8 Single-ended equivalent circuit

Since the middle point of L X is “grounded” from a differential point of view, we can study only the upper half of the circuit, getting the same results. L X I

is equal to L X /2. Stated that X L and X C are the reactances of L X I

and C respectively we obtain:

( )

in in L

C

L C C L

L C

L L

C L C II

IN

R jX

X X R

X X X jX R

X X R

RX jX

jX R

jX jX

Z R = +

+ +

+ + +

+

= + +

+

= +

) (

)

( (5.2)

Limit cases:

• X

<< R , X

2 2 2

2 2

L C L

in

X

X R

X

R R ∝

= +

⇒ (The input resistance is proportional to the square of L X )

L

in

X

X =

⇒

• X

>> R , X

R R

=

⇒

C

in

X

X =

⇒

(The influence of the inductance becomes negligible when its value tends to infinity, being it in parallel to Zin)

-200 -150 -100 -50 0 50 100 150 200 250 300

0 2 4 6 8 10 12 14 16 18 20

Lx' (nH)

Rin, Xin (Ohm)

Rin Xin

Figure 5.9 Effect of L

on the input impedance of the LNA

In Fig. 5.9 we can see a numeric example that was obtained with the following values:

R = 25 O, C = 500 fF (typical for an LNA with input pads)

We can see that there is a range of L X I

for which R in achieves very high values. For example if we

want 100 O we have two values of L _X ^I that satisfy this requirement. If we take the smaller value we

will have an inductive reactance that must be compensated with the series capacitors, whose size is

in the order of picoFarads. Otherwise, we need two additional series inductors that compensate the residual capacitance. This solution is more expensive because we need three external inductors.

5.5. Cascode with LC load

Thanks to its good stability properties (see Par. 4.1.1) we will use a Cascode topology. In order to achieve a good input matching we will examine two possibilities: feedback resistor and dege nerating inductor. Concerning the load we will make use of an LC-tuned load that resonates at our operating frequency.

L

V

2

V

C

Figure 5.10 Cascode architecture with LC-load.

The role of the inductor is to resonate with C T, which is the sum of the input capacitance of the following stage (C MIX , 300 fF), of the capacitance of the output node C out and of the load capacitor C load :

C

= C

+ C

+ C

(5.3)

From a small signal point of view the V DD node can be considered as ground. Consequently in the

AC behavior the inductor is in parallel with C T . However we cannot neglect the parasitic resistance

R _s in series with L. We can schematize the LC- load as in Fig. 5.11-a:

L

R

C

L

R

C

Figure 5.11 Equivalent circuits for the LC-load

Now we can replace the series RL with a parallel configuration such as in Fig. 5.11-b by simply equating the impedances of both sections. Of course this assumption is valid only in the small neighborhood of a given frequency (in our case the resonant frequency). Such an equation leads to the followings:

R

= R

( Q

+ 1 ) (5.4)

out out

p

L

Q

L Q  ≅



 



 +

=

1

(5.5) where Q out is defined as:

ser s o p o

p T

p o

out

R

L L

C R R

Q ω

ω = ω =

= (5.6)

The approximation in (5.5) is valid for Q out larger than 3-4 (that is our case).

The use of an inductor has many advantages:

• Its DC impedance is (theoretically) zero, hence we have no voltage drop through it and no dissipated power. In reality we have a very small drop due to the current of 5 mA flowing through R ser , in the order of 10-15 mV.

• As the load inductor resonates with the output capacitance at our operating frequency (f o ), we have a second order LC-filter at the output, with a finite Q out due to the series parasitic resistance of the inductor, centered on f _o . In addition, at the input the gate inductor L _g resonates with the gate-source capacitance of the input MOSFET at the same frequency f o

with its own Q in as well, because of the input resistance R S . On the whole we observe a BP

behavior of the circuit, whose Q is given by the sum of Q in and Q out . This aspect is very positive since we deal with signals that have a BP spectrum and we need to suppress any unwanted interferers in the vicinity of the useful band.

• From the equivalent circuit of the load of Fig. 5.11-b it stems that at the resonance frequency the impedance of the LC tank coincides with the parasitic parallel resistance. Its value is given by (5.4). Since R ser of an integrated inductor (see Par. 5.10) is of the order of few ohms (three ohms in our inductor) and we succeeded in realizing an inductor with a Q of about 8.8 at 2 GHz, we obtained a very high value for the load impedance at the frequency of interest (about 235 O). Hence we had a considerable gain at f o . This value of R load is however slightly lowered because of the output resistance seen at the drain of the output MOSFET that goes in parallel with our load. It should be noted that, thanks to the LC- load, the output voltage goes above the supply voltage in the presence of a signal.

• Being R ser very low it affects positively the noise performance, lowering the NF (the equivalent parallel resistance is very large).

5.6. Cascode with source inductive degeneration

5.6.1. Schematic

We analyze now the single-ended configuration with degeneration source inductance, neglecting the effect of the pads.

L

L

V

2

V

C

L

Figure 5.12 Cascode with degeneration inductor L

We made a parametric simulation, changing the input MOSFET width to understand its effect on the main parameters such as Gain, input impedance, noise, linearity. Every time the V GS was changed to keep I D constant. This architecture uses an inductor source to adjust the input resistance.

We adapted it to a source resistance of 100 O. The residual reactance was eliminated with an external inductor in series at the gate of the input transistor that resonates with the input capacitance.

The table below shows the size of the components, the DC values and the small signal parameters we found with the simulation:

W 1 (µm) 100 200 300 400 500 600

W ₂ (µm) 400

L s (pH) 450 800 1200 1600 2100 2600

L g (nH) 47 25 17 14 14 14

L load (nH) 2.1

C load (pF) 2.4

C gs1 (fF) 132 264 396 528 660 792

Q in 3 1.5 1 0.75 0.6 0.5

V gs1 (mV) 522 461 432 413 400 389

g m1 (mS) 48 66.2 75.2 80.3 84.6 87

r o1 (O) 137 110 100.7 96 91.9 90.1

g m2 (mS) 82

r o2 (O) 94.3

V od (mV) 119 58 29 10 -3 -14

V _DD (V) 0.8

I D (mA) 5

Tab. 5.1 DC results and circuit parameters of the Cascode with inductive degeneration

The value of C GS1 was approximated with the gate capacitance, obtained by multiplying the value of

C OX = 11 fF/µm ² , provided by the foundry, by W and L. The gate of M 2 was set to V DD . We put in

series to the load inductor of 2.1 nH a parasitic resistor of 3 O (see Tab. 5.1).

5.6.2. Analytic calculation of Zin

Regarding this circuit topology, by neglecting C gd1 in Fig. 5.12 and making the approximation r o1 ? 8 we get the usual formula for the estimation of Z in (see formula 4.4):

gs s

gs s m

in

sL sC

C L

Z = g

+ + 1 , (5.7)

that tells us that the input impedance is proportional to L S .

Unfortunately this formula is not accurate enough. For a better analytical estimation of the input impedance we will use the following formula:

( ) _{( )}

( ) ( ) _



 



 + +

+ +

 +



 



 + + +

+

+

 +



 



 + +

 +



 



 + + +

+

=

2 1 1 1

2 1 1

1 2

1 3

2 1 2 1 1 1 2

1 1 1

2 2

2

3 1

1

1

m

gd gs gd o m gd gs o m

gd gs o gd o m s gd gs s o

gd gs s

m o m

gd o o m s m

gd s o m gs s o m

gd gs s m

o gs gd s

in

g

C C C r C g

C r g s

C C C r

r g L C C L s r C C L s

r g g

C r r

g L g s

C L r C g

L g r

C C s L g

r C C s L Z

(5.8)

The complete calculation of Z in is reported in Appendix A.

To verify how accurate such formula is, we compared it with the (5.7) and with the results given by

the simulator, related to the configurations in Tab. 5.1. C gd was assumed to be one fourth of C gs .

0 50 100 150 200 250 300 350

100 200 300 400 500 600

Win (um)

Rin (Ohm)

Simulated Rin Theoret. Rin (5.7) Theoret. Rin (5.8)

Figure 5.13 R

as a function of W

-700 -600 -500 -400 -300 -200 -100 0

100 200 300 400 500 600 Win (um)

Xin (Ohm)

Simulated Xin Theoret. Xin (5.7) Theoret. Xin (5.8)

Figure 5.14 X

as a function of W

We can see from the above figures that the formula (5.8) is largely more accurate than (5.7).

5.6.3. Analytic calculation of the gain

We can approximate the voltage gain with the following formula:

Gain = Q

g

( R

// R

) ≅ Q

g

( R

//( g

r

r

)) (5.9)

where

gs o s

in

R C

Q 2 ω

= 1 (5.10)

is the bounty factor of the input mesh, whe n the circuit is adapted to the source resistance R _S .

R

= R

( Q

+ 1 ) (5.11)

is the equivalent parallel resistance of the LC-resonating load. R ser is the series parasitic resistance of the load inductor and Q out is its bounty factor so defined:

ser load o

out

R

Q = ω L (5.12)

0 5 10 15 20 25 30 35

100 200 300 400 500 600

Win (um)

Gain (dB)

Simulated Gain Theoretical Gain (5.9)

Figure 5.15 Gain as a function of W

The real gain is lower than expected because we neglected the parasitic capacitance of the transistors. C GS1 was taken into account through Q in .

5.6.4. Estimation of the noise figure

The dominant noise source in the circuit is the thermal noise of the channel of the input MOSFET.

We schematize it with a noise current generator in parallel to the MOSFET:

2 ,Rs

V

R

L

L

R

2

I

V

V

Figure 5.16 Simplified circuit to estimate the Noise Figure

Its value is approximately the following:

KT g i

3

= 8 (5.13)

where K is Boltzmann’s constant and T is the absolute temperature. The total noise voltage at the output is, considering also the thermal noise of the source resistance:

V

= 4 KTR

A

+ i

R

(5.14)

where

in p m

v

g R Q

A =

(5.15)

The Noise Factor is therefore:

= +

= +

+ =

=

=

1 2

2 2

1 2 1 2

2 1 2

2 2

,

3 1 2 4

3 8 4 1

3 4 8

4

p m

v s

p m v

s

v s out n

Q g R R

Q g KTR

R KTg A

KTR

R KTg A

KTR A

KTR F V

1 2 2 0

3 1 8

m s gs

g R ω C +

= (5.16)

We see from the approximated formula (5.16) the great importance of the bounty factor in the input mesh to reduce the noise.

Replacing the values in (5.16), extracting the g _{m 1} from the DC analysis (Tab. 5.1) of the simulator we obtain the approximated curve of the Noise Figure. Comparing it with the real ones, simulated with a Noise analysis Spice Model 2, Fig. 5.17, we see that they are pretty different.

0 0,2 0,4 0,6 0,8 1 1,2 1,4

100 200 300 400 500 600 Win (um)

NF (dB)

Simulated NF Theor. NF (5.16)

Figure 5.17 Noise Figure as a function of W

We note the presence of a minimum in the simulated curve. This can be explained as follows: (5.16) tells us that the noise factor is inversely proportional to Q in 2

that predicts a 0 dB Noise Figure as W approaches zero. In reality we have to consider the resistance of the inversion layer that is about: ²

m

inv

g

R 5

≈ 1 (5.17)

The effective V _gs will be now:

in eff

gs

Q V

V = (5.18)

where Q eff is an “effective” Q in that includes the effect of R inv and could be so defined:

) 2

( 1

inv s gs o

eff

C R R

Q = +

ω (5.19)

This quantity tends to a constant value for W small enough, since C _gs is proportional to W and the inversion layer resistance is inversely proportional to the same quantity.

The inversion layer resistance can be represented as a resistor in series with C gs whose noise contribution must be taken into account. Replacing the (5.19) in (5.16) and adding the thermal noise of R inv we obtain

3

1 2

eff m s S

inv

Q g R R

F = + R + (5.20)

For W ? 0, the last term in (5.20) is inversely proportional to 1/g m 1 since Q eff remains contant.

Moreover the term in the middle is proportional to R inv . That means that the NF will begin to increase again for a definite W and implies the presence of a minimum.

2 A. A. Abidi, G. J. Pottie, W. J. Kaiser, “Power-Conscious Design of Wireless Circuits and Systems ” Proceeding of

the IEEE, Vol. 88, No. 10, pag. 1532, October 2000

5.6.5. Consideration about linearity

Contrary to what is expected the linearity improves as W increases, as we can see in the graph below.

CP1

-35 -33 -31 -29 -27 -25 -23 -21 -19 -17 -15

100 200 300 400 500 600

Win (um)

CP1 (dBm)

CP1

Figure 5.18 1-dB Compression Point as a function of W

We have two opposite effects associated with the increasing input MOSFET width: the overdrive voltage V GS -V T decreases, worsening the linearity while the input Q decreases. This means that the signal voltage between gate and source, equal to Q in V in , decrease as well, so improving the linearity by preventing the amplifier to saturate. It can be shown ³ that in a narrowband architecture like our LNA the input IP3 is proportional to 1/(Q _in ) ² . Furthermore, the linearity is improved by the source inductor that performs a negative feedback. In particular it linearizes the system in the following way: if the input signal at the gate increases, a larger drain current will flow through the inductor, its voltage drop (that is the source voltage) will increase and V gs will decrease, in such a way compensating the initial variation and keeping g m constant.

3 A. A. Abidi, G. J. Pottie, W. J. Kaiser, “Power-Conscious Design of Wireless Circuits and Systems ” Proceeding of

the IEEE, Vol. 88, No. 10, pag. 1532, October 2000

5.6.6. Stability

Another issue we can experience is the possibility that the real part of the input impedance becomes negative, leading to oscillations. To understand this look at Fig. 5.19

C

L

C

Figure 5.19 Source degeneration inductor with parasitic capacitance in parallel

In a CS circuit the bulk-source capacitance is shorted because the source is grounded. When we use a source degeneration technique this capacitance will be in parallel with L S . We saw in the simplified formula (5.7) that the real part of such a circuit is about:

gs s m

in

C

L

R = g (5.21)

If we replace L S in (5.21) with the parallel of the inductor with C BS we have now:

BS S S gs

m

in

L C

L C

R g

1 ω ω

= − (5.22)

where the fraction on the right is the reactance between source and ground. If this term becomes negative, that is if:

2

L

C

> 1

ω (5.23)

then R _in will be negative too, leading to instability. This can be avoided by minimizing C _BS .

5.6.7. Simulation results

Unfortunately, simulating the complete circuit with the pads, this architecture gave us an unexpected result in the transient analysis. The system seemed to oscillate even if the stability parame ter K f was by far larger than 1. A probable cause of this behavior was the pad capacitance, since the system worked correctly without this parasitic.

5.7. Cascode with feedback resistance

5.7.1. Schematic

L

L

V

2

V

C

R

C

Figure 5.20 Cascode with feedback resistor R

We will investigate now a second possibility to realize the required input match: a parallel feedback resistor. The capacitor C f of 1 pF was needed to separate input and output in DC. At high frequencies (2 GHz) its reactance is negligible in comparison with R f :

= 1 ≅ 80 Ω

f o

f

C

X ω (5.24)

All the other parameters and the DC values stay unchanged and are the same as those of the circuit

with L S .

5.7.2. Analytic calculation of Zin

1

1 1 1

2 1 1

2 1

1 2

2 1 2 1

1

1 2

2 1 2 1 1 1

1 1 1

2 1 1

2

// 1

1

) (

1 1

1 1 1

1

) (

gs

m m

L m m

m m gd

m m m m

gd f m

L m L

f L

in

sC

Z Z g

g

Z Z Z g g

Z g

Z Z g

sC

Z g

Z g Z g

g sC Z

Z R g

Z Z Z Z g

R Z Z

+ − + +

− + +

− + +

 





 



 + + +

+

− +

= +

(5.25)

For the complete calculation of Z in see Appendix A.

Using the analytic formula (5.25) and replacing the value of the DC analysis, valid for a drain current of 5 mA, we see how the input impedance changes when R f is varied. The two graphs below show the effect of R _f on the input impedance in two cases: W _in = 100 µm and 500 µm. We realize that the input resistance of the LNA reaches a maximum when the feedback resistance decreases and beyond that R in drops as well. For values of the input MOS width that are larger than 100 µm it was not possible to obtain 100 O. This is really not a problem since we have still to consider the effect of the pads and we can raise this value with the external inductor (see Par. 5.4). We can see from this graph that there are two possible values of R f that realize the desired resistance: a smaller and a larger one. The former gives a better linearity, the latter a better Noise Figure.

0 50 100 150 200 250

0 4 8 12 16 20 24 28 32 36 40 44 48 Rf (kO)

Rin (O)

W=100µm W=500µm

Figure 5.21 Dependence of R

on R

at two different W

s

Concerning the input reactance, it approaches zero as the R _f decreases.

-500 -450 -400 -350 -300 -250 -200 -150 -100 -50 0 50

0 4 8 12 16 20 24 28 32 36 40 44 48 Rf (kO)

Xin (O)

W=100µm W=500µm

Figure 5.21 Dependence of X

on R

at two different W

s

For every width of the input MOSFET we made an adaptation to a source of 30 O, since it was not possible to reach 100 O. The table below shows the size of the components used to this purpose:

W 1 (µm) 200 300 400 500 600

W 2 (µm) 400

R f (kO) 19.7 9.5 5.7 3.7 2.5

L g (nH) 19.8 12.7 9.2 7 5.5

Q _in ⁴ 5 3.3 2.5 2 1.67

Tab. 5.2 Circuit parameters of the Cascode with feedback resistor

L g is the series inductor at the input that eliminates the residual negative reactance. We compared the expected theoretical values given by the formula (5.25) with the results of the simulation. Also in this case C gd was assumed to be one fourth of C gs . The graphs below illustrate this comparison, relative to the resistance and the reactance of Z _in :

4

The value of Q

is now larger because the circuit was adapted to a source resistance of 30 O

0 5 10 15 20 25 30 35 40

200 300 400 500 600

Win (um)

Rin (Ohm)

Simulated Rin Theor. Rin (5.25)

Figure 5.22 Theoretical and simulated values of R

as a function of W

-300 -250 -200 -150 -100 -50 0

200 300 400 500 600

W (um)

Xin (Ohm)

Simulated Xin Theor. Xin (5.25)

Figure 5.23 Theoretical and simulated values of X

as a function of W

5.7.3. Analytic calculation of the gain

To estimate the voltage gain we used the following small signal circuit, where the capacitances of

the transistors were neglected:

1 1 gs m

V g

R

R

V

R

V

Figure 5.24 Simplified variation circuit to estimate the Gain

The effect of C GS1 will be included when we multiply the final gain by the Q in . The Cascode is seen as a transconductive amplifier whose output resistance is, approximately:

1 2 2 o o m

CASC

g r r

R ≅ (5.26)

From Fig. 5.24, with simple calculations we obtain:

P m f

m

OUT

g V

R R

R R g

V  





 



 −

+

= +

1

(5.27)

where:

CASC

P

R

R

R = // (5.28)

and thus, considering the resonating input mesh:

 





 



 −

+

= +

= 1

m f

m in

IN

OUT

g

R R

R R g

V Q

Gain V (5.29)

0 5 10 15 20 25 30 35 40

200 300 400 500 600

Simulated Gain Theor. Gain (5.29)

Figure 5.25 Theoretical and simulated Gain as a function of W

The difference between theoretical and simulated values stems from the approximation we made by neglecting the MOSFET capacitances.

5.7.4. Noise figure

Once again we had a minimum in the Noise Figure. This is due to the effective Q in , whose value is much larger than expected for small W because of the inversion layer resistance.

simulated NF

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6

200 300 400 500 600

Win (um)

NF (dB)

simulated NF

Figure 5.26 Simulated Noise Figure as a function of W

Moreover, the NF is larger than that of the source degeneration Cascode. The reason is the presence of the noisy feedback resistor that increases the overall noise, particularly for larger values of W, where we used smaller R f .

5.7.5. Considerations about linearity

CP1

-35 -33 -31 -29 -27 -25

200 300 400 500 600

Win (um)

CP1 (dBm)

CP1

Figure 5.27 Simulated 1-dB Compression Point as a function of W

The simulated values of the 1-dB compression point are not very good. The reason is the very high input Q factor (see Tab.5.2). In the final circuit however, the real Q _in will be much smaller because of the unavoidable parasitics, particularly in the input pads, hence we will see a significant improvement of linearity. Again Fig. 5.27 depicts that the dependence of CP1 on Q _in is much stronger than that on the overdrive voltage. Moreover, the feedback resistance improves the linearity. If the input signal increases, the higher drain current will cause a drop in the output voltage (V d2 ). This will reduce the input gate voltage through R f so stabilizing the g m of the input transistor.

So far we have seen the positive effect of the input Q on the Gain (which increases proportionally to

the bounty factor) and over the Noise figure (5.16). On the other hand this factor should be limited

in order to keep the linearity acceptable ( IIP

∝ 1 / Q

). Another issue arises when dealing with very

high input Q: the strong dependence on the tolerance of the passive components. A change in their

size has a strong influence on the resonance frequency. It can be shown that, if we want a maximum deviation of 1-dB in the gain at the nominal frequency, we must have: ⁵

2 2

2

1

 

 

 +  ∆

 

 



<  ∆

C C L

L

Q (5.30)

Thus, the larger the relative variation in the passive elements (denominator), the smaller must be Q in order to limit the sensibility of the circuit to such variation.

5.8. Possible solutions to obtain two gain steps

We analyze some ways to design a Variable Gain Amplifier (VGA).

5.8.1. Crossed Cascode

In this circuit the MOSFETs HG and LG conduct alternately depending on the output of control logic. This solution works as follows: in High Gain the MOS HG are switched on and they conduct a signal that will be added to that that flows through the inner transistors; in Low Gain the MOS LG are ON and their signal will be subtracted to that of the inner transistors. If the HG and LG MOS are sized with the same W and L, the DC output voltage will not change with the gain step we selected. This advantage is important only if we use a resistive load while with an inductive load the output voltage is practically coincident with V DD .

5 H. Darabi, A, A. Abidi, “A 4.5 mW 900-MHz CMOS Receiver for Wireless Paging” IEEE Journal of Solid-State

Circuits, Vol. 35, No. 8, pag. 1086, August 2000

L

V

2

V

C

2

V

L

V

Figure 5.28 VGA 1: Crossed Cascode

A problem of such a configuration is that it is not possible to adapt the circuit to the input port with the same adapting network in both gain modes because the input impedance of this circuit is strongly dependent on the Gain level. A partial solution would be the use of an auxiliary circuit that can be switched on in low gain mode to modify the Z in . However, if our aim is to design a multifreque ncy amplifier this solution is not feasible.

5.8.2. Variable current generator

This solution makes use of a variable current generator. In High Gain both I 1 and I 2 are ON, the

maximum current flows through the transistors, maximizing their g m . In Low Gain only I 1 works so

that the bias current is lower. An advantage of this circuit is the reduced power consumption in low

gain modality thus maximizing the battery endurance in a portable device.

C

L

V

2

V

V

2

V

L

I

I

Figure 5.29 VGA 2: Cascode with variable current generator

However when dealing with MOSFETs whose channel length is only 0.12 µm a small current means that they will work in the subthreshold zone. In our case with a current level of 1 mA, required to obtain the required low gain, an overdrive voltage of -100 mV was obtained in the simulations, which means that the MOS work in deep subthreshold zone. Operation in this region is very difficult to model and can lead to unexpected results. The Noise Figure in Low Gain mode increases substantially when working in deep subthreshold.

5.8.3. Capacitive divider

A third method to realize two gain steps is shown in Fig. 5.30 and makes use of a capacitive

divider at the output:

C

L

V

2

V

V

2

V

L

C

C

C

C

C

C

Figure 5.30 VGA 3: Cascode with output capacitive divider

Two capacitor C low can be inserted by mean of two switches, controlled through an integrated logic.

In High Gain these capacitors are switched off then the output voltage will be given by the capacitive divider C ₁ , C _mix . The latter is the capacitance seen at the input of the load (mixer) and is smaller then C 1 . In Low Gain mode C low are activated and they will work in parallel with C mix . Being C low much bigger than C 1 and C mix the voltage drop through the parallel C mix , C low will be very low. This topology enabled us to achieve a good input matching with the same external network in both modes. The Noise Figure remains nearly unchanged (and very low) when switching in Low Gain mode. This is because the bias current and the working transistors are the same in both modes. The input dynamic range does not improve when the LG mode is activated since we intervene only at the output of the amplifier. This implies that the linearity of the LNA is about the same in both Gain steps. However, as we will demonstrate later, reducing the voltage of the output signal the linearity of the complete receiver will be improved.

5.9. Multifrequency amplifier

In order to realize a frequency-variable amplifier we implemented the following solution: the load capacitance is varied by adding few additional capacitors. The larger the value of the total output capacity, the lower the resonance frequency, which determines the maximum of the Gain curve.

The additional capacitors are depicted in Fig. 5.31 as C lf and C lmf . In low frequency mode(1.8 GHz)

all capacitors are inserted, in medium frequency (1.9 GHz) only C load and both C lmf . In high

frequency only C load works.

C

L

V

2

V

C

C

C C

V

L

2

V

C

C

C

C

Figure 5.31 Multifrequency LNA: Cascode with variable resonating load

5.10. Integrated inductor (model with parasitics, area, tolerance)

Our circuit makes use of integrated inductors as a load. It has a differential architecture, thus it requires a couple of identical inductors that have one terminal in common (Fig 5.32).

Figure 5.32 Arrangement of inductors with a pin in common

With these considerations in mind we can design the layout of the couple of inductors in a particular

optimized shape in order to reduce the required space on the silicon die. The plain view is shown in

Fig 5.33-a and consists in a planar spiral with octagonal shape. Its bulk is made of one or more

metal layers shorted together with vias.

(a)

Substrate Common

A B

Common

A

B

C

1

R

L

L

R

M

1

C

C

C

1

R

C

C

R

C

R

(b)

Figure 5.33 Integrated inductor: (a) physical layout, (b) lumped element model

To better simulate the behavior of this component in the schematic view we utilized an equivalent circuit (Fig. 5.33-b) made up with components describing all the parasitics present in the actual inductor. This model makes use of lumped components that synthesize the real distributed behavior of the parasitics. Here is a description of the meaning of the elements:

Component Meaning

C ab Capacitance between the terminals A, B

L 1 , L 2 Inductance between the “Common” pin and A, B respectively M Mutual inductance between L 1 , L 2

R _s1 , R _s2 Resistance between the “Common” pin and A, B respectively C ox1 , C ox2 , C ox3 Capacitance between the metal layer and the substrate

C sub1 , C sub2 , C sub3 Substrate loss capacitance R sub1 , R sub2 , R sub3 Substrate loss resistance

Table 5.3 Inductor modeling: description of the parameters

For our design we need to create a couple of inductors whose value (in pH) is set by the circuit

requirements. An integrated inductor suffers mainly from three kinds of losses: ohmic, capacitive

and inductive. The first stems from the resistivity of the metal windings, the second from metal-

metal and metal-substrate capacitive coupling and the third through metal-substrate inductive

coupling (Eddy currents). We must find an optimal solution that minimizes the parasitic capacitances, the parasitic series resistance (to increase the Q factor), the required area and maximize the resistance toward the substrate to obtain an element as close to “ideal” as possible. To this aim we make some remarks: 1. To minimize the parasitic capacitance between metal layer and substrate we should use the upper layers (larger distance layer-sub). 2. To minimize the series resistances we should use the largest possible number of layers, shorted together (larger area of the windings), in contrast with 1. 3. To minimize the area we must use narrow windings that implies however larger resistance or reduce the spacing between the windings (increasing the capacity between the windings). 4. We can design inductors with large inductance but at the cost of a huge required surface. We designed the component with the aid of a software tool, called Fsymcoil, whose interface window is shown in Fig. 5.3.

Figure 5.34 User interface of Fsymcoil

The user sets the technology file, the desired metal layers, number and width of the windings,

spacing between winding, inner radius. Then the program calculates all the values of the

components of the model in Fig 5.33-b and draws the final shape (like in Fig 5.33-a). We noted a

beneficial effect due to the mutual inductance (M): the final value of the single inductors is larger

than that of L 1 and L 2 and is equal to L 1 +M, hence we need a number of windings smaller as expected. We made an implementation of an inductor with a good compromise among area, quality factor and final value. The table below contains all the parameters of the inductor we designed.

Parameter Inductor 2.1 nH x 2

L ₁ , L ₂ 1.13 nH

k 0.86

M 0.97 nH

R s1 , R s2 3.05O

C ab 121.6 fF

C ox1 , C ox2 125.9 fF

C ox3 251.8 fF

C sub1 , C sub2 12.0 fF

C sub3 24.1 fF

R sub1 , R sub2 1.62 kO

R _sub3 810 O

Inner radius 24 µm

External diameter 103.2µm

Windings 7

Track width 3 µm

Spacing between tracks 1.1 µm

f

6.5 GHz

Table 5.4 Parameters of the integrated inductor

5.11. General Scheme

C

C

L X

V DD

Figure 5.34 Schematic of external adapting network, Pads, LNA, Mixer

5.12. Final circuit schematic

The final schematic is depicted in Fig. 5.35. On the left we can see the biasing transistor with the

resistance R 1 . It biases the gates of the input transistors (M 1 ) with the required voltage to have a

drain current of 5 mA per MOSFET. Once we polarize the input MOSFETs the I D of the Cascode is

fixed by them. Consequently, the gate voltage of M 2 is determined. In order to maximize the drain-

source voltage of M 1 so that they can work in deep saturation V G2 must be as large as possible. For

this reason the common gate transistors (M 2 ) have a gate voltage of V DD . The bias resistors of 10 kO

prevent the input signal to go to the gate of M 3 . Their large size minimizes their contribution to the

noise figure. A current source was avoided to reduce the number of stacked transistors and hence

the required supply voltage, which is limited in our case to 0.8 V. C HG was added to avoid a change

in the resonance frequency of the load when switching between high and low gain. In low gain we

see from the drains of the output MOSFET, looking toward the output, C 1 in series with the parallel

C LG -C MIX , where C MIX is the input capacitance of the mixer. This yields a total capacitance of about

710 fF. In high gain we see the series of C 1 and C MIX in parallel with C HG that leads to 870 fF. This

difference causes a small frequency shift in the minimum of S 11 . We could use a larger C LG but that

would reduce the gain excessively. C 1 must be small enough so that most of the output voltage

drops through it in low gain (capacitive divider with C LG ) but much larger than C MIX (300 fF) so that the most part of V OUT drops through the mixer in High Gain.

C

L

V

V

C

C

C

C

C

R

R

R

C

L

V

R

R

C

C

C

C

C

C

V

M

M

V

M

Figure 5.35 Schematic of the final circuit, including the bias section

The switching of the capacitors is realized through MOSFETs biased in the linear region or cut-off, whose gate is controlled by the outputs of an integrated logic (see Par. 5.8.2). The inductors in the schematic are, in the simulation, instances of the detailed circuit with parasitics, illustrated in Fig.

5.33-b.

MOS W (µm) L (nm)

M 1 77·6.52=502.04 120

M ₂ 77·6.52=502.04 120

M 3 6.52 120

Switches 48·6.52=312.96 120

Table 5.5 Size of the MOS transistors

Component Value

C load 300 fF

C f 1 pF

C LF 400 fF

C LMF 600 fF

C HG 650 fF

C LG 6 pF

C 1 800 fF

R _f 1.7 kO

R BIAS 10 kO

R 1 6 kO

L LOAD 6

2.1 nH

Table 5.6 Size of the passive components

5.13. Control logic

We need this digital circuit to select the operating mode. We have two input pins, M0 and M1 and four outputs, HG, LG, LMF, LF which serve to activate the required capacitors.

The operating modes are:

M1, M0 = 0 0 : GSM 1800 M1, M0 = 0 1 : GSM 1900

M1, M0 = 1 0 : UMTS 2100 Low Gain M1, M0 = 1 1 : UMTS 2100 High Gain

6

For details about the integrated inductor see Par. 5.7

The table 5.7 shows how this logic works according to the input pins

Input Output

M1, M0 HG LG LF LMF

0 0 1 0 1 1

0 1 1 0 0 1

1 0 0 1 0 0

1 1 1 0 0 0

Table 5.7 Truth table of the control logic

The dual gain functionality is provided only at 2.1 GHz since the UMTS standard requires this capability while the traditional GSM (1.8-1.9 GHz) does not use it.

The logic port scheme (NAND, NOR, NOT) is reported below:

Figure 5.36 Logic port scheme of the control logic

5.13.1. Simulation results

The followings simulations were performed considering all the parasitics in the Pads (Fig. 5.4, 5.5)

and the complete model of the integrated inductor. The supply voltage was 0.8 V and the circuit has

an input differential impedance of 100 O, including the external adapting network.

5.13.1.1. DC results

MOS V GS (mV) V od (mV) V DS (mV) I D (mA) g m (mS) g ds (mS)

M 1 393.9 -8.9 340.2 4.55 78.3 10

M 2 445.4 -12.9 431.6 4.55 79.3 10.28

M 3 393.9 -4.6 393.9 0.065 1.1 0.137

Table 5.8 DC operating point of the MOS transistors

The table above shows that the transistors operate slightly in the subthreshold region. This was not avoidable since the channel length we use are very short. To increase the V od we require a drain current that is beyond our specifications. We could increase the channel length but this would lead to a worsened Noise Figure and a smaller Gain. We can also reduce the MOSFET width obtaining the same negative effects. Linearity is also worsened with a smaller W (or a longer L) since we increase the Q in even if the overdrive voltage becomes larger.

5.13.1.2. Summary of simulation results

The table below gives a summary of the results obtained with the simulation of the circuit. The values are referred to the correspondent frequency of each mode, i.e. 1.8, 1.9, 2.1 GHz.

Mode AC Gain (dB) S11 (dB) NF (dB) Kf IIP3 (dBm) CP1 (dBm)

18 HG 15.8 -18.1 1.27 1.35 -5.54 -17.76

19 HG 16.1 -23.7 1.16 1.33 -5.31 -18.06

21 HG 16.4 -17.3 1.05 1.31 -5.94 -18.47

21 LG 3.0 -15.6 1.14 2.80 -7.35 -19.74

Table 5.8 Simulation results

The detailed graphs are reported in appendix B.

5.13.1.3. Considerations about linearity

The reason why we want a multigain amplifier is to avoid the saturation in presence of a strong

input signal. The topology we chose lowers the gain reducing the signal voltage at the output and

not at the input of the LNA. One may object that such a solution would ha ve no influence on the linearity of the system. We should however consider that the LNA is only the first stage of a receiver. We have seen with the formula (2.11) that if the stages of a chain have a gain the latter will have a larger influence on the overall linearity than the first ones. Our amplifier will be followed by a mixer whose gain is around 5 dB. We simulated the chain with our amplifier followed by a mixer in both gain modes and traced the graphs relative to the IIP3. These are illustrated below:

High Gain

-140 -120 -100 -80 -60 -40 -20 0 20

-50 -45 -40 -35 -30 -25 -20 -15 -10 Input (dBm)

Output (dB)

1 dB/dBm 3 dB/dBm 1st order 3rd order

Figure 5.45 Overall IIP

in 2.1 GHz HG mode

Low Gain

-140 -120 -100 -80 -60 -40 -20 0 20

-40 -35 -30 -25 -20 -15 -10 -5 0 Input (dBm)

Output (dB)

1 dB/dBm 3 dB/dBm 1st order 3rd order

Figure 5.46 Overall IIP

in 2.1 GHz LG mode

The overall Input Intersection point was of -13.2 dBm for High Gain Mode and -4.0 dBm for Low Gain Mode (Fig. 5.45-5.46).

We see that with the capacitive divider at the output, that is reducing the voltage at the input of the

mixer, we were able to improve the IIP3 by nearly 10 dBm.