SISTEMI EMBEDDED

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SISTEMI EMBEDDED

Course Presentation – Spring 2018

Federico Baronti

Dip. Ing. Informazione

Via G. Caruso, 16 – Stanza B-1-09

050 2217581 – [email protected] http://www.iet.unipi.it/f.baronti/

Office hours:

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2M ElettronicaLuMaMeGiVeSa

8:30/9:30

9:30/10:30 NanoelettronicaC33 NanoelettronicaC22 10:30/11:30 NanoelettronicaC33 NanoelettronicaC22

11:30/12:30 NanoelettronicaC33 Sistemi embeddedB24 Sistemi di elaborazioneSI 7 12:30/13:30 Sistemi embeddedB24 Sistemi di elaborazioneSI 7

13:30/14:30 Sistemi di elaborazioneADI1 Sistemi di elaborazioneSI 7 14:30/15:30 Sistemi di elaborazioneADI1 NanoelettronicaC41

15:30/16:30 Sistemi embeddedADI3 ex B26 NanoelettronicaC41 Sistemi embeddedADI3 ex B26 16:30/17:30 Sistemi embeddedADI3 ex B26 NanoelettronicaC41 Sistemi embeddedADI3 ex B26

17:30/18:30 Sistemi embeddedADI3 ex B26 Sistemi embeddedADI3 ex B26

w w w . l a n t i v . c o m

Class Schedule

F. Baronti - Sistemi Embedded - University of Pisa 2

Optional Lab

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Course Objectives

Learn expertise and methodologies to

design and program an embedded system

We’ll use as a reference a System on Programmable Chip (SoPC) platform

based on an Intel (formerly Altera) FPGA

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Course Organization

Group Project

Computer Organisation

Embedded C

Programming Embedded

C

Programming

Tools:

Compiler Linker JTAG debugger

Tools:

Compiler Linker JTAG debugger

Nios II proc.

& System Interconnect

Fabric Nios II proc.

& System Interconnect

Fabric Performance

Metrics Constraints Performance

Metrics Constraints

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Course Requirements

• Digital Electronics

• Digital Logic Design

– HDL Coding

• Software Programming

– Basic knowledge of C or C⁺⁺ Language

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Group Project

• Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite board

– Computer implementation

• May require the design of one or more custom peripherals

– Software programming

• Project assignment during the 5

^th

week

• See Projects of previous years to gather an idea

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Course Material (1)

• Available at the course web page:

^http://

http://www.iet.unipi.it/f.baronti/didattica/SE/2018/Sistemi Embedded.html

• Slides used during lectures

• Project templates/examples

• Text book:

– C. Hamacher, Z. Vranesic, S. Zaky, N. Manjikian

"Computer Organization and Embedded Systems,”

McGraw-Hill International Edition

• Documentation from Intel FPGA (Altera)

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Course Material (2)

• Quartus Prime Lite Edition (16.1 update 2),

with Max 10 Device Support

• University Program Installer (16.1)

• Nios II Documentation

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The DE10-Lite package includes:

The DE10-Lite board

Type A Male to Type B Male USB Cable

11. . 2 2 DDEE1010-L-Liittee SSysystteem m CCD D

The DE10-Lite System CD contains the documentation and supporting materials, including the User Manual, Control Panel, System Builder, reference designs and device datasheets.

User can download this System CD from the web (http://DE10-Lite.terasic.com/cd).

11. . 3 3 LLaayoyouutt aannd d CCoompmpoonneennttss

This section presents the features and design characteristics of the board.

A photograph of the board is shown in Figure 1-2 and Figure 1-3. It depicts the layout of the board and indicates the location of the connectors and key components.

Course Material (3)

• 14x DE10-Lite: Development & Education board

– Intel Max 10 10M50DAF484C7G (50k LE; 1,638 Kb in M9K blocks)

NEWNEW

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Course Material (4)

• 2x Touch display (LT24), 6x 8M Pixel Camera (D8M-GPIO), Multi-touch LCD Module Second Edition (MTL2), Servo Motor Kit (SVK)

MLT2 User Manual 27 www.terasic.com

April 12, 2016

Figure 5-2 displays the five-finger painting of the canvas area.

Figure 5-2 Five-finger Painting

55..22 SSyysstteem m DDeessccrriippttiioonn

For LCD display processing, the reference design is developed based on Altera’s Video and Image Processing Suite (VIP). The Frame Reader VIP is used for reading display content from the associated video memory, and VIP Video Out is used to display the display content. The display content is drawn by the NIOS II processor according to user input.

For multi-touch processing, a Terasic Memory-Mapped IP is used to retrieve the user input, including multi-touch gestures and single-touch coordinates. For IP--usage details please refer to the Chapter Three in this document. Note: the IP is encrypted, so the license should be installed before compiling the Quartus II project.

Figure 5-3 shows the system generic block diagram of demonstration reference design.

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MTL2

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Exam Evaluation

• Project Evaluation (~40 %): the same marking for all the group members

– Presentation and Demo (~30 %) - Due on last class – Project report (~70 %) – Due a “week” before the

selected exam date

• Oral Test (~60 %)

– Project discussion (~50 %)

– Assessment of understanding and mastering the course contents (~50 %)