Capacitors Voltage Switching Ripple in Three-Phase Three-Level Neutral Point Clamped Inverters with Self-Balancing Carrier-Based Modulation

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Article

Capacitors Voltage Switching Ripple in Three-Phase Three-Level Neutral Point Clamped Inverters with Self-Balancing Carrier-Based Modulation

Manel Hammami , Gabriele Rizzoli * , Riccardo Mandrioli and Gabriele Grandi

Department of Electrical, Electronic, and Information Engineering, University of Bologna, 40136 Bologna, Italy;

manel.hammami2@unibo.it (M.H.); riccardo.mandrioli4@unibo.it (R.M.); gabriele.grandi@unibo.it (G.G.)

* Correspondence: gabriele.rizzoli@unibo.it; Tel.: +39-051-20-9-3585

Received: 23 October 2018; Accepted: 19 November 2018; Published: 22 November 2018
^

_

Abstract: This paper provides a comprehensive analysis of the capacitors voltage switching ripple for three-phase three-level neutral point clamped (NPC) inverter topologies. The voltage ripple amplitudes of the two dc-link capacitors are theoretically estimated as a function of both amplitude and phase angle of output current and the inverter modulation index. In particular, peak-to-peak distribution and maximum amplitudes of the capacitor voltage switching ripple over the fundamental period are obtained. A comparison is made considering different carrier-based pulse-width modulations in the case of almost all sinusoidal load currents, representing either grid connection or passive load with a negligible current ripple. Based on the voltage switching ripple requirements of capacitors, a simple and effective original equation for a preliminary sizing of the capacitors has been proposed. Numerical simulations and experimental tests have been carried out in order to verify the analytical developments.

Keywords:voltage ripple; voltage source inverter; three-phase inverter; DC-link capacitor design

1. Introduction

In industrial applications, the most used switching inverter is the two-level converter. Due to mass production, it is a relatively cheap and reliable configuration. Furthermore, as the number of semiconductor devices is low, they can be simply controlled by different types of pulse-width modulation (PWM) techniques. However, the main drawback of the two-level converter is the high harmonic content of the output voltage, which makes the use of bulky output filter necessary, increasing the cost of the system and the losses. The harmonic content can be reduced simply by increasing the PWM switching frequency, which leads to an increase of the switching losses. The use of power filters and high switching frequency has to be balanced to achieve reasonable converter costs with acceptable efficiency.

During the last decades, the drawbacks of the two-level converter motivated researchers to develop new converter topologies. A very promising inverter family, called multilevel inverters (MLIs), offer better quality output voltage waveforms with a reduced harmonic content comparing to the conventional two-level inverter topologies, increase the overall voltage and power rating of the converter, and generally mitigate the electromagnetic interferences.

The penetration of multilevel inverters has been steadily increasing due to their widespread usage in manufacturing, transport, energy, high-power drives and other industry applications. Several MLI topologies have been introduced and extensively studied in the literature. Most currently used multilevel topologies can be grouped: cascaded H-bridge (CHB), neutral point clamped (NPC), and flying capacitors (FC).

Energies 2018, 11, 3244; doi:10.3390/en11123244 www.mdpi.com/journal/energies

Multilevel inverters were initiated by the invention of the so-called NPC inverter in 1981 by Nabae et al. [1]. The NPC inverter uses a single DC bus subdivided into a number of voltage levels by a series string of capacitors. The voltages across the individual switches are clamped by diodes at the voltage level of only one capacitor of the series DC-link string. The major difficulty associated with control of the diode-clamped inverter is the balancing of the capacitor voltages [2,3]. To achieve that, many modulation techniques have been developed [4–8]. In particular, carrier-based modulation and space vector modulation (SVM) strategies, similar to those employed for conventional two-level three-phase inverters, can be readily modified and extended to fulfill the multilevel NPC requirements.

An essential part of MLI design is the selection of DC-link capacitors. The capacitors are a sensitive element of the inverter and a common source of failures. So far, regarding two-level converter systems, some papers have investigated the minimum DC-link capacitance and proposed methods for its size reduction [9,10]. Recently, based on the DC-link voltage analysis and considering both low- and/or high-frequency DC voltage components, simple and effective guidelines for designing the DC-link capacitor have been presented in [11] for single-phase H-bridge inverter, and in [12] for three-phase three-level flying capacitor inverter. Methods used to derive expressions for RMS value and harmonic spectrum of the capacitor current in two-level inverters, are extended to the three-level inverters in [13].

An analytical expression for calculating RMS current through the DC-link capacitor in a three-level NPC inverter is given in [14]. The analysis of the DC-link capacitor current in three-level NPC and CHB inverters and a new numerical approach for calculating the RMS value of the capacitor current is proposed in [15].

Evaluation of the low-frequency neutral-point voltage oscillations in the three-level NPC inverter using space vector modulation (SVM) techniques has been analyzed in [16]. A novel modulation strategy for the NPC inverter is proposed in [17] to overcome one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point. The proposed modulation strategy can completely remove this oscillation for all the operating conditions and for any kind of loads, even unbalanced and nonlinear loads.

Nowadays, NPC inverters are the most widely used three-level inverter topologies in the industrial applications, considering both the conventional and the T-type configurations (Figure1).

In order to choose the most suitable topology and hereby increase power efficiency, the comparison between of conventional NPC and T-type inverters has been investigated and reported in the literature [18], also considering the loss evaluation. An efficiency comparison of both over-mentioned topologies is presented in [19] and the result shows that the T-type inverter is generally more efficient at lower switching frequencies.

Energies 2018, 11, x FOR PEER REVIEW 3 of 19

input current. Section 4 presents the analysis of the capacitor voltage switching ripple. Section 5 defines the guidelines for a preliminary design of the DC-link capacitors. In Section 6 simulation and experimental verifications have been reported, and Section 7 presents the conclusion.

2. System Configuration and Modulation Principles

2.1. System Configuration

The circuit scheme of a three-level three-phase neutral point clamped inverter (NPC) is shown in Figure 1, for both conventional and T-type configurations. It consists of a DC voltage source (V^s) with series RL impedance, representing either a simplified model of a real DC source or a DC filter (series reactor). Each leg of the inverter is composed of four power switches (for leg A: S^A(1) to S^A(4), the same for legs B and C). Two capacitors C¹ and C² are connected to the neutral point of the inverter and serve as a voltage divider. For proper operation of the NPC inverter, the neutral point must be kept at one half of DC-link voltage by using a proper modulation strategy able to achieve voltage balancing between the capacitors.

ia ib ic

Vs

A B C

C1

C2

Rs

is Ls

SA(1)

SA(2)

SA(3)

SA(4) Vdc

v1

v2

i+

i− A+ i

−A i

−A i

i− i+

+A i

A B C

C1

C2

Rs is Ls

SA(1)

SA(3)

SA(4)

SA(2)

ia ib ic

Vs Vdc

v1

v2

Figure 1. Circuit schemes of the three-phase three-level neutral point clamped (NPC) inverter:

conventional type (left side) and T-type (right side).

2.2. Modulation Principles

In case of balanced modulation and within the linear modulation range, the output voltages normalized by Vdc and averaged over the switching period (Tsw = 1/fsw) correspond to the modulating signals [20]:









+

= +

− ϑ

=

+

= +

− ϑ

=

+

= + ϑ

=

π π

m m

m m

m m

C u C m

u

C u C m

u

C u C m

u

C* 43

C

*B 23

B

*A A

) ( sin

) ( sin

) ( sin

. (1)

where ϑ = ωt, ω is the fundamental angular frequency (ω = 2πf), f is the fundamental frequency, m is the inverter modulation index, u_i^* are the normalized reference output voltages of each phase (i = A, B or C) and C^m represents the injected common mode signal.

The voltages across the two capacitors C1 and C2 can be spontaneously regulated to half of the DC-link voltage by the use of proper modulation technique with self-balancing capability.

Correspondingly, the following averaged switching functions for the upper and lower switches

) 1 (i

S and S can be written (averaging is denoted by overline): ⁽_i⁴⁾







+

−

= +

=

i i i

i i i

u u S

u u S

) 4 (

) 1 (

. (2)

With reference to the modulation (1) and considering phase A, the averaged switching functions of the upper and the lower switches, Equation (2), become:

Figure 1. Circuit schemes of the three-phase three-level neutral point clamped (NPC) inverter:

conventional type (left side) and T-type (right side).

Energies 2018, 11, 3244 3 of 20

The analysis of inverter DC-link input current and voltage is essential for sizing and designing the DC-link capacitor since it directly impacts the price, the lifetime and the failure rate of a converter system. A DC-link capacitor has to deal with the harmonics of the inverter input current and to avoid the high DC-link voltage ripple appearance. In general, the low-frequency voltage ripple component is more important for the required capacitance design since it has a higher value comparing to the switching frequency voltage ripple component. Although correctly sizing the DC-link capacitances is important to control the magnitude of the low-frequency voltage ripple, it is not the only thing that must be considered.

The calculation of low-frequency input current and input voltage ripples on DC-link capacitors have been analyzed and presented in the literature by other authors [15,16]. The evaluation of voltage switching ripple for the NPC converters has not been reported yet. The analysis of the voltage switching ripple in DC-link capacitors of three-level three-phase NPC inverters, applicable to both conventional and T-type configurations (Figure1), is presented in this paper, with reference to different carrier-based PWM techniques. The peak-to-peak capacitor voltage switching ripple amplitudes are analytically determined as a function of modulation index and output phase angle. Based on the limitation on the peak-to-peak capacitor voltage switching ripple amplitudes, simple and practical expressions for sizing the capacitors have been proposed.

The paper is organized as follows. Section 2introduces the system configuration and the modulation principles. Section3presents the analysis of low-frequency and switching frequency input current. Section4presents the analysis of the capacitor voltage switching ripple. Section5defines the guidelines for a preliminary design of the DC-link capacitors. In Section6simulation and experimental verifications have been reported, and Section7presents the conclusion.

2. System Configuration and Modulation Principles

2.1. System Configuration

The circuit scheme of a three-level three-phase neutral point clamped inverter (NPC) is shown in Figure1, for both conventional and T-type configurations. It consists of a DC voltage source (Vs) with series RL impedance, representing either a simplified model of a real DC source or a DC filter (series reactor). Each leg of the inverter is composed of four power switches (for leg A: S_A⁽¹⁾to S_A⁽⁴⁾, the same for legs B and C). Two capacitors C1and C2are connected to the neutral point of the inverter and serve as a voltage divider. For proper operation of the NPC inverter, the neutral point must be kept at one half of DC-link voltage by using a proper modulation strategy able to achieve voltage balancing between the capacitors.

2.2. Modulation Principles

In case of balanced modulation and within the linear modulation range, the output voltages normalized by Vdcand averaged over the switching period (Tsw= 1/fsw) correspond to the modulating signals [20]:







uA=m sin(ϑ) +Cm=u_A^∗ +Cm

uB=m sin(ϑ−^2π₃ ) +Cm=u^∗_B+Cm

u_C=m sin(ϑ−^4π₃ ) +Cm=u^∗_C+Cm

. (1)

where ϑ = ωt, ω is the fundamental angular frequency (ω = 2πf ), f is the fundamental frequency, m is the inverter modulation index, u^∗_i are the normalized reference output voltages of each phase (i = A, B or C) and Cmrepresents the injected common mode signal.

The voltages across the two capacitors C1 and C2 can be spontaneously regulated to half of the DC-link voltage by the use of proper modulation technique with self-balancing capability.

Correspondingly, the following averaged switching functions for the upper and lower switches S⁽¹⁾_i and S⁽⁴⁾_i can be written (averaging is denoted by overline):

( S⁽¹⁾_i =ui+|ui|

S⁽⁴⁾_i = −ui+|ui| ^{. (2)}

With reference to the modulation (1) and considering phase A, the averaged switching functions of the upper and the lower switches, Equation (2), become:

( S⁽¹⁾_A =m sin(ϑ) +Cm+|m sin(ϑ) +Cm|

S⁽⁴⁾_A = −m sin(ϑ) +Cm+|m sin(ϑ) +Cm| ^{. (3)} Due to the modulation symmetry among the three phases, the switching functions for the phases B and C are readily obtained considering the phase displacement of the normalized output voltages given in Equation (1).

In case of sinusoidal PWM (SPWM), the injected common-mode signal is zero:

Cm=0. (4)

However, in case of centered PWM (CPWM), the injected common-mode signal is:

Cm= −¹

2(max(u^∗_A, u^∗_B, u^∗_C) +min(u^∗_A, u^∗_B, u^∗_C)). (5) In this last case, Cmcan be rewritten as:

Cm= ¹ 2m







sin ϑ,−^π₆ ≤ϑ≤ ^π₆,^5π₆ ≤ϑ≤ ^7π₆ sin ϑ+^2π_3
, ^π₆ ≤ϑ≤ ^π₂,^7π₆ ≤ϑ≤ ^3π₂ sin ϑ−^2π₃
, ^π₂ ≤ϑ≤ ^5π₆ ,^3π₂ ≤ϑ≤ ^11π₆

. (6)

A straightforward method to implement carrier-based optimized centered PWM (OCPWM) for three-phase three-level inverters has been proposed in [20]. The procedure is based on applying the traditional min/max centering separately to pivot voltages and residual two-level voltages.

Pivot voltages are determined by a simple polarity combination of reference voltages. The resulting common-mode voltage that has to be injected in reference voltages is determined in few simple steps as described in the following equations:

Cm= −¹ 2



max(u^p_A, u_B^p, u^p_C) +_min(u_A^p, u_B^p, u^p_C)^−¹ 2



max(u^2L_A, u^2L_B , u^2L_C) +_min(u^2L_A, u^2L_B , u^2L_C)^ ₍₇₎ being











u_A^p = ¹₄^hsign(u^∗_A) −¹₃ sign(u_A^∗) +sign(u^∗_B) +sign(u_C^∗)
ⁱ u_B^p= ¹₄^hsign(u^∗_B) −¹₃ sign(u^∗_A) +sign(u^∗_B) +sign(u^∗_C)
ⁱ u_C^p = ¹₄^hsign(u^∗_C) −¹₃ sign(u^∗_A) +sign(u^∗_B) +sign(u^∗_C)
ⁱ

(8)







u^2L_A =u^∗_A−u^p_A u^2L_B =u^∗_B−u^p_B u^2L_C =u^∗_C−u_C^p

(9)

Figure2shows the three carrier-based modulations considered in this paper.

Energies 2018, 11, 3244 5 of 20

Energies 2018, 11, x FOR PEER REVIEW 5 of 19

Si(1)

, Si(3)

S_i⁽²⁾, S_i⁽⁴⁾ ui

Figure 2. Carrier-based PWM modulation logic for each leg (i) of NPC inverters: SPWM (red trace), CPWM (blue trace), and OCPWM (green trace) in case of m = 0.4. Underline denotes complementary.

3. Input Current Analysis

Input Current Components

With reference to Figure 1, the instantaneous input currents i⁺(t) and i^–(t) are composed of the averaged value over the switching period, i⁺ and i⁻, and the switching frequency component,

∆i and + ∆i . Similarly, ⁻ i and ⁺ i consist of DC component over the fundamental period, I^{− dc}, and the alternating low-frequency component, i~ and ⁺ i~ , leading to: ⁻







∆ + +

=

∆ +

=

∆ + +

=

∆ +

=

−

−

−

−

−

+ + +

+ +

i i I i i t i

i i I i i t i

dc dc

) ~ (

) ~

( (10)

In case of balanced load and neglecting the output current ripple, the corresponding three-phase output currents can be written as:









ϕ

−

− ϑ

=

ϕ

−

− ϑ

=

) ϕ

− ϑ

=

π π

) (

sin

) (

sin ( sin

43 c

23 b

a

ac ac ac

I i

I i

I i

(11)

where Iac is the output current amplitude and ϕ is the power phase angle.

The averaged component (over the switching period) of each leg input current can be determined by multiplying the switching function of upper or lower switch of each phase by the corresponding output current. In the case of leg A it leads to:







−

=

=

− +

A a A

A a A

) 4 ( ) 1 (

i S i

i S

i (12)

By introducing Equations (3) and (11) in Equation (12), the averaged currents of the upper and lower switch of the leg A become:







+ ϑ +

− ϑ

− ϕ

− ϑ

=

+ ϑ +

+ ϑ ϕ

− ϑ

=

− +

] ) ( sin sin

[) sin(

] ) ( sin )

( sin [) sin(

A A

m m

ac

m m

ac

C m

C m

I i

C m

C m

I

i (13)

The total input currents i and ⁺ i can be calculated as the sum of the three leg currents as: ⁻







−

−

−

=

+ +

=

− +

C c B b

A a

C c B b

A a

) 4 ( ) 4 ( ) 4 (

) 1 ( ) 1 ( ) 1 (

i S i S i S i

i S i S i S

i (14)

Due to the three-phase symmetry of modulation and output currents within the fundamental period T, both input currents have a periodicity of T/3. As a consequence, the analysis can be restricted to an angle range of 2π/3, and all the input harmonics are multiple of 3. i.e., apart from the DC component, the lowest harmonic order component is the 3rd.

Figure 2.Carrier-based PWM modulation logic for each leg (i) of NPC inverters: SPWM (red trace), CPWM (blue trace), and OCPWM (green trace) in case of m = 0.4. Underline denotes complementary.

3. Input Current Analysis

Input Current Components

With reference to Figure1, the instantaneous input currents i⁺(t) and i^–(t) are composed of the averaged value over the switching period, i⁺and i⁻, and the switching frequency component,∆i⁺and

∆i⁻. Similarly, i⁺and i⁻consist of DC component over the fundamental period, Idc, and the alternating low-frequency component, ei⁺and ei⁻, leading to:

( i⁺(t) =i⁺+∆i⁺ =Idc+ei⁺+∆i⁺

i⁻(t) =i⁻+∆i⁻ =I_dc+ei⁻+∆i⁻ (10) In case of balanced load and neglecting the output current ripple, the corresponding three-phase output currents can be written as:







ia=Iacsin(ϑ−ϕ) ib =Iacsin ϑ−^2π₃ −ϕ) ic= Iacsin

ϑ−^4π₃ −ϕ)

(11)

where Iacis the output current amplitude and ϕ is the power phase angle.

The averaged component (over the switching period) of each leg input current can be determined by multiplying the switching function of upper or lower switch of each phase by the corresponding output current. In the case of leg A it leads to:

( i⁺_A =S⁽¹⁾_A ia

i⁻_A = −S⁽⁴⁾_A ia

(12)

By introducing Equations (3) and (11) in Equation (12), the averaged currents of the upper and lower switch of the leg A become:

( i⁺_A= Iacsin(ϑ−ϕ)[m sin(ϑ) +Cm+|m sin(ϑ) +Cm|]

i⁻_A= Iacsin(ϑ−ϕ)[−m sin ϑ−Cm+|m sin(ϑ) +Cm|] ⁽¹³⁾ The total input currents i⁺and i⁻can be calculated as the sum of the three leg currents as:

( i⁺=S_A⁽¹⁾ia+S⁽¹⁾_B i_b+S⁽¹⁾_C ic

i⁻= −S⁽⁴⁾_A ia−S_B⁽⁴⁾i_b−S_C⁽⁴⁾ic

(14)

Due to the three-phase symmetry of modulation and output currents within the fundamental period T, both input currents have a periodicity of T/3. As a consequence, the analysis can be restricted

to an angle range of 2π/3, and all the input harmonics are multiple of 3. i.e., apart from the DC component, the lowest harmonic order component is the 3rd.

With reference to the phase angle range 2π/3≤ϑ≤4π/3, two sub-ranges π/3 can be identified.

Considering Equations (2), (11) and (14), the input currents i⁺and i⁻can be expressed as:

i⁺ =

( S⁽¹⁾_A ia+S_B⁽¹⁾i_b, ^2π₃ ≤ϑ≤π

S⁽¹⁾_B i_b, π≤ϑ≤ ^4π₃ ⁽¹⁵⁾

i⁻ =

( −S⁽⁴⁾_C ic, ^2π₃ ≤ϑ≤π

−S⁽⁴⁾_A ia−S⁽⁴⁾_C ic, π≤ϑ≤ ^4π₃ ⁽¹⁶⁾ Introducing Equations (1), (2), and (11) in Equations (15) and (16), and setting Cm= 0 as in case of SPWM, leads to:

i⁺ =

( mIac2 cos(ϕ) +cos 2ϑ−^2π₃ −ϕ
, ^2π₃ ≤ϑ≤π

mIaccos(ϕ) +cos 2ϑ−^π₃ −ϕ
, π≤ϑ≤ ^4π₃ ⁽¹⁷⁾

i⁻=

( mIaccos(ϕ) −cos 2ϑ−^2π₃ −ϕ
, ^2π₃ ≤ϑ≤π

mIac2 cos(ϕ) −cos 2ϑ−^π₃ −ϕ
, π≤ϑ≤ ^4π₃ ⁽¹⁸⁾ Similarly, replacing Equation (6) in Equation (1) in case of CPWM, input currents i⁺and i⁻can be expressed as

i⁺=















mIac

2

h√

3 sin(2ϑ−ϕ) +sin ^π₆ +ϕ

+_{4 cos}(ϕ)ⁱ, ^2π₃ ≤ϑ≤ ^5π₆

mI_ac 2

h√

3 sin 2ϑ−^π₃ −ϕ

−sin ϕ−^π₆
+4 cos(ϕ)ⁱ, ^5π₆ ≤ϑ≤π

mI_ac 2

√3cos 2ϑ−^π₆ −ϕ

+cos ϕ+^π₆
, π≤ϑ≤ ^7π₆

mIac

2

√3sin(2ϑ−ϕ) +sin ϕ+^π₃
, ^7π₆ ≤ϑ≤ ^4π₃

(19)

i⁻=



















mI_ac 2

h−√

3 sin(2ϑ−ϕ) −sin ^π₆ +ϕ

+2 cos(ϕ)ⁱ, ^2π₃ ≤ϑ≤ ^5π₆

mI_ac 2

h−√

3 sin 2ϑ−^π₃ −ϕ

+sin ϕ−^π₆
+2 cos(ϕ)ⁱ, ^5π₆ ≤ϑ≤π

mI_ac 2

h−√

3 cos 2ϑ−^π₆ −ϕ

−√

3 cos ϕ+^π₆
+6 cos(ϕ)ⁱ, π≤ϑ≤ ^7π₆

mI_ac 2

h−√

3 sin(2ϑ−ϕ) −√

3 sin ϕ+^π₃
+6 cos(ϕ)ⁱ, ^7π₆ ≤ϑ≤ ^4π₃

(20)

Although the above analytical calculations are based on SPWM and CPWM, the analysis could be readily extended to other PWM techniques, such as OCPWM, leading to more complex expressions not presented in this paper.

Consequently, the low-frequency input current components are readily determined in case of SPWM as:

I_dc= ³

2mIaccos(ϕ) (21)

ei⁺ = ( ₁

2mIaccos(ϕ) +2 cos 2ϑ−^2π₃ −ϕ
, ^2π₃ ≤ϑ≤π

−¹₂mIaccos(ϕ) −2 cos 2ϑ−^π₃ −ϕ
, π≤ϑ≤ ^4π₃ ⁽²²⁾

ei⁻ =

( −¹₂mIaccos(ϕ) +2 cos 2ϑ−^2π₃ −ϕ
, ^2π₃ ≤ϑ≤π

1

2mIaccos(ϕ) −2 cos 2ϑ−^π₃ −ϕ
, π≤ϑ≤ ^4π₃ ⁽²³⁾

Energies 2018, 11, 3244 7 of 20

In the case of CPWM, the low-frequency input currents are expressed as:

ei⁺=















mIac

2

h√

3 sin(2ϑ−ϕ) +sin ^π₆ +ϕ

+cos(ϕ)ⁱ, ^2π₃ ≤ϑ≤ ^5π₆

mIac

2

h√

3 sin 2ϑ−^π₃ −ϕ

−sin ϕ−^π₆
+cos(ϕ)ⁱ, ^5π₆ ≤ϑ≤π

mIac

2

√3cos 2ϑ−^π₆ −ϕ

+cos ϕ+^π₆
−3 cos(ϕ), π≤ϑ≤ ^7π₆

mI_ac 2

√3sin(2ϑ−ϕ) +sin ϕ+^π₃
−3 cos(ϕ), ^7π₆ ≤ϑ≤ ^4π₃

(24)

ei⁻=



















−^mI₂^ach√

3 sin(2ϑ−ϕ) +sin ^π₆ +ϕ

+cos(ϕ)ⁱ, ^2π₃ ≤ϑ≤ ^5π₆

−^mI₂^ach√

3 sin 2ϑ−^π₃ −ϕ

−sin ϕ−^π₆
+cos(ϕ)ⁱ, ^5π₆ ≤ϑ≤π

−^mI₂^ach√

3 cos 2ϑ−^π₆ −ϕ
+√

3 cos ϕ+^π₆
−3 cos(ϕ)ⁱ, π≤ϑ≤ ^7π₆

−^mI₂^ach√

3 sin(2ϑ−ϕ) +√

3 sin ϕ+^π₃
−3 cos(ϕ)ⁱ, ^7π₆ ≤ϑ≤ ^4π₃

(25)

4. Input Voltage Analysis

4.1. Input Voltage Components

Based on the analysis of the inverter input current ripple components, the instantaneous voltages v1and v2across DC-link capacitors can be written as:

( v1=V1+v_e1+_∆v1

v₂=V₂+v_e2+_∆v2 ⁽²⁶⁾

where V1and V2are the DC components averaged over the fundamental period,ve1andve2are the alternating low-frequency ripple components, and∆v1and∆v2are the switching frequency ripple components of the voltages across capacitors C1and C2, respectively. Being the low-frequency ripple components widely studied in literature, the analysis is focused on the switching ripple component.

4.2. Peak-to-Peak Voltage Switching Ripple Evaluation

In order to calculate the voltage switching ripple of DC-link capacitors, the amount of the switching frequency component of currents∆i1and∆i2circulating through the DC-link capacitor C₁and C₂should be determined. Assuming that the DC source impedance at the switching frequency is much higher than the capacitor’s reactance, the whole current component∆i⁺and∆i^–are circulating through the capacitors C1and C2, i.e.,∆i1=∆i⁺and∆i2=∆i⁻. In this case, the corresponding DC voltage variations (peak-to-peak) over the sub-periods [0–∆t1] and [0–∆t2] can be expressed as

∆V1= ¹ C₁

∆t1

Z 0

∆i⁺dt,∆V2= ¹ C2

∆t2

Z 0

∆i⁻dt. (27)

being∆t1and∆t2specific switching time intervals. The instantaneous input current is considered constant within each considered time interval.

Due to the periodicity of the input currents i⁺ and i^–, the evaluation of peak-to-peak voltage ripple is limited to the phase angle range 2π/3≤ϑ≤4π/3. Analyzing the voltage ripple, two cases have been identified: the first case considering zero phase angle (ϕ = 0^◦) and the second considering ϕ= 60^◦. The peak-to-peak voltage switching ripple of capacitors has been analytically calculated as:

In case of ϕ = 0^◦:

∆V1= ^Tsw C₁









1−S⁽¹⁾_A 

i⁺, ^2π₃ ≤ϑ≤ ^5π₆

1−S⁽¹⁾_B 

i⁺, ^5π₆ ≤ϑ≤ ^4π₃ ⁽²⁸⁾

∆V2= ^Tsw C2







1−S⁽⁴⁾_C 

i⁻, ^2π₃ ≤ϑ≤ ^7π₆



1−S⁽⁴⁾_A 

i⁻, ^7π₆ ≤ϑ≤ ^4π₃ ⁽²⁹⁾

In case of ϕ = 60^◦:

∆V1= ^Tsw C₁













1−S⁽¹⁾_A 

i⁺, ^2π₃ ≤ϑ≤ ^5π₆

ia+i_b−i⁺

S⁽¹⁾_A , ^5π₆ ≤ϑ≤π

1−S⁽¹⁾_B 

i⁺, ^5π₆ ≤ϑ≤ ^4π₃

(30)

∆V2= ^Tsw C2







1−S_C⁽⁴⁾

i⁻, ^2π₃ ≤ϑ≤ ^7π₆

−ic−ia−i⁻

S⁽⁴⁾_C , ^7π₆ ≤ϑ≤ ^4π₃ ⁽³¹⁾ being S⁽¹⁾_i and S⁽⁴⁾_i the switching function for the upper and lower switches of phase i (being i = A, B or C), given by Equation (2). The total averaged input currents i⁺ and i⁻ can be calculated by Equations (17) and (18) in case of sinusoidal PWM, and by Equations (19) and (20) in case of centered PWM. In case of optimized centered PWM the input currents can be calculated introducing Equations (2), (7) and (11) in Equations (15) and (16), leading to more complex developments.

Equations (28)–(31) suggest normalization for∆V1and∆V2, as follow:

∆V1= ^Iac

fswC1∆U1, ∆V2= ^Iac

fswC2∆U2. (32)

being∆U1and∆U2the normalized peak-to-peak voltage switching ripple amplitude of capacitors.

Figure3shows the distribution of the normalized peak-to-peak voltage switching ripple calculated based on Equations (28), (29), (30) and (31) over the period [0, 120^◦]. Two modulation indices have been selected, m = 0.3 and m = 0.5 and two output phase angles are considered, ϕ = 0 and ϕ = 60^◦.

Energies 2018, 11, x FOR PEER REVIEW 9 of 19

Figure 3 shows the distribution of the normalized peak-to-peak voltage switching ripple calculated based on Equations (28), (29), (30) and (31) over the period [0, 120°]. Two modulation indices have been selected, m = 0.3 and m = 0.5 and two output phase angles are considered, ϕ = 0 and ϕ = 60°.

ϕ = 0 ϕ= 60°

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(a)

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(b)

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(c)

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(d)

Figure 3. Normalized peak-to-peak voltage ripple amplitude across the capacitors over the period [0, 120°] for two modulation indices m = 0.3 (a,b) and m = 0.5 (c,d) and output phase angles ϕ = 0 (a,c) (left) and 60° (b,d) (right) in case of SPWM (red), CPWM (blue) and OCPWM (green).

Figure 3 presents the normalized peak-to-peak voltage ripple amplitude across the upper capacitor since the normalized peak-to-peak voltage ripple amplitude across the lower capacitor has exactly the same profile with a phase shift corresponding to 60° (1/2 of the considered period).

According to Figure 3, it can be seen a wide excursion of the normalized peak-to-peak voltage ripple amplitude, generally ranging between 0 (min) and 0.25 (max). Despite there are evident differences in the voltage switching ripple envelope profile among the three modulation strategies, it cannot be identified a modulation clearly better than the others from this point of view. This consideration is also supported by the diagrams presented in Figure 4, representing the maximum of the normalized peak-to-peak ripple amplitude, calculated numerically, over the whole modulation index range, for ϕ = 0°, 30°, 60°, and 90°, considering SPWM, CPWM, and OCPWM. Again, these three modulation techniques give similar and comparable results also with reference to the maximum of the peak-to-peak voltage switching ripple. For all the cases, the absolute maximum of normalized peak-to-peak voltage ripple amplitude can be assumed as 0.25.

0 0.1 0.2 0.3

0 0.1 0.2 0.3 0.4 0.5 0.6

ϕ=0° ϕ=30° ϕ=60° ϕ=90°

max

V1

∆

m

(a)

0 0.1 0.2 0.3

0 0.1 0.2 0.3 0.4 0.5 0.6

ϕ=0° ϕ=30° ϕ=60° ϕ=90°

max V1

∆

m

(b)

0 0.1 0.2 0.3

0 0.1 0.2 0.3 0.4 0.5 0.6

ϕ=0° ϕ=30° ϕ=60° ϕ=90°

max

V1

∆

m (c)

Figure 4. Maximum peak-to-peak value of the normalized voltage switching ripple vs. modulation index m in case of (a) sinusoidal pulse-width modulation (SPWM), (b) centered PWM (CPWM) and (c) optimized centered PWM (OCPWM) for different output phase angles.

Figure 3.Normalized peak-to-peak voltage ripple amplitude across the capacitors over the period [0, 120^◦] for two modulation indices m = 0.3 (a,b) and m = 0.5 (c,d) and output phase angles ϕ = 0 (a,c) (left) and 60^◦(b,d) (right) in case of SPWM (red), CPWM (blue) and OCPWM (green).

Figure3presents the normalized peak-to-peak voltage ripple amplitude across the upper capacitor since the normalized peak-to-peak voltage ripple amplitude across the lower capacitor has exactly the same profile with a phase shift corresponding to 60^◦(1/2 of the considered period).

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According to Figure 3, it can be seen a wide excursion of the normalized peak-to-peak voltage ripple amplitude, generally ranging between 0 (min) and 0.25 (max). Despite there are evident differences in the voltage switching ripple envelope profile among the three modulation strategies, it cannot be identified a modulation clearly better than the others from this point of view.

This consideration is also supported by the diagrams presented in Figure4, representing the maximum of the normalized peak-to-peak ripple amplitude, calculated numerically, over the whole modulation index range, for ϕ = 0^◦, 30^◦, 60^◦, and 90^◦, considering SPWM, CPWM, and OCPWM. Again, these three modulation techniques give similar and comparable results also with reference to the maximum of the peak-to-peak voltage switching ripple. For all the cases, the absolute maximum of normalized peak-to-peak voltage ripple amplitude can be assumed as 0.25.

Energies 2018, 11, x FOR PEER REVIEW 9 of 19

Figure 3 shows the distribution of the normalized peak-to-peak voltage switching ripple calculated based on Equations (28), (29), (30) and (31) over the period [0, 120°]. Two modulation indices have been selected, m = 0.3 and m = 0.5 and two output phase angles are considered, ϕ = 0 and ϕ = 60°.

ϕ = 0 ϕ= 60°

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(a)

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(b)

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(c)

0 0 0.05

0.1 0.15 0.2 0.25

120°

U1

∆

ϑ

(d)

Figure 3. Normalized peak-to-peak voltage ripple amplitude across the capacitors over the period [0, 120°] for two modulation indices m = 0.3 (a,b) and m = 0.5 (c,d) and output phase angles ϕ = 0 (a,c) (left) and 60° (b,d) (right) in case of SPWM (red), CPWM (blue) and OCPWM (green).

Figure 3 presents the normalized peak-to-peak voltage ripple amplitude across the upper capacitor since the normalized peak-to-peak voltage ripple amplitude across the lower capacitor has exactly the same profile with a phase shift corresponding to 60° (1/2 of the considered period).

According to Figure 3, it can be seen a wide excursion of the normalized peak-to-peak voltage ripple amplitude, generally ranging between 0 (min) and 0.25 (max). Despite there are evident differences in the voltage switching ripple envelope profile among the three modulation strategies, it cannot be identified a modulation clearly better than the others from this point of view. This consideration is also supported by the diagrams presented in Figure 4, representing the maximum of the normalized peak-to-peak ripple amplitude, calculated numerically, over the whole modulation index range, for ϕ = 0°, 30°, 60°, and 90°, considering SPWM, CPWM, and OCPWM. Again, these three modulation techniques give similar and comparable results also with reference to the maximum of the peak-to-peak voltage switching ripple. For all the cases, the absolute maximum of normalized peak-to-peak voltage ripple amplitude can be assumed as 0.25.

0 0.1 0.2 0.3

0 0.1 0.2 0.3 0.4 0.5 0.6

ϕ=0° ϕ=30° ϕ=60° ϕ=90°

max

V1

∆

m

(a)

0 0.1 0.2 0.3

0 0.1 0.2 0.3 0.4 0.5 0.6

ϕ=0° ϕ=30° ϕ=60° ϕ=90°

max V1

∆

m

(b)

0 0.1 0.2 0.3

0 0.1 0.2 0.3 0.4 0.5 0.6

ϕ=0° ϕ=30° ϕ=60° ϕ=90°

max

V1

∆

m (c)

Figure 4. Maximum peak-to-peak value of the normalized voltage switching ripple vs. modulation index m in case of (a) sinusoidal pulse-width modulation (SPWM), (b) centered PWM (CPWM) and (c) optimized centered PWM (OCPWM) for different output phase angles.

Figure 4.Maximum peak-to-peak value of the normalized voltage switching ripple vs. modulation index m in case of (a) sinusoidal pulse-width modulation (SPWM), (b) centered PWM (CPWM) and (c) optimized centered PWM (OCPWM) for different output phase angles.

5. Dc-link Preliminary Capacitor Design

Based on the analysis of capacitor voltage ripple components, simple and effective guidelines for a preliminary design of the capacitors C1 and C2 are proposed in this section. In particular, the capacitances can be calculated taking into account requirements or restrictions referred to the switching frequency and/or low-frequency voltage ripple components.

Despite the design of DC-link capacitors in the three-phase three-level inverter has been widely addressed in literature considering always the low-frequency voltage ripple, a guideline for the design of the DC-link capacitors for this multilevel inverter configuration based on the switching voltage ripple has not been developed yet.

In general, the capacitor voltage switching ripple amplitude could have additional specific restrictions to limit switching noise, electromagnetic interferences, and voltage stress on the DC-link.

In this paper, the selection of the DC-link capacitors C₁and C₂can be performed on the basis of the maximum amplitude of the peak-to-peak voltage switching ripple at the switching frequency (that is in the order of kHz).

According to Figure4, it can be noted that the maximum amplitude of the peak-to-peak ripple is determined as:

∆U₁^max=∆U₂^max= ¹

4 (33)

In this case, the capacitances can be readily calculated on the basis of Equations (32) and (33):

C1≥ ¹ 4

Iac

fsw∆V₁^max, C2≥ ¹ 4

Iac

fsw∆V₂^max (34)

6. Results

In order to verify proposed theoretical developments valid for both the considered NPC multilevel inverter configurations (Figure1), numerical simulations and corresponding experimental tests are carried out. Inverter is controlled by carrier-based multilevel PWM (Figure2) with reference to the three considered modulation techniques (SPWM, CPWM, and OCPWM). The switching frequency is set 2.5 kHz to better emphasize the switching ripple components, and two different output phase angles (0 and 60^◦) are considered, as for the specific analytical developments. The main circuit parameters are summarized in Table1for both simulations and experiments.

Table 1.Simulation/experiment circuit parameters.

Label Description Parameters

Vs DC voltage source 100 V

Rs DC source resistance 5Ω

L_s DC source inductance 10.15 mH

C₁, C₂ DC-link capacitors 1.12 mF

f, fsw fundamental and switching frequencies 50 Hz, 2.5kHz

6.1. Simulation Results

Simulation results are carried out by implementing the power circuit scheme and the PWM techniques by Matlab/Simulink, considering SPWM, CPWM, and OCPWM.

The first simulation tests (Figures5and6) are concerning the input inverter currents. In this case, unity sinusoidal output current (Iac= 1A) are considered to easily verify the analytical developments presented in Section3, with specific reference to the considered output phase angles ϕ = 0^◦and ϕ = 60^◦.

Energies 2018, 11, x FOR PEER REVIEW 11 of 19

in case of m = 0.4 and for two cases of output phase angles ϕ = 0° (Figure 5) and ϕ = 60° (Figure 6). The bottom traces in Figures 5 and 6 show the total input current, with emphasis to instantaneous value i (blue trace) and its averaged value over the switching period + i (red trace). The low-frequency ⁺ current component (green trace) is determined analytically in both cases of SPWM and CPWM by Equations (22) and (24), respectively, and is calculated by replacing Equations (2), (7), and (11) in Equation (15), in the case of OCPWM.

The numerical results generally show a perfect matching with the theoretical values. The small delay between averaged and theoretical currents (Tsw/2) is due to the averaging process itself.

-1 -0.5 0 0.5 1

Leg dc-link current (A)

-1 -0.5 0 0.5 1

-1 -0.5 0 0.5 1

0.02 0.025 0.03 0.035 0.04

-1 -0.5 0 0.5 1

Total input current (A)

0.02 0.025 0.03 0.035 0.04

-1 -0.5 0 0.5 1

0.02 0.025 0.03 0.035 0.04

-1 -0.5 0 0.5 1

t (s) t (s) t (s)

Figure 5. One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4, I^ac = 1A and ϕ = 0°.

0 02 0 02 0 03 0 03 0 0

-1 -0.5 0 0.5 1

Leg dc-link current (A)

-1 -0.5 0 0.5 1

-1 -0.5 0 0.5 1

0.02 0.025 0.03 0.035 0.04

-1 -0.5 0 0.5 1

Total input current (A)

0.02 0.025 0.03 0.035 0.04

-1 -0.5 0 0.5 1

0.02 0.025 0.03 0.035 0.04

-1 -0.5 0 0.5 1

t (s) t (s) t (s)

Figure 6. One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4, Iac = 1A and ϕ = 60°.

The second group of simulation tests is concerning the switching voltage ripple across the two DC-link capacitors. In this case, the load circuit model is corresponding to the real experimental setup, made with the purpose to easily adapt the output phase angles to the considered cases (ϕ = 0 and ϕ = 60°), according to Figure 7. The corresponding circuit parameters are given in Table 2.

The voltage switching ripple is determined by filtering away the low-frequency components form the instantaneous capacitor voltages.

Figure 5. One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4, Iac= 1A and ϕ = 0^◦.

The top traces in Figures5and6show the simulation results comparing the instantaneous input current of leg A i⁺_A (blue trace) with its averaged value over the switching period i⁺_A (red trace), and the corresponding low-frequency current component calculated by Equation (13) (green trace) in case of m = 0.4 and for two cases of output phase angles ϕ = 0^◦(Figure5) and ϕ = 60^◦(Figure6).

The bottom traces in Figures5and6show the total input current, with emphasis to instantaneous value i⁺(blue trace) and its averaged value over the switching period i⁺(red trace). The low-frequency current component (green trace) is determined analytically in both cases of SPWM and CPWM by Equations (22) and (24), respectively, and is calculated by replacing Equations (2), (7), and (11) in Equation (15), in the case of OCPWM.