Study and characterization of the APiX sensor for particle tracking

Universit` a degli Studi di Padova

DIPARTIMENTO DI FISICA “G. GALILEI”

Corso di laurea in Magistrale in Fisica

Tesi di Laurea Magistrale

Study and characterization of the APiX sensor for particle tracking

applications

Candidato:

Giuseppe SPADONI

Matricola 1106977

Relatore:

Prof. Gianmaria COLLAZUOL

Anno Accademico 2015-2016

A mia sorella.

A mio fratello.

A chi mi vuol bene.

iii

Abstract

A prototype of a new kind of silicon pixel sensor is studied in this work: the APiX (Avalanche PiXel sensor). The device, formed by two vertically-aligned pixel arrays, exploits the coincidence between two simultaneous avalanche events to discriminate between particle-triggered detections and dark counts. A proof-of-concept two-layer sensor with per-pixel coincidence circuits was designed and fabricated in a 150 nm CMOS process and vertically integrated through bump bonding. The sensor includes a 48 x 16 pixel array with 50 µm x 75 µm pixels.

APiX is made of an array of avalanche pixels, that has been designed in a 180 nm CMOS process with high voltage (HV) option. This is a single poly, up to six metal technology. The array includes sensors with a pitch of 50µm×100µm, different size (20µm×20µm, 30µm×30µm and 45µm×43µm) and based on different process layers. Different versions of the front-end electronics, implementing a passive or active quenching technique to suppress the avalanche, have been monolithically integrated in the same substrate as the detector.

The main purpose of this work is to investigate the characteristics of the technology in view of the fabrication of a dual-tier, low material budget sensor for charged particle detection and present the results from the chip characterization in terms of front-end electronics functionality, dark count rate, breakdown voltage, optical cross-talk, quantum efficiency and tracking efficiency with ionizing particles.

Keywords : APD, SPAD, APIX, noise and particles characterization.

Contents

1 Introduction 1

1.1 Breakdown simulations . . . . 2

1.2 Impact ionization . . . . 5

1.2.1 Many-body problem for photoionization. . . . 6

1.2.2 Ionization rates for p-n junction. . . . 8

1.3 Simple circuit implementation: Recharge and quenching . . . 10

1.3.1 Recharge circuits . . . 10

1.3.2 Quenching circuits. . . 11

1.4 CMOS implementation for SPADs: pixel detectors . . . 13

2 The APiX sensor 17 2.1 The Architecture . . . 18

2.2 Enabling pixels . . . 21

2.3 Data acquisition . . . 22

3 Noise Characterization 25 3.1 Dark Count Rate (DCR) . . . 25

3.1.1 Count-V characteristic and analysis . . . 26

3.2 Optical Noise . . . 30

3.2.1 Horizontal cross-talk on APiXC1 . . . 32

3.2.2 Vertical Cross-talk . . . 35

4 Quantum efficiency and PDE. 37 4.1 Internal efficiency . . . 37

4.1.1 Setup . . . 38

4.1.2 Results . . . 39

4.2 External efficiency . . . 42

4.2.1 Sources . . . 42

4.2.2 Monochromator . . . 43

4.2.3 Calibration and Normalization using PMTs . . . 45

4.2.4 Optical Filters . . . 46

4.2.5 DAQ chain . . . 46

4.2.6 Apparatus limits . . . 46

4.2.7 Results . . . 47

5 Particle characterization. 49 5.1 Characterization with ⁹⁰ Sr source. . . 49

5.1.1 Experimental results . . . 50

5.2 Test beam of APiX at CERN . . . 51

Conclusions 53

v

A Algorithms and firmwares 55

A.1 APiXC2 Enabling firmware ARDUINO DUE (SAM3X8E ARM). . . 55

A.2 APiXC2 DAQ Firmware for ARDUINO DUE (SAM3X8E ARM). . . 56

A.3 APiXC2 DAQ software. . . 58

A.4 APiXC1 Multipurpose firmware for ARDUINO DUE (SAM3X8E ARM) . . . 66

A.5 APiX Matrix Generator . . . 76

A.5.1 Matrix generation with All-On algorithm . . . 76

A.5.2 Matrix generation with Single-On algorithm . . . 79

A.6 APiXC1 DC-Sweep software . . . 81

A.7 APiXC1 Crosstalk DAQ software (NI-DAQ external counter) . . . 82

B Simulations with PENELOPE 89 B.1 Interaction modelling . . . 89

B.1.1 Elastic scattering. . . 89

B.1.2 Inelastic scattering. . . 90

B.1.3 Bremsstrahlung emission. . . 91

B.2 The algorithm . . . 91

Acknowledgement 93

Ringraziamenti 95

Bibliography 98

Chapter 1

Introduction

Semiconductor detectors are widely used in particle, nuclear and medical physics. This thesis work focusses on monolithic detectors for tracking and imaging. Pixelated solid state devices can have very high spatial resolutions O(micron) but need quite complicated and costy front-end and readout electronics. These detectors are made by electronically independent units, called pixel. Recently new kinds of pixelated devices for tracking and imaging were proposed which are based on avalanche diode pixels (APD) as elementay units. Here we studied a new device type, based on APD working in geiger mode.

Avalanche photodiodes (APDs) are p-n, p-i-n o metal-resistor-semiconductors (MRS)[20]

junction, biased near the breakdown voltage. The I-V characteristic is the same as a normal diode, like figure 1.1. For a short time, before injection of the first carrier into the diode’s deple- tion region, the diode will operate with a voltage above the breakdown voltage, with only leakage current flowing through the junction. The injection of an ionizing carrier into the depletion region creates a self-sustaining avalanche of carriers [8].

Figure 1.1: Characteristic of a ideal p-n junction in steady state. [8]

For single photon measurements avalanche photodiodes can be used. That devices are called Single Photon Avalanche Diodes (SPAD). These are specifically made for operating as single photon detectors. Often, they are developed in silicon [6]. Because of the actual know-how in microelectronics an lithography, the research can improve SPAD performance, using diverse architectures.

The fundamental principle of SPADs is the photo-ionization or charged-particle ionization generation. We can say that when a ionizing radiation enters into the active area of the SPAD,

1

the scattering of this radiation with the semiconductors lattice generates a e-hole couple, which is accelerated due to the high electric field imposed by the external bias voltage. The accelerated drift of carriers produce the impact generation and drifting of new ones, that create a current spike.

Figure 1.2: Multiplication and drift regions shown on a p+-n CMOS chip, with the relevant depletion layer and multiplication and drift regions [8]. The figure is not in scale

This phenomenon is generated into the depletion region. For example in figure 1.2 is shown the section of a p+-n CMOS junction. Due to the high doping level, the depletion region is approximately contained only in the n-doped semiconductor. A SPAD depletion layer can be separated in two parts: the drift region, where the expected carrier generation is negligible; and the multiplication region, where nearly of all of the impact ionization takes place. Qualitatively the multiplication region is defined as the smallest possible region with 95% of carrier generation [8]. Ignoring the depletion layer of p-n junction of the substrate, in figure 1.2 we can note that the depletion layer is extended from z 0 to z 1 , the multiplication region is the first third of the layer and the rest is the drift region. Carriers entering from the substrate junction will be swept toward back, and then they not cause ionization since the well-substrate junction’s V bd is larger than that of p+-n well due to the smaller doping in the substrate.

The distinction between the drift and the multiplication regions is important. In fact, if the drift region is quite large, the charge is generated uniformly in the volume, creating a so called space-charge-resistance, and introducing a consistent timing response uncertainty.

The size of multiplication region is important for simulations of generation of avalanches and their propagation and, as a consequence, to predict and develop figures of merit of the detector[8].

Although, the main limit of SPADs detectors in the presence of high-frequency noise back- ground. Pancheri et al [11] has develop a new Geiger-mode SPAD detector, called APiX, based on the vertical integration of avalanche, pixels connected in pairs. Those pixels operates in co- incidence in fully digital mode and with the processing electronics embedded on the chip. The APiX sensor addresses the need to minimize the material budget and related multiple scattering effects in tracking systems requiring a high spatial resolution in the presence of a large occupancy.

Let now focus on the breakdown process simulation, photo-ionization and charged-particle ionization, analyzing cross sections and features of some simulation and results collected in literature.

1.1 Breakdown simulations

APD and SPAD requires an accurate modeling of semiconductor properties at high electric fields. Fine tuned models for impact ionization and other recombination and generation processes are needed to correctly predict the device breakdown voltage and dark count rate.

Breakdown simulation is necessary to simulate the photon detection probability, by estimating

1.1. BREAKDOWN SIMULATIONS 3 quantum efficiency and breakdown probability [15].

CMOS SPADs and APDs have a breakdown voltages near 20 V, so the high-field region width is typically in order of 1µm or narrower and the peak electric field is larger than 5 × 10 ⁵ V /cm . Hayat [9][18] introduced a procedure to estimate the multiplication gain and excess noise factor of avalanche, based on a non-local model. This model was extended to estimate the breakdown probability in Geiger-mode and was applied to devices fabricated in silicon III-V semiconductors.

A series of device simulations were performed for both types of the device. The SPAD’s structure for this simulation is simplified. The structure is shown in figure 1.3. The p+/n-well SPAD is also modeled with an asymmetric abrupt junction. As the n-well doping is not constant, this assumption can lead to some innacurancy in the simulation[9].

Figure 1.3: Simplified 1-D models used in device simulations[15].

The first quantity simulated is the breakdown probability using the local model. This model focuses in the avalanche generation using a probability density functions of avalanche triggering, one for electrons and one for holes.

An electron located at a position x has a probability P e (x) to trigger a breakdown event. Simi- larly, P h (x) is the probability of holes to trigger an avalanche. The breakdown probability P b (x) respect the conditionate probability theorem[15][8]:

P _b (x) = P e (x) + P h (x) − P e (x)P h (x) (1.1) For Hayat and McIntyre[8][9][18], the trigger probability can be obtained by a controlled diffusion equation [8][15]:

dP _e

dx = −(1 − P e )α e [P e + P h − P _e P _h ], (1.2) dP _h

dx = (1 − P _h )α _h [P _e + P _h − P _e P _h ], (1.3) where α e and α h are the ionization rate for electrons and holes, described in section 1.2. The boundary condition is that P e (W ) = 0 and P h (0) = 0 . In this case, however, the electric field can exceed the peak of 5 × 10 ⁵ V /cm , the upper limit described in the first chapter[22].

The results (figure 1.4) show that the model are in agreement to Okuto’s empirical expressions[15]

and Fishburn’s argumentation, which says that the drifting region the in the first 30% of the

total length (red line) of the depletion layer[8].

Figure 1.4: Breakdown probability simulation, using parameter from [15], green is for holes and yellow from electrons. The composed probability is the blue line.

The second step of the simulation is to obtain of breakdown probability and breakdown voltage. To obtain this parameter we are using the dead-space model, created by McIntyre and used for some structure by Hayat [9]. The APiX case is simulated by Pancheri et al. [15].

In dead-space model, an electron (hole) ha to acquire an energy at least equal to electron (hole) ionization threshold energy of the material E ie (E ih ) in order to be able to generate an electron-hole pair by impact ionization. The electron (hole) has to travel a dead-space d e (d h ) before being able to cause impact ionization. Electron and hole dead spaces are related to the electrostatic potential ψ(x) in the space-charge region using the relation:

ψ[x + d _e (x)] − ψ[x] = E _ie

q (1.4)

ψ[x] − ψ[x − d _h (x)] = E _ih

q . (1.5)

Considering an electron generated in x, the probability density function of the distance ξ to the first impact ionization is h e (ξ|x) = 0 for ξ < d e and, for ξ > d e :

h _e (ξ|x) = α e (x + ξ)e ⁻

R

de(x)

α

(x+y)dy

. (1.6)

Similarly for the hole: h h (ξ|x) = 0 for ξ < d h and h h (ξ|x) = α h (x − ξ)e ⁻

R

dh(x)

α

(x−y)dy

(1.7) for ξ > d h . The probability P Z (x) that an electron generated at x originates a finite number of carriers is related to P e (x) by the relation:

P Z (x) = 1 − P e (x), (1.8)

and, in the same way for holes, we have P Y (x) = 1+P _h (x) . in the end the breakdown probability becomes P b (x) = 1 − P Z (x)P Y (x) . P Z and P Y (x) can be estimated by resolving these integral recursive equations:

P Z (x) = Z +∞

W −x

h e (ξ|x)dξ +

Z W −x 0

P _Z ² (x + ξ)P Y (x + ξ)h e (ξ|x)dξ (1.9) P _Y (x) =

Z +∞

x

h _h (ξ|x)dξ + Z x

0

P _Y ² (x − ξ)P Z (x − ξ)h h (ξ|x)dξ (1.10)

1.2. IMPACT IONIZATION 5

Figure 1.5: Simulated electric field, dead spaces and breakdown probabilities at V

= 2V . Left: p+/n-well.

Right: pwell/n-iso[15].

SPAD type p+/nwell pwell/n-iso

nwell doping 6.2 × 10 ¹⁶ cm ⁻³

grading coefficient 3.7 × 10 ²¹ cm ⁻⁴

p neutral region width X P (µm) 0.05 0.63 n neutral region width X N (µm) 0.10 0.18

Simulated V B (V) 16.6 23.7

Simulated temperature profile(V/K) 0.0099 0.0132

Table 1.1: Summary of SPAD model parameters and simulation results[15].

Pancheri et al[15] simulates the breakdown voltage of abrupt and linearly graded junctions with different doping concentration and grading coefficient, in cases of only electron and only hole injection. They obtains good agreement with their experimental data. The parameter used for their simulation and results are summarized in figure 1.5 and table 1.1.

1.2 Impact ionization

Let now focus on the basic phenomenon, which is used for avalanche photodiodes: impact photoionization and charged particle ionization.

First of all let analyze the many-body problem, using Hartree-Fock approximation, and then the application to the diode.

With this brief discussion we want to have the first indication to calculate some of most

important figure of merits, that will be discussend into the next chapters.

1.2.1 Many-body problem for photoionization.

This method for the molecules photoionization is theoretical interesting for the application of Hartree-Fock approximation and frozen core one ¹ , used for many-body fermionic system. This well-know approximation is derived by the mean-field approximation for many-body systems.

Like many body problems, the procedure used to solve it is to find the mean-field potential and the residual interaction potential.

When the interaction equation is find, the solution is find in iterative way, and all the parameters are tabulated by Lucchese et al. [12] [13].

Let start to consider a system composed with general molecules in steady-state, molecules’

electrons and an incident photon. The Schrodinger equation is characterized by the exchange- static potential. The electron momentum term and the orbital kinetic term. Of course, the wave function is related to the polarization of input photon and its momentum ~k:



− 1

2 ∇ ² − 1

r + V (~r) − k ² 2

 ψ _~ ^(±)

k (~r) = 0, (1.11)

where V is the exchange potential. In the frozen core Hartree-Fock the hyptothesis is that the final state of the electron is described by a single electronic configuration, so an orbital. For this reason the solution is imposed in this form:

ψ _~ ^(±)

k (~r) = r 2 π

X

l,m

i ^l e ^±iσ

F _l (γ; kr)

kr Y _lm (Ω _{r ˆ} )Y _lm ^∗ (Ω _{ˆ k} ). (1.12) F _l is determined by an equation of the many-body Columbian problem:



− ∇ 2 + Z

r



ψ _{~ k} (~r) = k ²

r ψ _{~ k} (~r), (1.13)

and the solution is well-know: in fact, denoted ρ = k~r and η = ^Z _k , the solution is dependent to the function ω:

ψ _k (~r) = 1 (2π) ^2/3

1 r

∞

X

l=0

4π(−i) ^l ω(η, ρ)Y _l ^m (~r)Y _l ^∗m (ˆ k); (1.14) and, placing 1.14 in 1.13, we obtain the equation:

d ² ω l

dρ ² +

 1 − 2η

ρ − l(l + 1) ρ ²



= 0. (1.15)

The final result of this equation is the Columbian function

F _l (η; ρ) = 2 ^l e ^−πη/2 |Γ(l + 1 + iη)|

(2l + 1)! ρ ^l+1 e ^−iρ M(l + 1 + iη, 2l + 2, ±2iρ), (1.16) where M is the ipergeometrical confluent function ² .

Let return on the original problem and rewrite the equation 1.11 in Lippman-Schwinger for:

ψ _k ^(±) = ψ ^c(±) _k + G ^c(±) ψ ^(±) _k , (1.17)

1

The Hartree-Fock frozen core approximation use a particular exchange potential for electrons: where Z is the atomic number, r

the distance from the origin r

the mutual electron distances and ψ

the j-electron wave function.

2

The ipergeometrical confluent function is the solution of the equation like:

z d

ω(z)

dz

− (b − z) dω(z)

dz − aω(z) = 0.

1.2. IMPACT IONIZATION 7 where G ^c(±) is the Coulomb Green’s function. Eigenvalues and eigenfunctions are determined considering the previous equation. Of course the solutions founded, for Hartree-Fock approxi- mation is a parametrization of Slater determinant:

ψ _k = 1

√ 2 |φ ₁ αφ ₁ β...φ _n αφ _k β| − |φ ₁ αφ ₁ β...φ _k αφ _n β|; (1.18) δψ _k = 1

√ 2 |φ ₁ αφ ₁ β...φ _n αδφ _k β| − |φ ₁ αφ ₁ β...δφ _k αφ _n β|, (1.19) minimized using the variational method [13]. At the end, let define the dipolar Matrix in both positional and momentum representation:

I _{~ k,ˆ} ^L _n = q

|~k| D ψ k

   ~ r · n ˆ

   ψ ⁽⁻⁾

E

; (1.20)

I _{~ k,ˆ} ^V _n = q

|~k|

E D

ψ _k    ∇ · ˆ ~ n

   ψ ⁽⁻⁾

E

. (1.21)

that results can be expanded using atomic armonic functions:

I _~ ^L,V

k,ˆ n = r 4π 3

X

l,m,n

I _l,m,n ^L,V Y _l ^∗ m(Ω _{k ˆ} )Y _ln ^∗ (Ω _{ˆ n} ) (1.22)

Lucchese et al shows that the cross section is related to the dipolar matrix and angular distri- bution of lattice’s scattering centers;

dσ ^L,V

dΩ _{ˆ k} = σ ^L,V 4π

h

1 + β ^L,V _ˆ

k P 2 (cosθ) i

(1.23)

where β _{ˆ k} ^L,V represent the asymmetry parameter of distribution of scattering centers, dependent by 

  I _~ ^L,V

k,ˆ n

2 [13], and P 2 (cosθ) the second order Legendre polynomial of the cosine of the angle between ˆk and ˆn. In the same way we can obtain the differential cross section related to a diffused source:

dσ ^L,V

dΩ _{k ˆ} = σ ^L,V 4π

h

1 + β _n ^L,V _ˆ P 2 (cosθ) i

. (1.24)

In particular of silicon [13] there is the transition:

([N e]3s ² 3p ² )SL + hν → ([N e]3s ² 3p ¹ )S ⁰ L ⁰ + e ⁻ (~k), using the previous iterative variational method we obtain[13]:

σ _ν = σ[αx + (β − 2α)x ^s+1 + (1 + α + β)x ^s+2 ] ∗ 10 ⁻¹⁸ cm ² , (1.25) where x = _2πν ^λ S ⁰ L ⁰ , λ is the photon wavelenght and ν the frequency correlated to ionization threshold. Coefficient α ,β and s are tabulated in [3].

In the exposition of the derivation of the photo-ionization cross-section, there is no hypothesis about the crystalline lattice or the impurity, ect...

For this reason in the next paragraph is analyzed the determination of the ionization rate

parameter, used to derivate some features of diodes.

1.2.2 Ionization rates for p-n junction.

Let analyze the problem of the ionization rate of p-n junction.

Firstly we have to give a profile for impurities. Overstraeten et al [22] considers that the profile of impurities is approximate by exponential distribution:

N (x) = N _s [exp(−x/λ) − 1] := N _s [exp(−z) − 1] (1.26) and the ionization ratio γ = ^α _α

depend on electric field ~ E from electron and hole initiated multiplication factor of the diode. As well as, the last hypothesis consists on that the ionization rates α p and α n are assumes constants. The profile of the probability of ionization is dependent on the electric field, respecting the Chynoweth’s law:

α( ~ E) = α ∞ e ⁻

b

| ~E|

(1.27)

where α ∞ and b are determined using a properly diode model. Let us consider a reverse biased junction, shown in the figure 1.6. The origin of the x-axis is taken at the junction. The boundaries

Figure 1.6: Diode model and symbols used for the calculatation of the multiplication factors.

of the depletion layer are respectively x n and x p . The total voltage across the junction is:

V = V a + V d , (1.28)

where V a is the external applied voltage and V d the build-in ptential. The sign convention for V _a used is that it is positive for reverse bias. The minority carrier currents are referred to as J pn , the hole at x n and J np , the electron current at x p respectively. For qV = q(V a + V d ) much larger than the threshold energy for ionization  i , the electrons and holes ionize, resulting in an increase of J pn to J pp at x p and of J np to J nn at x n . Since for V a = 0 the total voltage across the junction correspond to an energy, qV d , which is smaller than the threshold energy  i , there is no ionization.

The multiplication factor at reverse voltage V may be defined and is calculated[22], defining k = J np /J pn :

M (V ) = J (V )

J(V d ) = J _nn + J _pn J pn + J np

= J _pp + J _np J pn + J np

=

= e ⁻

R

xn

(α

−α

)dx

+ k (1 + k)1 − R x

x

α n e

R

xn

(α

−α

)dx

dx

= (1.29)

= ke ⁻

R

xn

(α

−α

)dx + 1 (1 + k)1 − R x

x

α _p e

R

xn

(α

−α

)dx

dx

. (1.30)

1.2. IMPACT IONIZATION 9 For the superposition principle, we can note that there is a simplest way to calculate the multi- plication rates is to calculate that in pure electron or hole injection cases. For pure hole injection k = 0 , and as a consequence:

1 − 1

M p (V ) := Φ p (V ) = Z x

x

α p e

R

xn

(α

−α

)dx

dx (1.31)

and, for pure electron injection (k → +∞):

1 − 1

M _n (V ) := Φ _n (V ) = Z x

x

α _n e ⁻

R

xn

(α

−α

)dx

dx, (1.32) where M n (V ) and M p (V ) are the multiplication factors, Φ p and Φ n the reduced ones. To determinate the ionization rate we have to determinate the diode parameter (x n , x p and ~ E(x, V )) and then the multiplication parameters using the ionization integrals 1.31 and 1.32.

To calculate the electric filed and the boundaries of the depletion layer we have to solve the Poisson equation of this system. A double integration of the Poisson equation yields the following set fo two equation in reduced partial widths z p and z n of the depletion layer:

( F (z n ) = F (z p )

e ^−z

(z p − z _n − 1) + e ^−z

− ^(z

^−z ₂

⁾

= v , (1.33) where ³ :

F (z) = e ^−z + z − 1; (1.34)

v = V _a + V _d

λE ₀ ; (1.35)

E ₀ = qλN _s

 . (1.36)

Knowing N s and λ, the parameters of the diode are obtained by numerical solving of 1.33. The electric field is given by:

E(z) = E ₀ [F (z _n ) − F (z)] (1.37)

and the maximum value of this field is:

E _m = E ₀ F(z _n ). (1.38)

Going back to the original coordinate x = zλ, we obtain the required boundaries of the depletion layer and electric field. The experimental method to derive impurities parameters and V _d is the measurement of the capacitance, discussed later [22].

The determination of ionization ratio γ is determined by equations 1.31 and 1.32. The threshold of ionization impose that the distance x p − x _i covered by the electron current J np injected into x _p before ionization, referred to figure 1.7, is given by:

ψ(x _i ) − ψ(x _p ) = Z x

x

E(x)dx =  _i

q , (1.39)

with ψ is the crystal potential. The holes injected from left to right at x i generate e-hole pairs by secondary ionization and increase the electron current at x i . At the and for some manipulation:

γ = M p (V ) − 1

M _n (V ) − 1 (1.40)

Finally, all parameters of silicon ionization rate are measured and tabulated[22]. This results are used during this work and are showed in figure 1.8. Now we have to focus on how to control the avalanche and the specific use of a SPAD.

3

q is the electronic charge q = 1.6 ∗ 10

C and  is the electric permeability of silicon: 1.04 ∗ 10

F ∗ cm [22]

Figure 1.7: Model of the calculation of the influence of the threshold energy 

on the charge multiplication.

Figure 1.8: Results obtained by Overstraeten et al. for ionization rates α

and α

[22].

1.3 Simple circuit implementation: Recharge and quenching

There are some features and parameters to control in SPAD managing, during measurement.

First of all we have to control current, because the heat dissipation of the component can damage the diode. Also we have to control the correlated noise, so the applied voltage would be restored rapidly. For this reason there is the necessity of quenching and recharging circuits.

1.3.1 Recharge circuits

For the components chosen, to insert in the box in figure 1.10, which can be used for the recharge, there are two types of recharge circuits: active and passive.

As a passive recharging circuit, we can use a simple resistor. The resistor must be large to

1.3. SIMPLE CIRCUIT IMPLEMENTATION: RECHARGE AND QUENCHING 11

Figure 1.9: General recharge circuit, where the recharge element is represented by the Rec. box. In the figure there is also the comparators output.

challenging the space-charge effect resistance. There are disadvantages with passive circuits, because the restoring time is not brief, consequently the dead time of this detector will become too long. For high events rates an avalanche can occur before the diode is completely recharged [8]. In figure 1.10 we note that the timing distortion becomes if the avalanche does not recharged properly and the bias voltage is not correctly restored .

Figure 1.10: A passive recharge circuit normally outputs rising edges, detected by the output if they cross the threshold during the rising (left). If the rate of the events becomes high, the bias voltage cannot be restored, giving a frozen high level (right).

There is also mentioned in literature the possibility of active recharge circuits [8]. The idea is to place a transistor in series with the SPAD use it like an high-impedance switch. The timing responce can be better using a feedback recharge-quenching circuit, creating a monostable element into the detector front-end.

An active recharge gives more saturation behavior when the rising edges in the output pulses are being counted, since the number of pulse will saturate with active recharge, but with passive recharge the number of rising edges will decrease at same point, as figure 1.10 shows.

1.3.2 Quenching circuits.

In addiction to recharge, this architectures also aid in quenching avalanche before completion by sensing avalanche onset and aiding in quenching too.

Circuits that quenches avalanche and the resets the bias voltage plays a key role in SPADs

detector performance. Like recharge elements, there are two type of quenching circuits: active

and passive.

Passive-quenching circuit (PQC). PCQ is a simple circuit used for the quench. Seeing the model in figure 1.11, the SPAD is reverse biased through a high ballast resistor R L of 100 kV or more, C d is the junction capacitance (typically ,1 pF), and C s is the stray capacitance (capacitance to ground of the diode terminal connected to R L , typically a few pF ). The diode resistance R d is given by the series of space–charge resistance of the avalanche junction and of the ohmic resistance of the neutral semiconductor crossed by the current. The R d value depends on the semiconductor device structure: it is lower than 500 V. Avalanche triggering is equivalent

Figure 1.11: Basic PQC’s: (a) configuration with voltage-mode output, (b) configuration with current-mode output, (c) equivalent circuit of the current-mode output configuration. The avalanche signal is sensed by the comparator that produces a standard signal for pulse counting and timing.[4]

to close the switch on the circuit in figure 1.11(c) creating a current spike. If I d (t) and V d (t) are diode’s current and voltage transients:

I d (t) = V d (t) − V bd

R _d := V ex (t)

R _d . (1.41)

When the event is triggered,the avalanche current discharges the capacitances so that V d and I d

exponentially fall toward the asymptotic steady-state values of V f and I f :

I _f = V _A − V _B R d + R L

' V _E R L

, (1.42)

V f = V B + R d I f . (1.43)

The approximation is justified since it must be R L  R _d , as shown in the following. The quenching time constant T q is set by the total capacitance C d + C _s and by R d and R L in parallel, i.e., in practice simply by R d ,

T _q = (C _d + C _s ) R _d R _L R d + R L

' (C _d + C _s )R _d := T _r . (1.44)

1.4. CMOS IMPLEMENTATION FOR SPADS: PIXEL DETECTORS 13 If I f is very small, V f is very near to V B . When the declining voltage V d (t) approaches V B , the intensity of I d (t) becomes low and the number of carriers that traverse the avalanche region is then small. Since the avalanche process is statistical, it can happen that none of the carriers that cross the high field region may impact ionize.

The probability of such a fluctuation to zero multiplied carriers becomes significant when the diode current I d falls below <100 µA, and rapidly increases as I d further decreases[4]. The pres- ence of the parasitic capacitances gives a dead time to recovery system, which is in microsecond range typically. As the recovery starts, the diode voltage V d rises over V bd . if a photon arrive during the recovery the triggering probability is low, but during the last part of the restoring process, the event triggering becomes possible.

The output pulse has the amplitude:

V u = (V A − V _B − I _q R d ) R s

R _L + R s

' V _E R s

R _L (1.45)

A drawback of the voltage-mode output is that the detector timing performance is not fully exploited, because of the intrinsic low-pass filter with time constant T q that acts on the fast current pulse to produce the voltage waveform.

The energy E pd dissipated in the SPAD during an avalanche pulse corresponds to the decrease of the energy stored in the capacitance C d + C s :

E pd = 1

2 (C s + C d )(V B + V E ) ² − 1

2 (C d + C s )V _B ² ' (C d + C s )V E V B . (1.46) The dissipation therefore depends not only on excess bias voltage V E and total capacitance C _d + C _s , but also on breakdown voltage V B . At moderate total counting rate n t , the mean power dissipation is given by n t E _pd and may cause significant heating, particularly in SPAD’s with high V B .

It is worth stressing, however, that PQC’s are fairly safe for SPAD’s, since they inherently avoid excessive power dissipation. At higher n t values, the dissipation rise is limited by the increased percentage of small-pulse events; at very high n t , the limit dissipation corresponds to the product of latching current I q and breakdown voltage V B .

Active Quenching circuits(AQC) To avoid drawbacks and damages to SPAD’s, active quenching approach is a good solution. The basic idea was simply to sense the rise of the avalanche pulse and react back on the SPAD, forcing, with a controlled bias-voltage source, the quenching and reset transitions in short times. The basic principle is that the rise of the avalanche pulse is sensed by a fast comparator whose output switches the bias voltage source to breakdown voltage V bd or below. After an accurately controlled hold-off time, the bias voltage is switched back to operating level. A standard pulse synchronous to the avalanche rise is derived from the comparator (figure 1.12) output to be employed for photon counting[4]. For a complete exposition we have to say that there is the possibility to create a mixed active-passive quenched circuit, like the example in figure 1.13.

The most important feature of this kind of circuit is the possibility of miniaturization, using CMOS lithography.

In the next part is shown how to create a SPAD CMOS implementation, and a brief analysis of problems and solutions during the construction process.

1.4 CMOS implementation for SPADs: pixel detectors

The implementation in CMOS technology permits to create miniaturized system of SPAD.

This technology also permit to create embedded front-end circuitry (recharge and quenching

circuits). For this reason, we have the possibility to create a matrix of this fundamental unit,

composed by the diode and the front-end circuit, such as a pixel.

Figure 1.12: Simplified diagram of the basic active quenching circuit configuration with opposite quenching and sensing terminals of the SPAD. The network in the dotted box compensates the current pulses injected by the quenching pulse through the SPAD capacitance, thus avoiding circuit oscillation.

The voltage waveforms drawn correspond to the circuit nodes marked with the same letter.[4]

Figure 1.13: Example of mixed active-passive quenching circuit [4].

1.4. CMOS IMPLEMENTATION FOR SPADS: PIXEL DETECTORS 15 On the other side, there are two features to manage during the measuring activities and developing. First of all we have to consider the containment of the avalanche into the active area, and then the reduction of the cross-talk between neighbor pixels.

Referred to figure 1.14, when the first avalanche filament is created. The strong carriers con- centration gradient drives a lateral diffusion. Few carriers diffuse and in turn starts avalanche multiplication in the sheath surrounding the filament, becouse of the high gradient region out- wards. Lateral diffusion then occurs at the new outer edge of the current, and this phenomenon propagates[5]. In the end there is the necessity to separate the active region by the surrounding areas. The structures responsible for this separation is called guard ring. After the implantation

Figure 1.14: Sketch of phenomena that support lateral propagation of the avalanche current started by a photon:

(a) lateral diffusion of carriers assisted by avalanche multiplication; (b) absorption within the detector area of photons emitted by hot carriers in the avalanche current.[5]

of doped semiconductor; if the guard ring is not present, the high curvature of the edge will cause the premature breakdown, which reduce the active region. Some SPADs do use virtual guard ring, with a look of an extra implant creating doping differences between the structure’s outer edge and active region; or real guard rings. The guard ring’s implementation introduce new constraints in the SPAD design.

The planar SPAD is the only architecture compatible with the standard CMOS processes.

Planar SPADs have a depletion layer that is hundreds of nanometer to several micrometer thick [5]. Because most modern CMOS processes use p substrate, a straight-forward SPAD uses the n+ diffusion implant to generate an n+-p junction, with a shallow n-well forming the guard ring.

Using a deep n-well isolates SPAD from substrate noise, since the substrate and the deep well form an additional junction that will prevent free carriers in the substrate, which often have a long mean free path, from diffusing into the junction itself. Due to the doping concentration and implant depth in CMOS processes, the depletion layer of implemented SPAD have narrowed and thus a major contribution to noise due to the tunneling. As well as the side effect of high doping levels impose the use of shallow trench isolation (STI)[17] (figure 1.15). STI has had an increasingly important role in the guard ring. The STI include a noise component, due to the trap-filled surface near the depletion region[8]. To reduce this effect, a retrograde junction is used. This junction create a uniform electric field, requiring less physical distance to achieve breakdown.

Dopant in a CMOS process do not have sharp boundaries as often portrayed, and they are

not implanted exactly where expected due to the diffusion. The diffusion can cause sizable

distortions to a SPAD’s multiplication region. In a small diode even distort the expect the value

of the diode’s breakdown voltage [8].

Figure 1.15: (Up)Cross-sections of SPADs with well-based guard rings: the multiplication region is high- lighted with a dashed eclipse.

(Down)Cross-section of SPADs with STI-based guard rings: The multiplication region is highlighted with a dashed eclipse. often, a retrograde n-well or retrograde implant is used to create the junction.

Figure 1.16: The diffusion of well-based guard rings’ implant (dotted) can cause sizable distorsion to the multi- plication region(dashed).

A feature of CMOS process generation beyond 250-nm is the presence of an optional deep N implant formed by an HV implantation step before n-well formation. This implant is contacted by a ring of n-well and is normally used to completely enclose the p-well regions in order to isolate NMOS transistors from the reminder of the substrate.

Another non-ideal effect consists to the inactive distance in the depletion layer, due to the diffusion of trapped carrier into the STI, reducing the active area, shown in figure 1.16. Due to doped silicon’s resistivity, ohmic resistances are introduced between the diode itself and contacts to external circuitry. The ohmic resistance is an important factor when attempting to quickly switch the applied voltage on the diode.

Most of this features are must include to the analysis of the measures during this work,

because they create distortions and noise generation.

Chapter 2

The APiX sensor

In actual research at high luminosity LHC, hybrid pixels has been successfully employed in their experiments since their beginning. This type of detector are used because their cheap material budget, low power consumption and radiation hardness[11], because the request of most precise vertex measurement and momentum resolution.

The first solution is to create a thin and full depleted silicon sensors, to reduce multiple scattering. But, in the other hand,this solution directly impacts to signal-to-noise ratio. For this reason is chosen to develop monolithic active pixel sensors, with CMOS technology.

Due to of CMOS foundry capability, there is the possibility to create gain avalanche detectors, that including integrate front-end electronic, with no need of pre-amplification.

The real problem of this kind of devices is represented by dark count rate (DCR). To solve this problem we can use two-tier avalanche pixel detector, consisting of two planar sensors layers.

The output signal coincidence is produced when simultaneous strikes both the detectors.

Thanks to cell-to-cell coincidence, the dark count rate DCR C of a two layer pixel will be reduced to:

DCR _C = DCR ₁ · DCR ₂ · 2∆t (2.1)

where DCR 1 and DCR 2 are the dark count rates of the two cells, rescectively,and ∆t is the co- incidence time resolution, so the duration of the signal provided by front-end electronics [14][11].

Figure 2.1: Single cell of a dual-layer avalanche pixel detector.

APiX is a dual-layer array of avalanche pixels, which has been developed is 180 nm CMOS process with high voltage option. This technique is usually used for automotive market(figure 2.1).

The chip is comprised of a number of different structures, including single avalanche diodes with

17

different size and based on different combination of technologies layers, for different type of mea- sures. Moreover, three different of the readout channel have been integrated, one implementing an active quenching technique. In the array, the different options for the sensors and front-end channel are put together so as to cover all possible combinations[14].

Now we analyze the architecture of APiX chip in the first section. In the second one we focus on the procedures, that are used for the enabling and the data acquisition.

2.1 The Architecture

Let we analyze the architecture of the fundamental unit of both chips. APiX is characterized by two different types of Geiger-mode avalanche detectors, represented in figure 2.2. Type 1

Figure 2.2: Cross section of two detector types.

detector has a shallow p+/nwell junction, while type 2 is based on a deeper pwell/deep nwell junction. The active module is less than 2 µm thick, and both detectors are isolated from the substrate thanks to a deep-nwell.

A simplified pixel block diagram is shown in figure 2.3. The detector is passively quenched

Figure 2.3: Block diagram, with some transistor level detail, of the front-end circuit with passive quenching.

and their output signal are digitalized using a low-threshold comparator.Transistor used in the readout channel are all core devices (V DD = 1.8V ), except for the current source performing the passive quenching operation and the transistor used to adapt the signal level from the sensor to the comparator, which are I/O devices(V DD = 3V ).

The output pulse can be shortened using a monostable circuit in four different width, from 750 ps to 8 ns, as we can see in figure 2.4. The circuit can be tested using an external T EST signal.

The pixel can be independently enable and disabled using a register, with arbitrary pattern.

2.1. THE ARCHITECTURE 19

Figure 2.4: APiX C1 monostable outputs visualized using a 1GHz probe. The temporal scale is 2ns/div.

The monostable output signals are also sent to a row-wise OR gate, combining the outputs of all activated pixels. This feature is improved to measure the DCR, that will be analyzed in the next chapter.

Figure 2.5: Schematic diagram of two layer pixels.[11]

APiX C1 Architecture Referring the red box in figure 2.5, the chip 1 (APiXC1) is composed by a 16×48 pixels array. Each pixel is made by: the avalanche detector and the passive quenching circuit, the 1-bit register for the enabling, the front-end electronics and the output register and the coincidence unit, to connect on the corespondent pixel of the second chip. In addiction to the OR output mentioned before, a row-wise coincidence detection circuit has also been included.

The output of two given rows can be connected to the row coincidence detector, as shown in figure 2.6, allowing for the study of the coincidence among arbitrary configuration of pixels between two rows. This feature is used to measure the cross-talk.

APiX C2 Architecture Referring the blue box in figure 2.5, the APiX chip2 (APiXC2) is

composed by always a 16 × 48 array of pixels, that are composed by the detector and quenching

circuit, the front-end circuit and the 1-bit enable register. The output of this register is splitted

Figure 2.6: Schemating diagram illustrating row-wise coincidence detection unit [11].

in two channels, one of this is connected to to the solder bump, and the other one is used by an independent output for a single-layer measurement.

Figure 2.7: Layout of pixels with different size of detectors.[11] On the left there are unshielded pixels and on the right there are the shielded ones.

The core sensor consist of a particular partitioning of the array. Both types of detectors in figure 2.2 were included in the array, in order to choose the best for the application[11]. As we can see in figure 2.7, the array contains detectors with different active areas: 30 × 30µm ² , 35 × 35µm ² , 40 × 40µm ² and 45 × 43µm ² . The main goal of these architecture is to characterize the quantum efficiency of the detector as a function of the filling factor [11].

Finally, the bump bonding technique used a 12µm solder bumps was chosen for the vertical integration, due to the accessibility and good yield of the process. Most of the pixels were covered with a metal shield to avoid inter-layer optical cross-talk (figure 2.7). A few pixels were left unshielded to study vertical crosstalk and allow for optical measurement.

A summary of arrays partitioning and pixel coupling is shown in figure 2.8.

Let now see the features, functionalists and algorithms necessary to enabling the pattern and

to read the data signals.

2.2. ENABLING PIXELS 21

Figure 2.8: Array partition for both chip of APiX detector. The enabling process access single cell from right to left.

2.2 Enabling pixels

The pattern of enabled pixel is independent for the to layers. For this reason, we must have to write twice the procedure. This processes are similar than the write procedure of asynchronous DRAMs.

The signals that are used to apply the pattern on the array is characterized by six digital signals:

• T EST _N(C2): Mentioned below, this signal is used to test the monostable output. This signal is set LOW during all the enabling process. This imposition permits to isolate the SPAD during the programming;

• V SR_RST (C2): this signal reset the content of the vertical shift register, which is use to select rows;

• V SR_CLK(C2): this signal is use to shift all the rows one by one;

• EN_RST (C2): reset the content of horizontal shift register, so the column selector regis- ter;

• EN_CLK(C2): signal use to shift colums one by one using the horizontal register;

• EN_IN(C2): bit which is used to activate a single pixel.

Like an asynchronous DRAM, we have to use an electronic system to control the process and to give a clock signal reference. For our experiment we used Arduino DUE (SAM3X8E-ARM) microcontroller, with 10 MHz main clock signal. All procedures are implemented in an Arduino firmware.

Referring the time diagram in figure 2.9, the procedure is used to enabling pixel is:

• Reset the vertical register and put it on the idle state;

Figure 2.9: Enabling process time diagram.

• Introduce, with a loop, the procedure to shift the VSR. In every iteration a V SR_CLK spike signal is sent to the register. In this way a column was selected and, consequently, the horizontal register is reset to its idle state.

• A second iterative loop was inserted to resolve the horizontal shift register. In this loop a EN _CLK signal is sent to horizontal register. The second operation in the loop consist to set the pattern with an "if" condition. To switch on a pixel is must be necessary to send a EN_IN spike signal from the controller.

• To visualize event in a row, the vertical shift register must be positioned in at the active row position, and send a T EST _N signal.

2.3 Data acquisition

In this last section is introduced the DAQ process. First of all we have to say that there are two read approach: bypassing the FIFO (for both chips) and using the internal memory (only for APiXC1).

In the first case the implementation is simple: the solution is to implement an internal window and count rising edge signal from the chip, and then use an interrupt signal to count OUT _OR rising edges.

A simplified time diagram of this process is shown in figure 2.10, where OUT _OR is the output signal of the detector, count the numeric data and ST ART _T is the internal signal ¹ . A possible result of the APiXC2 scan is shown by the heat-maps in figure 2.11. To manage APiXC1 data acquisition and double-layer’s one, the internal memory of the device is used.

The device has eight 96-bit FIFO, one FIFO for two adjacent rows. for this reason the internal signal used are:

• F IF O_RN: external FIFO initial reset;

• MEM_RN: internal memory initial reset;

• F IF O_SEL: external FIFO selector for a 8-bit shift register;

1

SAM3X8E-ARM microcontroller has four internal PLLs (phase-locked loop), which is used to generate a

reference signal with arbitrary frequency.

2.3. DATA ACQUISITION 23

Figure 2.10: Time diagram of C1(bypassing internal memory) and C2 layer data acquisition.

Figure 2.11: APiXC2 heat-maps obtained using the first algorithm. The software used is made ad-hoc using ROOT compiler.

• F IF O_T X: transmission enabling bit;

• F IF O_OUT < i >: This is the output of the i-th FIFO content (from 0 to 7).

In figure 2.12 there is an example of timing diagram of the internal FIFO reading process. In the first part (in the right of the double vertical line) there is the setup reset of both memories, used to erase the undefined data. The communication and the data transfer from F IF O_OUT < i >

is open using a spike of F IF O_T X signal. This signal is also used to shift the internal FIFO contents (on the left of the dashed line).

This two approaches can be used for different kind of solution, coupled with enable processes.

For example we can turn on all the matrix and transfer data from the FIFO or an external memory dump. In the same way we can turn on pixels one by one and read the data using an external process.

Complete firmware algorithms are available on Appendix A.

This solutions are all implemented and discussed in the next chapter, where we will talk of

electrical noise features.

Figure 2.12: Time diagram of the APiXC1 internal FIFO.

Chapter 3

Noise Characterization

Like all electronic instruments, also SPAD are affected by the noise. The noise has two different sources: electrical and optical. Both of this types consists by undesirable injection of carriers.

The dominant components of the noise are after-pulse and cross-talk. Both of they depends on the generation rate of carriers given by specific electric field, as these carriers will cause the spurious avalanches.

In this chapter we focus on the dark count rate and the optical noise, with the determination of some parameters like breakdown voltage,horizontal and vertical cross-talk.

3.1 Dark Count Rate (DCR)

Dark count Rate (DCR) is the rate of events detected in no exposition conditions. The DCR represent the rate of carrier injected into the depletion layer, which are generated in other parts of the device.

For example, the limitation imposed by implants depth, doping concentrations and design rule description in CMOS processes have led to narrow depletion width devices being reported with high DCR due to the tunneling and low photon detection efficiency [17].

Due to the doping concentration and implant depths for the sub 250-nm processes which are required to implement dense digital circuitry, the depletion layer of the SPADs have narrowed and thus a major contributor to dark count has become tunneling. As well as the side effects of high doping levels the use of STI in such processes is know to increase stress and charge traps, thus increasing the DCR and after-pulse[17].

The setups used for DCR characterization are two:

• The first consist on a own-made chip-carrier for APiXC2. Voltage level are regulated by four trimmers. V bd is generated by a DC-DC converter or, optionally, by an external generator. This carrier is connected to an ARDUINO DUE board, which is programmed to enable the array pattern and store data. The external voltage source is gave by ARDUINO board 5V reference, represented in figure 3.1;

• The PCB carrier for APiXC1 and the complete devices is connect to ARDUINO DUE board and level regulation transistor. the voltage references consists by two external generator, which is programmed by a numerical control, written in OCTAVE (or MATlab).

The chip, the carrier and the ARDUINO board are placed into a climatic chamber, with a range between −50 ^o C and +50 ^o C . The scheme is in figure 3.2.

25

Figure 3.1: (Left) Scheme of the APiXC2 carrier board, with the indication of levels. (Right) photo of the carrier used for the measurements.

Figure 3.2: (Left) Scheme of the APiXC1 and double layer system, with the indication of levels. (Right) photo of the carrier used for the measurements.

3.1.1 Count-V characteristic and analysis

The first measure we want to discuss is the I-V characteristic of SPAD includes into the array. Due to the design of the pixel, this operation is not possible, but we can do an alternative measure.

This alternative operation consist to acquire dark counts in function of the input voltage level V SP AD .

Using the chip carrier in figure 3.1, we had set manually the voltage reference, and then we had registered some frames at 10 fps for ten seconds. We have choose for both types of SPADs eight cells, four shielded and four unshielded, with different active areas. The voltage applied voltage reference are:

V REF = (0.732 ± 0.001)V (3.1)

V _BIAS = (1.507 ± 0.001)V (3.2)

V _{CLAM P} = (2.497 ± 0.001)V (3.3)

V _BN = (1.500 ± 0.001)V ; (3.4)

In all cases we found the same evolution of the DCR, which underline the three regimes:

linear, sub-Geiger and Geiger mode, as we can see in figure 3.3. In figure 3.4 we can see that the behavior of the SPAD is the same. Of course some parameters change due to the material.

In fact the first parameter is the minimum potential required to permits the avalanche into the SPAD: the breakdown voltage.

To measure the breakdown voltage in V bd for APiXC2 cell a linear regression is applied on the linear region of all cells, then the breakdown voltages are extrapolated by the fit, imposing that DCR = 0. Results are reported in tables 3.1 and 3.2.

The same characterization is made for APiXC1 device, but with different procedure, because

the different available setup.

3.1. DARK COUNT RATE (DCR) 27

Figure 3.3: Example of two homologue cells of two different chips. We can recognize the linear regime between 22.5 and 25 volts, the sub-Geiger regime at 25.5 volts, and then we found the Geiger regime.

Figure 3.4: DCR-V plot of diverse APiXC2 cells of both types and shielding. There are the results made by using two different chips, named with the color of their support.

With an external controller the V spad voltage is managed by a computer software, using MATlab.

Then automatically the frame are register by the help of an external counter.

The result is a little bit different than that obtained with the APiXC2, probably because the better quality of the APiXC1 carrier manufacture. As well as, seeing results in figure 3.5 the linear interpolation of linear regime’s point in not possible. To fit the breakdown parameters the error function is used:

y = a

Z _V

0

e ⁻

2

b

dt, (3.5)

where a, b and V bd are fit parameters. The obtained results are tabulated in table 3.3. The enumeration of APiXC1 cells is different than APiXC2 because the different algorithm used.

We can note that the breakdown voltage, so the working points, are not different for two

Cell coordinate side length (µm) type V _bd (V) SPAD 1

(0,47) 30 unshielded (19.22 ± 1.71)

(0,46) 35 unshielded (19.44 ± 0.78)

(0,45) 40 unshielded (20.27 ± 0.64)

(0,44) 45 unshielded (19.72 ± 2.31)

(0,41) 30 shielded (19.11 ± 1.67)

(0,38) 35 shielded (19.28 ± 1.42)

(0,35) 40 shielded (19.22 ± 2.33)

(0,24) 45 shielded (19.71 ± 1.50)

SPAD 2

(8,47) 30 unshielded (21.92 ± 0.87)

(8,46) 35 unshielded (21.82 ± 0.85)

(8,45) 40 unshielded (22.46 ± 0.42)

(8,44) 45 unshielded (22.34 ± 0.89)

(8,41) 30 shielded (22.50 ± 0.67)

(8,38) 35 shielded (21.99 ± 2.29)

(8,35) 40 shielded (22.23 ± 1.32)

(8,24) 45 shielded (22.01 ± 2.46)

Table 3.1: Black chip’s V

for different cells.

Cell coordinate side length (µm) type V bd (V) SPAD 1

(0,0) 30 unshielded (18.39 ± 0.40)

(0,1) 35 unshielded (19.08 ± 1.00)

(0,2) 40 unshielded (18.56 ± 0.86)

(0,3) 45 unshielded (18.48 ± 0.43)

(0,6) 30 shielded (18.48 ± 0.43)

(0,9) 35 shielded (18.40 ± 2.18)

(0,12) 40 shielded (18.27 ± 0.92)

(0,24) 45 shielded (18.44 ± 1.28)

SPAD 2

(8,0) 30 unshielded (22.19 ± 2.19)

(8,1) 35 unshielded (22.28 ± 0.87)

(8,2) 40 unshielded (22.17 ± 0.55)

(8,3) 45 unshielded (22.28 ± 1.65)

(8,6) 30 shielded (22.16 ± 2.07)

(8,9) 35 shielded (22.37 ± 1.18)

(8,12) 40 shielded (22.20 ± 1.18)

(8,24) 45 shielded (21.91 ± 0.35)

Table 3.2: Brown chip’s V

for different cells.

chips, the only difference is correlated by the SPAD type. The difference between the results of

two arrays consist by the absolute error, that derives by the measuring method. The APiXC2

carrier permit to control the V SP AD voltage using a voltmeter, with a precision of 0.01 volts,

but the internal controls used for the APiXC1 carrier gave a better precisions of voltage (0.001

volts). Also the contact between APiXC2 and its carrier sometimes becomes only capacitive, and

not resistive. In some cases counts fell down or becomes too higher, because the RTS (random

telegraph signal) that hibernate the output status at high level.

3.1. DARK COUNT RATE (DCR) 29

Figure 3.5: Breakdown curves of some pixel of APiXC1’s SPAD2.

Cell coordinate side length (µm) type V bd (V) SPAD 1

(0,23) 30 shielded (18.274 ± 0.002)

(0,24) 35 shielded (18.295 ± 0.008)

(0,27) 40 shielded (18.267 ± 0.001)

(0,30) 45 shielded (18.276 ± 0.004)

SPAD 2

(8,23) 30 shielded (22.497 ± 0.005)

(8,24) 35 shielded (22.483 ± 0.004)

(8,27) 40 shielded (22.490 ± 0.004)

(8,30) 45 shielded (22.489 ± 0.002)

Table 3.3: APiXC1’s V

for different cells.

The next question is that: there are some parameters that correlated by breakdown voltage?

To answer to this question we tried to correlate the breakdown point to active area and environ- ment temperature.

The first analysis is made for the APiXC2. Seeing the figure 3.6 we can note that the breakdown voltage not depends to the pixel area, because the constant profile of V bd .

The relation between temperature and breakdown voltage is made using a bonded chip into the climatic chamber. Both chips are turned on individually. In this way the noise from the other chip is excluded.

The mean value of V bd of the different SPADs is calculated (we can do this operation because the V bd is independent from the area) for different temperatures steps, between -50 and +30 ^o C . The results obtained are represented in figure 3.7.

We note intuitively that there is a linear relation between temperature and noise events, and the behaviour is also independent to the active area. The fit results are tabulated in table 3.4. Also the behavior is the same for both chips and are compatible with the error. The main argument is that the temperature control has a key role into a detecting measurement, to control the noise events.

We can note that our results according to simulations showned in the first chapter(table 1.1),

but, for both SPADs, the dead-space model gives an underestimated breakdown probability.

Figure 3.6: V

vs temperature for cells of APiXC2, using the board in figure 3.1

Figure 3.7: V

vs temperature graphs are shown. in the two graph on the upper part we note the independence from active area.

Chip Subunity V _bd,0 (V) V temp (V/K) APiXC1 1 18.058 ± 0.002 0.0156 ± 0.0001 APiXC1 2 21.631 ± 0.001 0.02121 ± 0.00004 APiXC2 1 17.494 ± 0.028 0.014 ± 0.001 APiXC2 2 21.617 ± 0.002 0.0183 ± 0.0001

Table 3.4: Fit parameter of the V

dependence form temperature.

3.2 Optical Noise

One of the main issues of SPAD arrays is optical noise. In our measures there is the evidence

of the cross-talk, thanks to the two mode of enable-reading processes, that are described in

3.2. OPTICAL NOISE 31 previous chapter.

Figure 3.8: Scan of the same APiXC1 chip: in ((1)) is used the all-on algorithm and in ((2)) the single-on one.

In the third scan, named |((1)) − ((2))| the absolute difference of two previous scan maps. The fourth graph represent the frequency occurrences of the single-on scan (red) and all-on scan (black).

In the figure 3.8 is shown the application of two different enabling-reading operation to the same chip in stable conditions ¹ : for the first one ((1)) all the matrix is turned on, then the content of the internal FIFO was read (call all-on algorithm); in ((2)) pixels are turned on one- by-one and an external counter saves counts of this pixel (call single-on algorithm). Both of that algorithms are reported in Appendix A. We note that there is a significant different between mean dark count rate between two operation. In fact there is a difference of the 30% ² .

The possible hypothesis is that there is a low percentage of new randomize noise in the difference, but the highest part of the difference is generate by the communication between pixels of the same array, called cross-talk.

Some simulations are done by Rech et al. imposing that the cross-talk event detection is due to reflection of photons on the lower silicon-air surface[16]. The emitters are represented by cylindrical emitting volume, that propagates his wave front, and then the light is partially absorbed. The cross-talk simulation for APiX are not treated in this work.

The main parameter that characterize the cross-talk is the cross-talk coefficient K, related to the coincidence counts. Coincidence counts are related by a composed probability of detection of both pixels. If C 1 and C 2 are dark count rate of two pixels and C 1,2 the coincidence rate:

C _1,2 = 2C ₁ C ₂ ∆t + K(C ₁ + C ₂ ); (3.6) where ∆t is the coincidence time window, practically the signal width. So, we can measure the cross- talk coefficient as:

K = C 1,2 − 2C 1 C 2 ∆t

C ₁ + C ₂ . (3.7)

In this section there is the exposition of the evaluation of the horizontal cross-talk coefficient, and a brief analysis of vertical cross-talk between two layers.

1

Conditions: temperature of 28

C and V

= 20.37V . The cross-talk measurements are done only for the first subunity of the array, where SPADs are characterized by p+/nwell junction.

2

In the data analysis and representation the cells affected by RTS signal are eliminated using the criteria that

are eliminated data higher of the (mean + 3σ) calculated after three acquisitions.