Fast Track + few
(Road Finder) CPUs Fast Track + few
(Road Finder) CPUs
ROBROB
offline quality Tracks:
Pt >1 GeV
Ev/sec = 50~100 kHz
Very low impact on DAQ
PIPELINE
LVL1LVL1
Fast network connection Fast network connection
CPU FARM CPU FARM
CALO MUON TRACKER CALO MUON TRACKER
Buffer Memory
ROD
Buffer
Memory ROB
L2 Algorithms
FE FE
Where to add FTK?
resolutionFull hits
resolutionLow super bins
Tracking in 2 steps: find Roads, then find Tracks inside Roads
Road Super Bin
Road = Pattern
Road
AM = BINGO PLAYERS
HIT # 1447
PATTERN N PATTERN 1 PATTERN 2
PATTERN 3
PATTERN 5 PATTERN 4
Dedicated device - maximum parallelism:
• Each pattern with private comparator
• Road search during detector readout
The Event
The Pattern Bank...TRACKING WITH PATTERN MATCHING
AM the Associative Memory
Bingo scorecard
ASSOCIATIVE MEMORY:
CHIP ARCHITECTURE
ONE PATTERN
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
word word word word
Layer 1 Layer 2 Layer 3 Layer 4
HIT
Patt 0
Patt 1 Patt 2 Patt 3
Output Bus
HIT HIT HIT
1/2
A M
1/2 A M
Divide into
sectors
6 buses 6 logical layers
2 sectors ATLAS Pixel + SCT
Feeding FTK @ 50KHz event rate
40MHz/bus
Pixels barrel SCT barrel Pixels disks
6 Logical Layers: full coverage
~70MHz cluster/layer
(Low Luminosity, 50KHz ev.)
ATLAS-TDR-11
20 9U VME boards – 3 types
SUPER BINS DATA
ORGANIZER
ROADS ROADS + HITS
EVENT # N
PIPELINED AM
HITS
FASTRACK
BUFFER MEMORY BUFFER
MEMORY
Front End Tracker
DO-board
EVENT # 1
AM-board
50~100 KHz event rate
GB
Few CPUs
Offline quality Track parameters
The AM board
13th Real Time Conference 2003 Alberto Annovi
The FTK Performances
AM-B7 AM-B8
AM-B1AM-B0DO5DO4DO3DO2DO1DO0
CUSTOM BACKPLANE
Ghost Buster
FTK INPUT
CPU0 CPU1
O(50 10
6) patterns
AM-B2 AM-B3
CPU2 CPU3 AM-B4 AM-B5 AM-B6
• Offline quality tracking
• 50 KHz event (Low luminosity)
• 2 crates (4 to include stereo layers)
• Connection to experiment not included
13th Real Time Conference 2003 Alberto Annovi
• Track confined to a road, fit is simple
• Linear expansion in the hit positions xi:
– = k (cik xi)2 final cut
– d = d0+ai xi = 0+ bi xi Pt = …
• Fit reduces to a few scalar products fast
• Constants from detector geometry
– Calculate in advance
– Correction of mechanical alignments via linear algorithm
• fast and stable
• A tough problem made easy !
Is 2
ndstep offline?
Track parameter residuals:
(d
0) = 17 m
/N
ATLAS Genova: M. Cervetto, P. Morettini, F. Parodi, C. Schiavi, presented on 20-
Nov-2002 at PESA
13th Real Time Conference 2003 Alberto Annovi
• Track finding within a road is fast
• Fitting in linear approximation
• Testing the linear fit with a fast
simulation of ATLAS Silicon Tracker
SVT TDR ’96
Impact parameter SVT simulated on real data
superimposed to real offline
SVT just started Real data
CDF run 127844 No alignment corrections
~ 45 m
~ 48 m
b
b
b
e
h b b
How to use Fast-Track to capture as much PHYSICS as possible
FTK
Hard life for all LVL2 objects!
D,Ds
D0
D0KK
BD0
Bhh BsDs*
Jets &
b-jets
Z0 bb
bbH/A bbbb tt qqqq-bb ttH qqqq-bbbb
H/A tt qqqq-bb H hh bbbb
H+- tb qqbb
ATL-DAQ-2000-033
Offline-quality b-tagging for events rich of b-quarks
with FASTRACK offline b-tag
performances @LVL2
ATLAS TP 31/3/2000
0.6 100
10 1000
b Ru
Calibration sample
“
ET200 +
j70 + j50 + j15
(||<2.5)
“
6 + j25 + j10 (||<2.5)
ATLAS + FTK
“ 4
“ 2.6
5 b-jet 237
Inclusive b-jet
CMS ATL-COM-DAQ-2002-022Sources: CMS TDR 6 & F. Gianotti, LHCC, 01/07/2002
1 3b leading
4 3 b-tags
50 mini event 2 b-jets +
Mbb > 50
160 mini ev.
2 b-tags + Mbb > 50 0.2
0.2 0.2 j200
3j90 4j65
Triggers w/o and with FTK
Scenario: L= 2 x 1033 deferral
25 j400
3j165 4j110
20 40
210
0.8
20 0.2
26
HLT rate HLT (Hz)
selection LVL1
rate (KHz) LVL1
selection
ATLAS
Events
Z b-bbar
Important b-jet calibration tool
Mbb(GeV)
CDF Run II (with SVT)
(S/B = 35)
Cdf/anal/top/cdfr/4158
Events
Mbb(GeV)
2fb-1
ATLAS + FTK 20fb
-1Problem: high L3 output rate
ATL-COM-DAQ-2002-022
Use mini events:
save FTK tracks & hits instead of full tracker data
20 Mbb > 50
3j + ET200
60 Mbb > 50
soft + 2j
LVL2
S/B
LVL1
bbH/A bbbb
Analysis:
4 b-jets |j|<2.5
PTj > 70, 50, 30, 30 GeV efficiency 10%
ATLAS-TDR-15 (1999)
Effect of jet PT cuts is even worse with deferralsMA (Gev)
tan
200
FTK triggers
LVL1 LVL2 Effic.
soft + 2j 3 b-tag 8%
3j + ET200 3b leading 13%
Electron Identification
Swapping trigger algorithms can reduce trigger rate while increasing efficiency!
CERN/LHCC/2000-17
With FTK tracks are ready on the
shelf: using tracks is even faster than using calorimeter raw data!
Efficiency & jet rejection could be enhanced by using tracks before calorimeters.
L2 tracking
High Quality tracking
13th Real Time Conference 2003 Alberto Annovi
L=2x1033 cm-2 sec-1
HLT selection @ CMS
H(200,500 GeV) 1,3h± + X)
0.4 0.5 0.6 0.7 0.8 0.9 1.
0 0.02 0.06 0.1 0.14 (QCD 50-170 GeV)
(H(200,500 GeV) 1,3h+X)
mH=500 mH=200
TRK tau on first calo jets Pix tau on first calo jet Staged-Pix tau on
first calo jet
TRK tau on both calo jets Calo tau on first jet
CERN/LHCC 02-26 CMS TDR 6 December 15, 2002
Efficiency & jet rejection could be enhanced by using tracks before calorimeters.
0.007 0.004
Trigger determina le misure di fisica al pari del rivelatore
Oggi l’uso delle tracce nel trigger e` limitato dalla potenza di calcolo necessaria
Pisa ha inventato un processore dedicato che permette di usare i tracciatori nel trigger al pari degli altri tipi di rivelatori
b-jet tagging e -jet tagging sono possibili a frequenze di ~ 50 KHz e
alta efficienza
→piu` Higgs su nastro!
Conclusioni
Backup slides
Thin Road Width: pix 1mm x 6.5cm Si 3mm x 12.5cm Medium Road Width: pix 2mm x 6.5cm Si 5mm x 12.5cm Large Road Width: pix 5mm x 6.4cm Si 10mm x 12.5cm
ATLAS Barrel (~CERN/LHCC97-16)
7 layers: 3 Pixel + 4 micro-strip (no stereo)
Cylindrical Luminosity Region: R = 1mm, z = ±15cm Generate tracks (Pt>1 GeV) & store NEW patterns
1/4
BARREL
10M patterns
13th Real Time Conference 2003 Alberto Annovi
ATLAS configuration:
12 detector layers – 5
•10
5SB/layer 128 chips/board PQ208 die: 16.3
2mm
2What chips do we have now ?
Config. Technology Status Density
(patt/chip)
CDF old full custom on-line 128
CDF old FPGA working 64
CDF current FPGA ~ designed 1000
~ATLAS old FPGA under test 32
ATLAS stand. cell 0.18 estimate (now) 11000 ATLAS stand. cell 0.1 estimate (1999) 40000
International Technology Roadmap for Semiconductor 1998
2005: patt / 9U-board
XCS40XL (.13) 64x103 Virtex (.1) 330x103 Stand. Cell (.1) 5000x103
Standalone program to produce hits from tracks, it includes:
• multiple scattering
• ionization energy losses
• detector inefficiencies
• resolution smearing
• primary vertex smearing: xy=1mm z=6cm
Detector hits generated from (Pythia):
• QCD10 sample: QCD Pt>10 GeV
• QCD40 sample: QCD Pt>40 GeV
• QCD100 sample: QCD Pt>100 GeV
• QCD200 sample: QCD Pt>200 GeV
all samples + noise + <5 MB>.
Road finding 6 layers/7 (FTK simulation)
resolutionFull hits
resolutionLow super bins
Tracking in 2 steps: find Roads, then find Tracks inside Roads
Road Super Bin
Road = Pattern
Road
Nfits
<Ncomb/road>
x
<Nroad/track>13 comb x 34 roads = ~440 comb/track 1.4 comb x 4 roads = 6 comb/track QCD Pt10 2.3 comb x 6 roads = 14 comb/track QCD Pt40 7.8 comb x 9.5 roads = 74 comb/track QCD Pt100 27 comb x 25 roads = 658 comb/track QCD Pt200
thin
thin large
large
Pt 200 Pt 100 Pt 40 Pt 10
Step 2: Software Linear Fit
Ncomb /trk
658 74
14 6
Ntrk /ev
17 16 10 8
L1 Trig jet jet soft jet
soft
L1 Rate 200Hz
<2KHz
~5KHz
~20KHz
Fits/sec 2.2MHz
<3MHz 750kHz 1.5MHz
<8MHz
Full 3D fit
fit/s 0.6 MHz
2D Fit
fit/s 2.2 MHz PIII 800MHz
2.5D Fit
fit/s 1.1 MHz
Htt 4400 fit/ev <latency> = 1ms
max latency = 100ms Pt 200 11200 fit/ev. <latency> = 3ms
only 8 CPUs (barrel)
Latency Test
Nfit /ev
11186 1184
140 48
More examples
qqH, VH bb+njets
L1: hadron L2: Mbb50
qqH WH ttH Z0H Efficiency % ~25 ~25 ~ 90 ~35
ttH bbbb+njets, H+Z0 bb+bb
L1: hadron L2: 3-b
Pythia vs CDF RUN I data
Physics background Pythia Xsec
study sample Data Xsec
pp bbbbbb 4 bjet+X 30 pp VH bbqq 2bjet+2jet 10 tt bbqqqq 2bjet+4jet 15
Multijet QCD background
Shower Monte Carlos expected to underestimate data cross-sections.
IN CDF WE OBSERVE THE OPPOSITE ?
We are studying this background:
Different Monte Carlos:
1) Herwig vs Pythia
2) matrix element calculations vs shower Monte Carlos
Hqq+HV 10 pb
6 + hadron
0.1 pb on tape
2000 H/year Hbb+Htt 1 pb
6 + hadron
0.05 pb on tape
1000 H/year gg H 30 pb
6
1 pb on tape
20000 H/year bb
bb
bb
bbbbqqqq
bbqq
bb
bbbb
bbH/Abbbb CDF
ATLAS
13th Real Time Conference 2003 Alberto Annovi
20 9U VME boards – 3 types
SUPER BINS DATA
ORGANIZER
ROADS ROADS + HITS
EVENT # N
PIPELINED AM
HITS
FASTRACK
BUFFER MEMORY BUFFER
MEMORY
Front End Tracker
DO-board
EVENT # 1
AM-board
50~100 KHz event rate
GB
Few CPUs
Offline quality Track parameters
The AM board
13th Real Time Conference 2003 Alberto Annovi
• Track confined to a road, fit is simple
• Linear expansion in the hit positions xi:
– = k (cik xi)2 final cut
– d = d0+ai xi = 0+ bi xi Pt = …
• Fit reduces to a few scalar products fast
• Constants from detector geometry
– Calculate in advance
– Correction of mechanical alignments via linear algorithm
• fast and stable
• A tough problem made easy !
AM input bandwidth = 40 MHz cluster/bus AM input buses = 6
<cluster/event> cluster rate
Pix 0 1300 65 MHz
Pix 2 + extra 1500 75 MHz SC0 + extra 1140 57 MHz SC1 + extra 1300 65 MHz
SC2 + extra 1160 58 MHz
SC3 + extra 1500 75 MHz
Ev/sec
50KHz
2 AM partitions
for the whole Pix+Si tracker More partitions as a backup option Less partitions Less hardware
conservative estimates from inner-detector & pixel TDRs
# of channles 16 106 Occupancy at High lum. 4.4 10-4
<# of hits/event> 7000 Divide by 5 for low lum. 1400 Add Hard Scattering (3MB) 2250 Add noise (10-5) 2400 Divide by 2 (<hit/cluster>) 1200 Multiply by 50KHz 60MHz
conservative estimates from inner-detector & pixel TDRs
Rate of cluster in Pix0
SVT TDR ’96
Impact parameter SVT simulated on real data
superimposed to real offline
SVT just started Real data
CDF run 127844 No alignment corrections
~ 45 m
~ 48 m
D,Ds
D0
D0KK
BD0
Bhh BsDs*
• The natural implementation of the linear fit is coupled with hits selection made by
dedicated hardware (Pisa group proposal).
But could be also an important tool for the online software selection.
• The importance of the size of (assumed) linearity region has been studied in the cases:
– Large region (0</6, ||<0.5, |z0|<10cm): the detector geometry gives the dominant
contribution to track resolution ((d0) = 90
m).
– Smallest region (each possible pattern of modules has different tuning): good results ((d0) = 17 m), but big effort is requested to tune all the detector. The memory needed in this case could be large: N possible patterns X 95 tuning constants (considering six layers) X 4 bytes (variables in float precision).
Conclusions
(by M.Cervetto on linear fit)Calorimet. LVL2 algorithm for Tau selection Efficiency for H vs. output rate
CMS-IN 2000-033
Tau Identification
13th Real Time Conference 2003 Alberto Annovi
Composition of LVL1 soft sample
26% of the events have no b-quarks inside 74% of the events have at least a b-jet:
13% direct production 27.5% flavor excitation 33.3% g splitting
23% of the events have at least 2 b-jet:
13% direct production 3% flavor excitation 7% g splitting
===========================================
no-btagging:
mjj>70 GeV Rate=1.2 ± 15% kHz double b-tagging:
mbb>70 GeV Rate=110 Hz
Level 2 rates: Pythia+ATLfast
Ideal: b=100% c =0% u,d =0%
Real: b=60% c =10% u,d =1%
Mis-tag: b=100% c =10% u,d =1%
13th Real Time Conference 2003 Alberto Annovi
ATL-DAQ-99-014
# RODS # RODS 360O in 180O in
Pix 0 36 18
Pix 2 32 16
Pixdisk 16 8
SC0-3 44 22
SCdisk 48 24
TOT 176 88
FTK inputs 24
13th Real Time Conference 2003 Alberto Annovi
Now: CDF-like configuration: 0.45 G
bit/s 6 layers - 48000 250 wide SB/Layer
•
full custom (.7)- 128 patt/chip
- 16x10
3patt/9U board
•
XCS30XL (.35) - 128 patt/chip - 16x10
3patt/9U board
•
XC2S200E (0. 186 lay) 50 euro/chip- 300 patt/chip
- 38x10
3patt/9U board
• XC2V1000 (0.158 lay – 0.12 transistors
) - 1200 patt/chip
- 153x10
3patt/9Uboard
• EP1C20F324C8 (0.1350 euro/chip
- 1100 patt/chip
- 141x10
3patt/9Uboard
• Stand.Cell (.35)
- 1000 patt/40 mm
2•
Stand.Cell (.18)- 4000 patt/40 mm
2• Stand.Cell (.13)
- 16000 patt/40 mm
2The Associative Memory CHIP
128 chips/board PQ208 (die:16.3
2mm
2)
13th Real Time Conference 2003 Alberto Annovi
2005: LHC-like configuration: 4.G
bit/s 12 layers - 500000 SB/Layer
•
XCS40XL (.13) - 64x10
3patt/9U board
•
Virtex (.1)-330x10
3patt/9U board
•
Stand.Cell (.1)- 5x10
6patt/9U board
International Technology Roadmap for Semiconductor 1998
CDF AM = 400 k pat. 4 milioni di pat.
XC2S200E55 $/chip;14000 chips: 1.4 GL XC2V1000 200$/chip; 3500 chips: 1.4 GL Standard Cell 1000 chips; 200 + 200 ML