m m 50 m 50 mmmm

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G. Rizzo 2007 IEEE Nuclear Science Symposium - Honolulu, Oct. 27 – Nov. 3 2007 1

Giuliana Rizzo

INFN and University, Pisa

on behalf of SLIM5 Collaboration

Recent developments on deep nwell CMOS MAPS with

sparsification capability

2007 IEEE Nuclear Science Symposium 2007 IEEE Nuclear Science Symposium

Honolulu, October 27

Honolulu, October 27 - - November 3 2007 November 3 2007

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Outline

• Introduction on CMOS MAPS

• Deep NWell MAPS design

the APSEL series chips

• Results on APSEL2 chips

• New developments for APSEL3

• Conclusions & Perspectives

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• Developed for imaging applications

• Several reasons make them very appealing as tracking devices :

– detector & readout on the same substrate – wafer can be thinned down to few tens of µm – radiation hardness (oxide ~nm thick)

– high functional density and versatility

– low power consumption and fabrication costs

Principle of operation

The undepleted epitaxial layer acts as a potential well for electrons

Signal (~1000 e-) collected through diffusion by the n-well contact

Charge-to-voltage conversion

provided by the sensor capacitance

small collecting electrode

Simple in-pixel readout (additionals nwells for PMOS not allowed in standard MAPS design!)

sequential readout

CMOS Monolithic Active Pixels

“Competitive” nwells for PMOS not allowed in stabdard MAPS design!

PMOS

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Deep NWell MAPS design

• Full in-pixel signal processing

realized exploiting triple well CMOS process

• Deep nwell (DNW) as collecting electrode Gain independent of the sensor capacitance collecting electrode can be extended

• Area of the “competitive” nwells inside the pixel kept to a minimum:, they steel signal to the main DNW electrode.

• Fill factor = DNW/total n-well area

~90% in the prototype test structures

• Pixel structure compatible with data sparsification architecture to improve readout speed.

PRE SHAPER DISC LATCH

New approach in CMOS MAPS design to improve the readout speed potential: APSEL chip series

• Proof of principle with the first prototypes realized in 130 nm triple well CMOS process (STMicrolectronics)

SLIM5 Collaboration - INFN & Italian University

competitive nwell Deep nwell

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Submitted DNW MAPS Chips 130 nm ST

IC group contribution:

•Pavia (PV)-Bergamo(BG) analog front-end

•Pisa(PI)-PV-BG in pixel digital logic

•Bologna-PI digital readout architecture

APSEL1

Sub. 12/2004 Sub. 8/2005 Sub. 8/2006

APSEL2_90 Sub. 9/2006

Sub. 11/2006 APSEL2D

Sub. 7/2007

APSEL3D APSEL3_T1, T2

TEST_STRUCT

ST 130 Process characterization

APSEL0

Preamplifier characteriz.

Improved F-E 8x8 Matrix

APSEL2M

Cure thr disp.

and induction

APSEL2T

Accessible pixel Study pix resp.

ST 90nm

characterization

Test digital RO architecture

8x32 matrix. Shielded pixel Data Driven sparsified readout

Test chips to optimize pixel and FE layout APSEL2_CT

Test chips for shield, xtalk

Sub. 5/2007 Sub. 7/2007

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90 Sr electrons

Landau mV

S/N=14

Cluster signal (mV)

• Noise ENC = 50 e-

• Indications of small cluster size (1-2 pixels)

• Cluster Signal for MIP (Landau MPV) 700 e-

S/N = 14 Cluster

Multiplicity

3x3 matrix, full analog output

APSEL2 3x3 matrix: analog output

Noise events properly normalized

1 2

Cluster seed

Hit pixels in 3x3 matrix

50µµµµm pixel pitch

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G. Rizzo 2007 IEEE Nuclear Science Symposium - Honolulu, Oct. 27 – Nov. 3 2007 7 8x8 matrix digital output

Sequential readout

Threshold dispersion ~ 100 e-

APSEL2 8x8 matrix: digital output

Average Noise ENC = 50 e-

Noise scan: hit rate vs discriminator threshold

Vthr Noise

90

Sr electrons: single pixel spectrum

Spectrum from analog output

Differential spectrum from digital output Vth (mV)

Noise (mV)

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Fast Readout Architecture for MAPS

• Data-driven readout architecture with sparsification and timestamp information under development.

• In the active sensor area we need to minimize:

– the logical blocks with PMOS to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor.

– digital lines for point to point connections to allow scalability of the architecture with matrix dimensions and to reduce cross talk with the sensor underneath.

Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the

periphery readout logic:

– Register hit MP & store timestamp – Enable MP readout

– Receive, sparsify, format data to output bus

APSEL2D chip received in July, tests started

- Pixel response and noise as expected

- Readout seems to work as expected, but crosstalk is present and interfering with operations

Data lines in common

2 MP private lines MP 4x4

pixels

Periphery readout logic

Column enable lines in common

Data out bus See Poster N24-260

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From APSEL2 to APSEL3

• Cross talk between digital lines and substrate – Requires aF level parasitic extraction to be modeled

• Relatively small S/N ratio (about 15)

– Especially important if pixel eff. not 100%

• Power dissipation 60 µµµµW/pixel – Creates significant system issues

M1 M2 M3 M5 M6

M4

Analog routing (local)

Digital routing (local/global) Shield

(VDD/GND )

APSEL3 Redesigned front-end/sensor

APSEL3D Digital lines shielding

Optimize FE Noise/Power:

• Reduce sensor capacitance (from 500 fF to

~300 fF) keeping the same collecting electrode area

– reduce DNW sensor/analog FE area (DNW large C) – Add standard NWELL area (lower C) to collecting

electrode.

• New design of the analog part

Optimize sensor geometry for charge collection efficiency using fast simulation developed:

– Locate low efficiency region inside pixel cell – Add ad hoc “satellite” collecting electrodes

APSEL3 Power=30 µµµµW/pixel: Perfomance APSEL2 issues

APSEL3 expected performance

APSEL3

Curr. Mirror

APSEL3 Transc.

APSEL2

^data

FE Version

22 24 98.6%

99.9%

31 e- 31 e- A

B

16 18 93.6%

99.4%

41 e- 41 e- A

B

14 88.7%

50 e- A

εεεε

^(@5

^σσσσ

⁾⁾⁾⁾ S/N

ENC

(PLS) Geom

.

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The cure for the crosstalk (APSEL2_CT)

• Dedicated test structures for crosstalk study on sensor with/without metal shield just received.

• First tests indicate shield is effective!

• Induced signal by digital transition (1.2V)

reduced in pixel with the metal shield w.r.t no shielded version.

• Residual crosstalk in shielded pixels below the level of the pixel noise (50 e- ~ 5mV)

• Still to investigate origin of the positive lobe…though seems not related to the digital signal on the line crossing the pixel

no shield

with shield

sensor

shield

No shield

Digital lines

Logic to connect digital signal to lines crossing the pixel

10 mV/div

1 us/div

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• First look at the crosstalk in the latest APSEL3 pixel just arrived:

– Only pixel with metal shield available

– Only a few lines crossing the sensor (connected to output pads)

• Residual crosstalk in shielded pixel (4-7 mV) at the level of the pixel noise (6.5 mV). Not yet calibrated in ENC (~ 40 e- expected from post layout simulation).

The cure for the crosstalk in APSEL3

2 mV/div

1 us/div

Shielded pixel output signal 3x3 matrix in APSEL3

Shielded pixel output

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An example of sensor optimization

DNW collecting electrode Competitive Nwells

3x3 MATRIX old sensor geom

Satellite nwells

connected to central DNW elect 3x3 MATRIX sensor optimized

• With old sensor geometry (left) Efficiency ~ 93.5% from simulation (pixel threshold @ 250 e- = 5xNoise)

• Inefficient regions shown with dots (pixel signal < 250 e-)

• Cell optimized with satellite nwells (right) Efficiency ~ 99.5%

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APSEL3D

• 256 pixel matrix with sparsified readout and timestamp - submitted 7/2007

• Innovative mixed mode design

– Pixel cell with full custom design and layout

– Sparsifying logic synthetized in std-cell from VHDL model

• Essential for large matrix design with complex logic

• Encouraging results on hit efficiency from VHDL simulation:

ε > 99% with hit rate up to several hundreds MHz/cm

²

(small matrix/preliminary study)

256 pixels - 50 µµµµ m pixel pitch

See Poster N24-260 A.Gabrielli

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Conclusions & Perspectives

• DNW MAPS design (130 nm, triple well STM CMOS technology) looks very promising for application in future thin trackers with fast readout requirements.

– Latest DNW MAPS (APSEL2) structures, with optimized noise and

threshold dispersion, showed good sensitivity to ionizing radiation (soft X and beta).

– New improvements in noise, power, charge collection efficiency implemented in the APSEL3 series (just received).

– Digital crosstalk can be kept under control using metal shield between sensor and digital lines.

– Data driven readout architecture with sparsification and timestamp under development: 8x32 matrix produced, 32x128 matrix in

production by end Nov. 2007.

• Test beam foreseen in summer 2008 to measure DNW MAPS rate capability, efficiency, resolution.

• DNW MAPS sensors, developed within the SLIM5 Collaboration,

now considered by the SuperB and ILC communities for application

in their silicon vertex trackers.

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• Basic R&D on DNW CMOS MAPS started in 2004 within the SLIM5 Collaboration.

– Several Italian Institutions involved in the project:

• BO, PI (coordination), PV-BG, TO, TN, TS.

– R&D project supported by the INFN and the Italian Ministry for Education, University and Research.

SLIM5- Silicon detectors with Low Interactions with Material

Realize a demonstration thin silicon tracker with LVL1 trigger capabilities:

• CMOS monolithic active pixels

• Thin strip detectors on high resistivity silicon

• Associative memory system for track trigger

• Low mass mechanical support and services

Test beam foreseen in 2008 to measure rate capability, efficiency,resolution SLIM5 Purpose: develop technology for thin silicon tracker systems (sensor/

readout/ support structure/ cooling) crucial to reduce multiple scattering effects for future collider experiments (SuperB, ILC)

SLIM5

Project

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1

Università degli Studi di Pisa,

²

INFN Pisa,

³

Scuola Normale Superiore di Pisa,

4

Università degli Studi di Pavia,

⁵

INFN Pavia,

6

Università degli Studi di Bergamo,

7

INFN Trieste and Università degli Studi di Trieste

8

INFN Bologna and Università degli Studi di Bologna

9

INFN Torino and Università degli Studi di Torino

10

Università degli Studi di Trento and INFN Padova

11

Università degli Studi di Modena e Reggio Emilia and INFN Padova

,

,

,

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Backup

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sensor

• Residual crosstalk present in the shielded pixel not related to digital transition on line crossing the pixel:

– When digital signal is send to the logic used to select a particular line but no line is activated same effect present on both pixel!

no shield

with shield shield

No shield

Digital lines

Logic to connect digital signal to lines crossing the pixel

The cure for the crosstalk (APSEL2_CT)

10 mV/div

1 us/div

No digital signal crossing the pixels

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Pixel gain calibration

Gain measured with a calibration capacitor and the Fe55 calibration peak (15% difference observed)

• 5.9 keV line (1640 e-) with charge totally collected by a single pixel

⊕

PWELL NWELL

P^-EPI-LAYER

P⁺⁺SUBSTRATE PWELL

INCIDENT PHOTONS

Charge entirely collected

DEPLETION REGION Charge

only partially collected by single pixel

⊕

Gain=577 mV/fC

Gain=490 mV/fC

Charge injected on calibration capacitor

Fe55 Calibration Peak

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MAPS Radiation Hardness

• Expected Background @ Layer0:

– Dose = 6Mrad/yr

– Equivalent fluence = 6x10

¹²

n

_eq

/cm

²

/yr

• CMOS redout electronics (deep submicron) rad hard

• MAPS sensor - Radiation damage affects S/N

• Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping)

^fluences ^{∼ 10}

¹²

ⁿ

eq

/cm

²

affordable, 10

¹³

n

_eq

/cm

²

possible

• Ionizing radiation: noise increase, due to higher diode leakage current (surface damage)

OK up to 20 Mrad with low integration time (10 µs) or T operation < 0

^o

C, or modified pixel design to improve it

• Irradiation test performed on several MAPS prototypes, with standard nwell sensor, indicate application for SuperB is viable.

• APSEL chips irradiation started this summer ….

Results from standard nwell MAPS prototypes

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Pixel Cell optimization: Signal

• Developed a fast simulation of the device (ionization and diffusion) to optimize the sensor geometry

- APSEL2 data + Fast Simulation

90

Sr electrons

– Detailed device simulation (ISE- TCAD) gives similar results

– Fair agreement among data and Fast Simulation

– Need further tuning of the sensible parameters

Fast Simulation identifies low efficiency regions inside pixel

– Improve efficiency adding in these areas small satellite nwells

connected to the main DNW electrode (low contribution to the total sensor capacitance)

– Satellite nwells in the surroundings of the competitive nwell very

effective to increase the efficiency

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Noise/power trade-off in Apsel3

42 16/0.25

30 60 460

APSEL2 I II III

ENC@200 ns [electrons

rms]

Input device dimensions

[µµµµm/µµµµm]

Input device drain current

[µµµµA]

Analog power dissipation

[µµµµW]

Detector capacitance

[fF]

40 4/0.25

5 8 140

30 17

140 140

25 30

10/0.25 4/0.25

20 12

schematic simulations

•Noise/power trade-off can take advantage of the substantial

reduction in the sensor capacitance

Final design sensor

capacitance ~ 150 – 300 fF

50 µµµµm 50µµµµm

DEEP NWELL

(digital and MIM capacitors section

not present)

DEEP NWELL Collecting electrode

NWELL NWELL

PWELL

Shaper input MiM cap.

Shap er feed back MiM cap.

APSEL2

50 µm

Only deep nwell area shown

APSEL3

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APSEL3T1 pixel cell

DNW + NMOS Analog section

PMOS Analog section

Digital

section Nwell satellite

collecting electrodes

50 µµµµ ^m

Sensor geometry B Sensor geometry A

50

µµµµ

^m

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