Immagini, riferimenti fonti per capitolo

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Immagini, riferimenti fonti per capitolo Capitolo 2: Figura 2.1 http://originalpeople.org/ishango-bone-worlds-oldest-math-tool/ Figura 2.2 https://it.wikipedia.org/wiki/Monti_Lebombo http://www.math.buffalo.edu/mad/Ancient-Africa/lebombo.html Figura 2.3 http://www.viaggionelmistero.it/confini-conoscenza/scoperte-enigmatiche/osso-di-ishango-primo-calcolatore-storia

Figura sui numeri sumeri pagina 31 http://www.scienceforpassion.com/2011/12/anche-i-numeri-hanno-una-storia.html

Figura tavolette argilla sumeri pagina 31 http://cicloinf.dimi.uniud.it/mostra/Pagina03.html e "Note sulla storia del concetto di numero." A. Gimigliano

Figure sui calami pagina 32 "Note sulla storia del concetto di numero." A. Gimigliano

Figure numeri egizi pagina 32 http://progettomatematica.dm.unibo.it/NumeriAdditivi/egizi.html "Matematica nell'antico Egitto" a cura del Prof. Masismo Amato

Figura papiro Hind pagina 33 "Note sulla storia del concetto di numero." A. Gimigliano Figura di testa pagina 34 "Note sulla storia del concetto di numero." A. Gimigliano

http://www.scienzagiovane.unibo.it/numeri/5-cifre.html

http://cellulenumeriealtro.blogspot.it/2013/08/antichi-sistemi-di-numerazione.html

Figura pagina 35 Ab¯u Jafar Muhammad ibn M¯us¯a al-Khw¯arizm¯ https://it.wikipedia.org/wiki/Muhammad_ibn_Musa_al-Khwarizmi

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Figura 2.4, 2.5 e pagina 41 in testa http://www.giovannipastore.it/ANTIKYTHERA.htm

Figura 2.6 https://it.wikipedia.org/wiki/Ingranaggio

Figura pagina 42 astrolabio https://it.wikipedia.org/wiki/Storia_dell%27astronomia

Figura 2.7 destra https://archeocomputing.wordpress.com/tag/regolo/

Figura 2.7 sinistra http://www.profesorenlinea.cl/matematica/logaritmos_Historia.html

Figura 2.8 http://ex-sheffield.org/soloparaingenierosnet/2015/01/10/la-regla-de-calculo/

Figura pagina 44 abaco http://progettomatematica.dm.unibo.it/NumeriAdditivi/curiosit02.html

Figura 2.9 abaco cinese

http://www.museoscienza.org/approfondimenti/documenti/macchina_poleni/storia2.asp

Figura pagina 46 Galileo Galilei "Calcolatori meccanici" Paolo Giangrandi Figura 2.10 "Calcolatori meccanici" Paolo Giangrandi

Figura testa triangoli simili pagina 47 "Calcolatori meccanici" Paolo Giangrandi Figura compasso di proporzione pagina 47 "Calcolatori meccanici" Paolo Giangrandi Figura pagina 48 riporto "Calcolatori meccanici" Paolo Giangrandi pagina 57 Figura 2.11 http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html

Figura bastoncini di Nepero pagina 50

https://php.math.unifi.it/archimede/archimede/laboratori/appunti/bastoncini.pdf Figure pagina 51,52,53 https://php.math.unifi.it/archimede/archimede/laboratori/appunti/bastoncini.pdf Figura 2.12 http://www.museoscienza.org/approfondimenti/documenti/macchina_poleni/vita.asp Figura pagina 54 http://www.museoscienza.org/approfondimenti/documenti/macchina_poleni/vita.asp

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Figura 2.13, 2.14 http://www.museoscienza.org/approfondimenti/documenti/macchina_poleni/macchina_aritmetica.as p Figura 2.15 sinistra http://www.handelforever.com/VersaillesSuprema/versailles/versaillesnews/laprimacalcolatricedibla isepascal.htm

Figura 2.15 destra https://it.wikipedia.org/wiki/Blaise_Pascal

Figura pagina 58 The Calcumeter http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html

Figure pagina 59 in testa e 2.16 http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html

Figura 2.17 sinistra https://evoluzionedelcomputer.wordpress.com/2012/06/10/tesina-5/

Figura 2.17 destra https://es.wikipedia.org/wiki/Stepped_Reckoner

Figure pagina 62 "Calcolatori meccanici" Paolo Giangrandi pagine 73 e 74 Figura 2.18 "Calcolatori meccanici" Paolo Giangrandi pagina 78

Figura 2.19 "Calcolatori meccanici" Paolo Giangrandi pagina 82 Figura 2.20 http://www.tecnoteca.it/museo/08 Babbage

Figura pagina 66 macchina analitica http://www.tecnoteca.it/museo/08 Figura 2.21 https://it.wikipedia.org/wiki/Ada_Lovelace

Figura pagina 67 fondo https://it.wikipedia.org/wiki/Luigi_Federico_Menabrea Figura 2.22 https://it.wikipedia.org/wiki/Macchina_analitica

Figura pagina 68 Colmar http://www.oacn.inaf.it/museo/costruttori.php?id=15 Figura 2.23 sinistra http://www.mhs.ox.ac.uk/staff/saj/arithmometer/ Figura 2.23 destra http://www.oacn.inaf.it/museo/strumenti.php?id=1 Figura 2.24 http://enhancedwiki.territorioscuola.it/?

title=File:DesktopMechanicalCalculators_inProduction_intheXIXCentury.svg Figura 2.25 https://www.ithistory.org/honor-roll/mr-curt-herzstark

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Figura 2.26 destra http://www.core77.com/posts/52367/The-Rocky-Road-for-the-Curta-the-First-Mass-Market-Pocket-Calculator

Figura 2.26 sinistra e centro

http://www.museoscienza.org/dipartimenti/catalogo_collezioni/scheda_oggetto.asp? idk_in=ST120-00179&arg=Calcolo

Figura 2.27 destra https://it.wikipedia.org/wiki/Claude_Perrault

Figura 2.27 sinistra, centro http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html Figura 2.28 http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html

Figura 2.29 https://de.wikipedia.org/wiki/Gottfried_Wilhelm_Leibniz

Figura pagina 74 testa http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html Figura 2.30 sinistra http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html Figura 2.30 centro https://en.wikipedia.org/wiki/Willgodt_Theophil_Odhner Figura 2.31 http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html

Figura 2.32, 2.33 https://it.wikipedia.org/wiki/Comptometer Figura 2.34 https://it.wikipedia.org/wiki/Herman_Hollerith

Figura 2.35 sinistra http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html Figura 2.35 destra https://www.madas.ch/?page_id=5803

Figura 2.36 http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html Figura 2.37 destra http://www.rauck.net/friden/History-06.htm

Figura 2.37 sinistra http://www.hpmuseum.org/ec132.htm Figura 2.38 http://retrocalculators.com/sundstrand.htm

Figura 2.39 http://www.nicolamarras.it/calcolatoria/storia_calcolatori.html

Figura pagina 81 "Appunti su algoritmi, macchine di Turing, computabilità", Marcello Frixione Figura 2.40 Computer Science - The First Computers History and Architectures - Rojas (MIT 2000

Figura 2.41 https://it.wikipedia.org/wiki/Alan_Turing Figura 2.42 http://www.engeene.it/test-turing-cosa-significa/

Figura 2.43 http://www.xlsemanal.com/conocer/20120212/conocer-historia-nacimiento-turing-1609.html

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Figura pagina 88 Konad Zuse http://www.windoweb.it/edpstory_new/ep_zuse.htm Figura 2.44 http://history-computer.com/ModernComputer/Relays/Zuse.html

Figura 2.45, 2.46, 2.47, 2.48, 2.49, 2.50 The Z1: Architecture and Algorithms of Konrad Zuse’s First Computer, Raul Rojas

Figura pagina 93 The Z1: Architecture and Algorithms of Konrad Zuse’s First Computer, Raul Rojas

Figura pagina 95 Zuse Z3 http://history-computer.com/ModernComputer/Relays/Zuse.html Figura 2.51 sinistra http://www.ingenieur.de/Themen/IT-Hardware/Konrad-Zuses-Z3-Computer-Welt-75

Figura 2.51 destra

http://www.deutsches-museum.de/en/exhibitions/communication/computers/universal-computers/

Figura pagina 96 Rappresentazione in virgola mobile nella Z3 The First Computers— History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000

Figura 2.52, 2.53 Rappresentazione in virgola mobile nella Z3 The First Computers— History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000

Figura pagina 98 Unità di controllo microprogrammata Rappresentazione in virgola mobile nella Z3 The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000

Figura pagina 99 Rappresentazione in virgola mobile nella Z3 The First Computers— History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 194

Figura 2.54

http://www.horst-zuse.homepage.t-online.de/Konrad_Zuse_index_english_html/rechner_s1.html Figura 2.55

http://www.horst-zuse.homepage.t-online.de/Konrad_Zuse_index_english_html/rechner_z4.html

Figura 2.56 http://history-computer.com/ModernComputer/Relays/Zuse.html Figura 2.57 destra https://de.wikipedia.org/wiki/Z22

Figura 2.57 sinistra https://www.flickr.com/photos/joachim_s_mueller/5205670311 Figura 2.58 "DIE ELEKTRONISCHE RECHENMASCHINE

ZUSE Z 22" Von Günter K I e m t, Kreuznach file in formato pdf Figure pagina 104 Variabili in Plankalkül

http://page.mi.fu-berlin.de/rojas/pub/computer_history/m_z/plankalkuel.pdf pagine 1 e 2 Figura 2.59 pubblicazione formato pdf Elektronenrechner_Z_23_ pagina 1

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Figura 2.60 http://www.horst-zuse.homepage.t-online.de/z5.html Figura 2.61 https://en.wikipedia.org/wiki/Z11_(computer)

Figura 2.62, 2.63 http://www.computerhistory.org/projects/zuse_z23/index.shtml

Figura 2.64 sinistra http://www.computerhistory.org/projects/zuse_z23/index.shtml Figura 2.64 destra

http://www.horst-zuse.homepage.t-online.de/Konrad_Zuse_index_english_html/rechner_z25.html Figura 2.66 centro https://en.wikipedia.org/wiki/Ring_modulation

Figura 2.66 sinistra, destra The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 250

Figura 2.65 destra https://en.wikipedia.org/wiki/Helmut_H%C3%B6lzer

Figura 2.65 sinistra, centro https://forum.nasaspaceflight.com/index.php?topic=41042.0 Figura 2.67 The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 231

Figura 2.68 sinistra The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 242

Figura 2.68 destra The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 237

Figura pagina 109 The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 109

Figura 2.69 "Il funzionamento della macchina enigma, dettagli tecnici", disegni e foto sono © Dirk Rijmenants 2004 - 2013 Traduzione italiana: Silvio Coccaro www.silcosoft.it

Figura 2.70 http://weidepan.altervista.org/storia3/? doing_wp_cron=1511454933.8845040798187255859375

Figura 2.71 http://www.di-srv.unisa.it/~ads/corso-security/www/CORSO-0203/Enigma/testo.htm Figura 2.72 http://users.telenet.be/d.rijmenants/en/enigmatech.htm

Figura 2.73 "Il funzionamento della macchina enigma, dettagli tecnici", disegni e foto sono © Dirk Rijmenants 2004 - 2013 Traduzione italiana: Silvio Coccaro www.silcosoft.it pagina 2 Figura 2.74 "Il funzionamento della macchina enigma, dettagli tecnici", disegni e foto sono © Dirk Rijmenants 2004 - 2013 Traduzione italiana: Silvio Coccaro www.silcosoft.it pagina 3 Figura 2.75 "Il funzionamento della macchina enigma, dettagli tecnici", disegni e foto sono © Dirk Rijmenants 2004 - 2013 Traduzione italiana: Silvio Coccaro www.silcosoft.it pagina 11

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Figura 2.76 "Il funzionamento della macchina enigma, dettagli tecnici", disegni e foto sono © Dirk Rijmenants 2004 - 2013 Traduzione italiana: Silvio Coccaro www.silcosoft.it pagina 12 Figura pagina 116 cifratrice Lorenz https://it.wikipedia.org/wiki/Lorenz_(cifratrice)

Figura 2.77 http://www.antonioeteresa.net/La%20trasmissione%20delle%20informazioni%20-%20Quinta%20parte.htm

Figura 2.78 http://www.wow-wordsoftheworld.it/27-2015/marzo-maggio-2015/45-una-epica-lotta-di-macchine-cap-3-colossus-1-500-valvole-per-il-primo-calcolatore-elettronico

Figura 2.79 sinistra https://it.wikipedia.org/wiki/John_Tiltman Figura 2.79 http://www.colossus-computer.com/colossus1.html

Figura pagina 119 Colossus http://www.colossus-computer.com/colossus1.html Figura pagina 120 Bletchley Park http://lowther-forestry.co.uk/2016/01/

Figura pagina 120, nota 50 inseguitore catodico http://www.leradiodisophie.it/Del-Ciotto-Tubi/09AmplBLargaEA4.pdf

http://page.mi.fu-berlin.de/rojas/pub/computer_history/m_z/plankalkuel.pdf http://www.cdvandt.org/Hoelzer%20V4.pdf

https://it.wikipedia.org/wiki/Lorenz_(cifratrice)

Figura pagina 122 pannello di controllo principale Colossus http://www.colossus-computer.com/colossus1.html

Figura pagina 123 Thyratron https://www.codesandciphers.org.uk/lorenz/colossus.htm

Figura 2.80 http://collection.sciencemuseum.org.uk/objects/co8418186/replica-of-the-baby-or-ssem-computer-valve-computer Figura 2.81 https://en.wikipedia.org/wiki/Ferranti_Mark_1 Figura 2.82 http://history-computer.com/ModernComputer/Electronic/SSEM.html Figura 2.85, 2.86 https://en.wikipedia.org/wiki/Manchester_Mark_1 Figura 2.87 http://curation.cs.manchester.ac.uk/digital60/www.digital60.org/rebuild/50th/gallery/gallery1/index. html

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Figura 2.88 https://blog.sciencemuseum.org.uk/alan-m-turing-and-colleagues-working-on-the-ferranti-mark-i-comp/

Figura 2.89 http://curation.cs.manchester.ac.uk/computer50/www.computer50.org/mark1/ip-fm1.crt.html

Figura 2.90 "The Atlas story", Simon Lavington https://elearn.cs.man.ac.uk/~atlas/docs/The %20Atlas%20story.pdf

Figura 2.91 https://elearn.cs.man.ac.uk/~atlas/docs/The%20Atlas%20story.pdf pagina 20 Figura 2.92 https://www.radiomuseum.org/tubes/tube_oc170.html

http://www.semicon-data.com/transistor/tc/oa/OC170.html

Figura 2.93 https://elearn.cs.man.ac.uk/~atlas/docs/The%20Atlas%20story.pdf pagina 19 Figura 2.94 The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 307

Figura 2.95 "EDSAC, 99" 15-16 April Cambridge University https://www.cl.cam.ac.uk/events/EDSAC99/reminiscences/

Figura 2.96 sinistra "EDSAC, 99" 15-16 April Cambridge University booklet formato pdf pagina 28

Figura 2.96 destra https://it.wikipedia.org/wiki/Midlands

Figura 2.97 The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 320 e 321

Figura 2.98 http://www.gettyimages.it/detail/fotografie-di-cronaca/this-meccano-model-was- built-by-douglas-hartree-fotografie-di-cronaca/90736198#this-meccano-model-was-built-by-douglas-hartree-based-on-the-built-picture-id90736198

Figura 2.99 http://history-computer.com/People/AtanasoffBio.html

http://www4.ncsu.edu/~belail/The_Introduction_of_Electronic_Computing/Atanasoff-Berry_Computer.html

Figura 2.100 destra John Vincent Atanasoff – The Inventor of the First Electronic Digital Computing - Prof. Kiril Boyanov

Figura 2.100 sinistra https://commons.wikimedia.org/wiki/File:Atanasoff-Berry_Computer_at_Durhum_Center.jpg

Figura 2.101 John Vincent Atanasoff – The Inventor of the First Electronic Digital Computing - Prof. Kiril Boyanov pagina 4

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Figura 2.102 Calcolatore Mark I manuale operativo pagina 5 del 1946 Figura 2.103 http://sites.harvard.edu/~chsi/markone/function.html Figura 2.104 Calcolatore Mark I manuale operativo pagina 35 del 1946

Figura 2.105 sinistra https://www.tomshw.it/storia-supercomputer-dal-1936-oggi-parte-1-25177

Figura 2.105 destra Calcolatore Mark I manuale operativo pagina 24 del 1946 Figura 2.106 Calcolatore Mark I manuale operativo pagina 39 del 1946

Figura 2.107 The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 101

Figura 2.109 sinistra http://csebtechnotes.blogspot.it/2014/07/types-of-cpu-architecture-accumulator.html

Figura 2.109 destra The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 104

Figura 2.114 http://www.computerhistory.org/collections/catalog/102680098

Figura 2.115 sinistra https://borislimpopo.com/2012/08/21/le-regole-auree-del-previsore-ideale-secondo-julian-bigelow/

Figura 2.115 destra https://it.pinterest.com/blogmobil/beautiful-minds/ Von Neumann Figura 2.116 sinistra https://en.wikipedia.org/wiki/JOHNNIAC

Figura 2.116 destra https://es.wikipedia.org/wiki/Selectr%C3%B3n Figura 2.117

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Figura 2.118 https://en.wikipedia.org/wiki/ORDVAC

Figura 2.119 https://it.wikipedia.org/wiki/UNIVAC_I https://www.thocp.net/hardware/univac.htm http://ethw.org/UNIVAC

Figura 2.120 https://en.wikipedia.org/wiki/UNIVAC_1101

Figura 2.121 ENIAC on a chip, http://www.seas.upenn.edu/~jan/eniacproj.html

Figura 2.122 destra "Il programma memorizzato" Genesi, significato e diffusione di un'idea, Silvio Hénin

Figura 2.122 sinistra https://it.wikipedia.org/wiki/EDVAC

Figura 2.123 Jonathan von Neumann and EDVAC Philip Levis November 8, 2004 pagina 4 Figura 2.124 https://en.wikipedia.org/wiki/SEAC_(computer)

Figura 2.125 sinistra "Metropolis, Monte Carlo and the MANIAC" H. L. Anderson pagina 10 Figura 2.125 destra http://informaticaitaliana.blogspot.it/2012/04/maniac.html

Figura 2.126 destra http://www.mirrorservice.org/sites/www.bitsavers.org/pdf/mit/tx-0/pics/? C=N;O=D

Figura 2.126 sinistra https://eptaweb.it/blog/curiosita-informatiche/38_storia-del-computer-le-5-generazioni

Figura 2.127 destra https://commons.wikimedia.org/wiki/File:SAGE_computer_room.jpg Figura 2.127 sinistra http://www.radomes.org/museum/equip/fsq-7.html

Figura 2.128 http://www.columbia.edu/cu/computinghistory/650.html Figura 2.129 Manuale IBM 709 pagina 2

Figura 2.130 sinistra http://www.columbia.edu/cu/computinghistory/701.html Figura 2.130 destra https://en.wikipedia.org/wiki/Williams_tube

Figura 2.131 https://en.wikipedia.org/wiki/IBM_SSEC

Figura 2.132 Manuale IBM moltiplicatore elettronico 603 pagina 4

Figura pagina 173, calcolatori costruiti in Giappone The First Computers—History and Architectures, edited by Raúl Rojas and Ulf Hashagen, 2000 pagina 322

Figura pagina 176, parametron https://www.thocp.net/hardware/parametron.htm

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Figura 2.135 http://www.webtotale.it/sfide-connettere-la-programma-101-ad-internet/ Figura 2.136 https://www.inexhibit.com/it/case-studies/olivetti-programma-101-la-storia-ed-il-design-primo-personal-computer/ Figura 2.137 https://www.giornalelavoce.it/la-nascita-del-personal-computer-una-storia-canavesana-78947 Figura 2.138 http://www.olivettiani.org/ricordi-di-mauro-ii.html Figura 2.139 http://www.computerhistory.it/index.php? option=com_content&view=article&id=20&Itemid=139 Figura 2.140 http://www.computerhistory.it/index.php? option=com_content&view=article&id=20&Itemid=139

Figura pagina 186 CEP pisana "La Calcolatrice Elettronica Pisana e la Macchina Ridotta", Donati Michela, Relazione Seminario di Cultura Digitale

Figura 2.141 https://cctld.it/storia/doc/lettera_fermi.html Figura 2.142, 2.143 http://hmr.di.unipi.it/Archivio.html

Figura 2.144 http://www.aisdesign.org/aisd/ettore-sottsass-jr-e-il-design-dei-primi-computer-olivetti

Figura pagina 194, avviso Olivetti http://matematica.unibocconi.it/articoli/mario-tchou-e-lelettronica-italiana

Figura 2.145 Paolo_Monti_-_Servizio_fotografico_(Italia,_1968) https://commons.wikimedia.org/wiki/File:Paolo_Monti_-_Servizio_fotografico_(Italia,_1968)_-_BEIC_6346627.jpg

Figura 2.146 ELEA 9002 http://www.storiaolivetti.it/fotogallery.asp? idPercorso=628&idOrd=10#viewfotogallery

Figura 2.147

http://www.corsi.storiaindustria.it/areetematiche/prodotti/008/002/approfondimenti/elea.shtml Figura pagina 194, calcolatore ELEA 9003 http://filibertobiolca.altervista.org/pagina-705183.html Figura 2.148 http://iltemporitrovatodiantonella.blogspot.it/2013/10/

Figura 2.149 http://www.storiaolivetti.it/fotogallery.asp? idPercorso=627&idOrd=3#viewfotogallery

Figura 2.150 http://www.vintagecalculators.com/html/ncr_18-16___busicom_junior.html Figura 2.151 http://www.vintagecalculators.com/html/busicom_le-120a___le-120s.html

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Figura 2.152 http://www.hpmuseum.org/hp9100.htm Figura 2.153 http://www.hpmuseum.org/hp9810.htm Figura 2.154 http://www.hpmuseum.org/hp9820.htm Figura 2.155 http://www.hpmuseum.org/hp9830.htm Figura 2.156 http://www.hpmuseum.org/hp9805.htm Figura 2.157 http://www.hpmuseum.org/hp9815.htm Figura 2.158 http://www.hpmuseum.org/35fam6.jpg Figura 2.159 http://www.vintagecalculators.com/html/hewlett_packard.html Figura 2.160 http://www.hpmuseum.org/41cv.jpg Figura 2.161 http://www.hpmuseum.org/71.jpg Capitolo 3:

Figura 3.1 Tesi di Laurea Triennale "FENOMENI DI TRASPORTO IN DIODI E TRANSISTORI MOS" Antonio Bruno, capitolo 1 pagina 8

Figura 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 3.10, 3.11, 3.12, 3.13, 3.14, 3.15, 3.16, 3.17, 3.18, 3.19, 3.20, 3.21, 3.22, http://www.computerhistory.org/siliconengine/timeline/

Figura 3.5 sinistra https://it.wikipedia.org/wiki/Walter_Schottky

Figura pagina 230 Dov Froman http://www.computerhistory.org/siliconengine/timeline/ Figure pagina 231 Robert Dennard, TMS 1000, Microma liquid crystal display

http://www.computerhistory.org/siliconengine/timeline/

Figura 3.23 sinistra http://www.computerhistory.org/revolution/memory-storage/8/368/1017 Figura 3.23 destra http://gigazine.net/gsc_news/en/20150831-intel-cpu-history/

Figure pagina 232 John Birkner e H. T. Chua, DSP-1 http://www.computerhistory.org/siliconengine/timeline/ Figura 3.24

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Figura 3.25 A Brief History of Silicon Valley, Nick Milner Milner Company Marketing LLP pagina 5

Figura 3.26, 3.27, http://www.nzeldes.com/HOC/IntelFirsts.htm

Figura biografia Robert Noyce pagina 237, "The man behind the microchip" Leslie Berlin Figura 3.28 Brevetto US2981877

Figura biografia Gordon E. Moore pagina 238

https://www.intel.com/pressroom/kits/events/moores_law_40th/ Figura National Medal of Technology and Innovation pagina 239

https://it.wikipedia.org/wiki/National_Medal_of_Technology_and_Innovation

Figura biografia Andrew Grove pagina 239 https://it.wikipedia.org/wiki/Andrew_Grove Figura biografia Federico Faggin pagina 240

http://www.corriere.it/reportages/tecnologia/2017/federico-faggin/

Capitolo 4:

Figura pagina 245 Gordon E. Moore http://www.personal.psu.edu/lxb5198/Assign_6.html Figura 4.1 sinistra "Understanding Moore’s law : four decades of innovation" pagina 71 David C. Brock Chemical Heritage Foundation

Figura 4.1 destra Intel Data Catalog 1975 sezione 4-20

Figura 4.2 "Understanding Moore’s law : four decades of innovation" pagina 70 David C. Brock Chemical Heritage Foundation

Figura 4.3 "Understanding Moore’s law : four decades of innovation" pagina 85, 87 David C. Brock Chemical Heritage Foundation

Figura 4.4 sinistra "Understanding Moore’s law : four decades of innovation" pagina 88 David C. Brock Chemical Heritage Foundation

Figura 4.4 destra "Understanding Moore’s law : four decades of innovation" pagina 89 David C. Brock Chemical Heritage Foundation

Figura 4.5 sinistra Albert Yu Intel IEEE Micro pagina 2 1996 "The Future of Microprocessors"

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Figura 4.6 The Lives and the Death of Moore’s Law Ilkka Tuomi Visiting Scientist Joint Research Centre Institute for Prospective Technological Studies ilkka.tuomi@jrc.es pagina 16 Figura 4.7 The Lives and the Death of Moore’s Law Ilkka Tuomi Visiting Scientist Joint Research Centre Institute for Prospective Technological Studies ilkka.tuomi@jrc.es pagina 17 Figura 4.8, 4.9 The Lives and the Death of Moore’s Law Ilkka Tuomi Visiting Scientist Joint Research Centre Institute for Prospective Technological Studies ilkka.tuomi@jrc.es pagina 19, 20

Figura 4.10 regola di Pollack https://cacm.acm.org/magazines/2011/5/107702-the-future-of-microprocessors/fulltext figura 2 The Future of Microprocessors Shekhar Borkar, Andrew A. Chien Communications of the ACM, Vol. 54 No. 5, pagine 67-77

Figura 4.11 "Extreme Ultraviolet Litography", Imaging the future S&TR novembre 1999, Lawrence Livermore Laboratory pagina 3

Figura 4.12 Immersion Lithography Stretching the limits of Deep UUV lithography John Culver March 13, 2006 pagina 3

Figura 4.13 Immersion Lithography Stretching the limits of Deep UUV lithography John Culver March 13, 2006 pagina 5

Figura 4.14 Design of High-Performance Microprocessor Circuits - A. Chandrakasan, et. al., (IEEE, 2001) pagina 48

Figura 4.15 sinistra

http://meroli.web.cern.ch/meroli/lecture_scaled_CMOS_Technology.html http://meroli.web.cern.ch/meroli/link.html

Figura 4.15 destra Tesi di Laurea Triennale "Dissipazione di Potenza nei Circuiti CMOS: Origini e Tecniche per la Riduzione" Giovanni Bruni

Figura 4.16 Laurea Triennale in Ingegneria Elettronica "Legge di Moore e Tecnologie Microelettroniche Future" Andrea Muraro pagina 15

Figura 4.17 http://jestec.taylors.edu.my/Vol%2010%20issue%203%20March%202015/Volume %20(10)%20Issue%20(3)%20364-382.pdf pagina 3

Figura 4.18 presentazione "Leakage in MOS devices" Mohammad Sharifkhani

http://slideplayer.com/slide/1653602/7/images/18/Subthreshold+leakage+(Temperature+Effect).jpg Figura 4.19 "MOS Scaling Transistor Challenges for the 21st Century" Mark Bohr, Portland Technology Development, Intel Corp. Pagina 2

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Figura 4.20 snistra "Understanding Moore’s law : four decades of innovation" pagina 91 David C. Brock Chemical Heritage Foundation

Figura 4.21 File formato pdf Intel "Press45nm107_FINAL" pagina 4

Figura 4.22, 4.23, 4.24 "Overview of the Use of Copper Interconnects in the Semiconductor Industry" Annabelle Pratt, Ph.D., Advanced Energy Industries, Inc. Pagine 2, 3, 4

Figura pagina 269 processo damascene "Overview of the Use of Copper Interconnects in the Semiconductor Industry" Annabelle Pratt, Ph.D., Advanced Energy Industries, Inc. Pagina 5 Figura 4.25 crescita silicio stirato

https://depts.washington.edu/matseed/mse_resources/Webpage/Functional%20IC %20Processing/IC.htm

Figura 4.26 Laurea Triennale in Ingegneria Elettronica "Legge di Moore e Tecnologie Microelettroniche Future" Andrea Muraro pagina 29

Figura 4.28 File formato pdf Intel "Press45nm107_FINAL" pagina 12

Figura 4.30 destra "CMOS Power Consumption and Cpd Calculation" Texas Instruments pagina 6

Figura 4.30 sinistra "Towards a Thermal Moore’s Law" Purdue University pagina 21 Figura 4.31 sinistra "Towards a Thermal Moore’s Law" Purdue University pagina 25 Figura 4.31 destra "Towards a Thermal Moore’s Law" Purdue University pagina 23

Figura 4.32 "ASSESSING TRENDS IN THE ELECTRICAL EFFICIENCY OF COMPUTATION OVER TIME" Jonathan G. Koomey pagina 4

Figure pagina 278 brevetto US3115581 Jack Kilby Figura 4.33 brevetto US3356858 Frank Wanlass

Figura 4.34: Brevetto per la tecnologia delle memorie a semiconduttore DRAM US3387286 Robert Dennard

Figura pagina 280 prof. Kanti Jain https://ece.illinois.edu/newsroom/article/1095 Figura 4.35 https://www.researchgate.net/figure/237011279_fig4_Fig-55-Basic-photolithography-and-pattern-transfer-Example-uses-an-oxidized-Si-wafer

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http://dionisio.centropiaggio.unipi.it/gvozzi/Shared%20Documents/Micro%20e%20Nano %20Sistemi/Tecnologie%202D/Lithography.pdf

Figura 4.36 Moore’s Law Coming to an End

http://www.personal.psu.edu/lxb5198/Assign_6.html

Figura 4.37 sinistra Tesi di Laurea Triennale "Dissipazione di Potenza nei Circuiti CMOS: Origini e Tecniche per la Riduzione"Giovanni Bruni pagina 48

Figura 4.37 destra disegno struttura FinFET elaborato da presentazione http://slideplayer.com/slide/4735685/#.Wh9Cizj8TK8.google_plusone_share

Figura 4.38 Presentazione Intel Advancing Moores law in 2014 pagina 25

Figura pagina 284 (sinistra) Presentazione Intel Advancing Moores law in 2014 pagina 22

Figura pagina 284 (destra) Tesi di Laurea Triennale "Dissipazione di Potenza nei Circuiti CMOS: Origini e Tecniche per la Riduzione"Giovanni Bruni pagina 49

Figura 4.39 Tabella proprietà semiconduttori Germanio, Si(1-x)Ge(x), Silicio The General Properties of Si, Ge, SiGe, SiO2

and Si

3

N

4 June 2002 Virginia Semiconductor pagina 2 Figura 4.40 Low k dielectrics Prof. Krishna Saraswat Department of Electrical Engineering Stanford University pagina 9

Figura 4.41 Interlayer Dielectrics for Semiconductor Technologies pagine 333, 334

Figura 4.42 Tesi laurea "Grafene: Proprietà, Sintesi e Applicazioni" Dimitri Reali pagina 9

Figura 4.43 http://www.uniroma2.it/didattica/Chimica-Medica/deposito/chimica_organica_01.pdf

Figura 4.45 Presentazione http://slideplayer.it/slide/584270/ LM Fisica A.A 2013/2014 F. De Matteis

Figura 4.47 "Il grafene: proprietà, tecniche di preparazione ed applicazioni" Girolamo Di Francia, Ettore Massera, Mara Miglietta, Ivana Nasti, Tiziana Polichetti ENEA

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pagina 30

Figura 4.50 "Performance of arsenene and antimonene double-gate MOSFETs from first principles" Nature Communications

Tabella pagina 299, estratto da "Performance of arsenene and antimonene double-gate MOSFETs from first principles" Nature Communications

Figura 4.51 2015 ITRS 2.0 Beyond CMOS pagina 31

Figura 4.52 http://chimicapratica.altervista.org/index_htm_files/F19%20-%20Semiconduttori.pdf pagina 7

Figura 4.53 sinistra "Appunti di nanoelettronica" Prof. Massimo Macucci dipartimento ingegneria dell'informazione università di Pisa pagina 2

Figura 4.53 destra

https://commons.wikimedia.org/wiki/File:ScanningTunnelingMicroscope_schematic.png Figura 4.54 sinistra "Challenges of 22 nm and beyond CMOS technology" pagina 23

Figura 4.54 destra Tesi di Laurea Magistrale "Studio della variabilità atomistica nei dispositivi nanowire tramite simulazioni 3D" Luca MASCETTI pagina 23

Figura 4.55, 4.56 http://www.edgefxkits.com/blog/tunneling-feld-efect-transistor-tfet-working-applications/

Figura 4.57 http://www.material.tohoku.ac.jp/~kotaib/e_study_detail_spin.html Figura 4.58 A spin metal–oxide–semiconductor field-effect transistor using half-metallic-ferromagnet contacts for the source and drain - APPLIED PHYSICS LETTERS VOLUME 84, NUMBER 13 29 MARCH 2004

Figura 4.59 https://www.researchgate.net/fgure/271537393_fg2_Figure-2-Working-principle-of-a-negative-capacitance-feld-efect-transistor-NC-FET

"A Tutorial Introduction to Negative Capacitor Field Effect Transistors: Perspective on The Road Ahead" Muhammad A. Alam

Figura 4.60 "Nanoelectromechanical Switches for Low-Power Digital Computing" Alexis Peschot pagina 4

Figura 4.61 "Pathway to the PiezoElectronic Transduction Logic Device" P.M. Solomon

Capitolo 5:

Figura 5.1 http://sanfranciscoitaly.com/post/57450671249/dr-federico-faggin-looks-beyond-microprocessing http://www.intel4004.com/images/iedm_covart.jpg

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Figura 5.2 "PARAMETRI ELASTICI E TERMOFISICI DEL SILICIO CRISTALLINO" A. Marini Figura 5.3 http://www.intel4004.com/btstrp.htm Figura 5.4 http://www.intel4004.com/buried.htm Figura 5.5 https://www.quora.com/If-there-had-been-an-Apollo-style-project-in-the-1960s-with-the-sole-goal-of-developing-a-modern-video-game-roughly-how-much-would-it-have-cost Figura 5.6 https://it.wikipedia.org/wiki/Silicio_policristallino

Figura 5.7 Federico Faggin and Thomas Klein.: "A Faster Generation Of MOS Devices With Low Thresholds Is Riding The Crest Of The New Wave, Silicon-Gate IC’s". "Electronics" magazine, September 29, 1969

Figura 5.8 http://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/

Figura 5.9 http://www.intel4004.com/images/elect_pg2_pg3.jpg Figura 5.10 http://www.intel4004.com/images/elect_pg4_pg5.jpg

Figura 5.11 sinistra http://www.i-programmer.info/history/machines/3345-birth-of-the-intel-4004-the-first-microprocessor.html

Figura 5.11 destra http://www.4004.com/

Figura 5.12 http://www.i-programmer.info/history/machines/3345-birth-of-the-intel-4004-the-first-microprocessor.html

Figura 5.13, 5.14, 5.15, 5.16 "The making of first microprocessor", Dr. F. Faggin, IEEE SOLID-STATE CIRCUITS MAGAZINE 2009

Figura fondo pagina 329 datasheet Intel MCS 4 dicembre 1971 Figura calcolatore PDP 11 https://en.wikipedia.org/wiki/PDP-11 Figura pagina 332 datasheet Intel 4003, 4004

Figura 5.17 "The making of first microprocessor", Dr. F. Faggin, IEEE SOLID-STATE CIRCUITS MAGAZINE 2009 pagina 17

Figura 5.18 https://en.wikipedia.org/wiki/Rubylith

Figura 5.19 Pagina iniziale del datasheet Intel del sistema MCS-4 in tecnologia pMOS silicon gate da 10 µm.

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Figura 5.20 Schema delle interconnessioni tra i vari circuiti integrati del sistema completo MCS-4.

Figura pagina 336, 337 datasheet Intel pagina 5 Figura pagina 338 datasheet Intel pagina 7 Figura pagina 339 datasheet Intel pagina 10 Figura 5.21 datasheet Intel 4040 pagina 1

Figura 5.22 Intel MCS-40 Users Manual Nov 74 pagina 21 Figura 5.23 pinout Intel 4040 da datasheet

Figura 5.24 nuove istruzioni Intel 4040 da datasheet Figura 5.25 istruzioni I/O Intel 4040 da datasheet

Figura 5.26 istruzioni di accumulatore Intel 4040 da datasheet Figura 5.27 formato istruzioni Intel 4040 da datasheet

Figura 5.28 http://canoro.altervista.org/cpu/companies/intel/4040.php Capitolo 6: Figura 6.1 http://www.bytecollector.com/mark_8.htm Figura 6.2 http://www.old-computers.com/Museum/computer.asp?c=346 Figura 6.3 http://www.old-computers.com/museum/computer.asp?c=523 Figura 6.4 http://www.old-computers.com/museum/computer.asp?c=352 Figura 6.5 http://www.robotrontechnik.de/index.htm?/html/computer/pbt4000.htm Figura 6.6 http://www.scelbi.com/

Figura 6.7 sinistra Intel 8008usersManualRev2_Nov72 pagina 5

Figura 6.7 destra http://www.righto.com/2017/02/reverse-engineering-surprisingly.html Figura pagina 354 schema a blocchi e pinout Intel 8008 da datasheet pagina 3

Figura 6.8 Intel 8008 datasheet pagina 7 Figura 6.9 Intel 8008 datasheet pagina 9

Figura 6.10 https://geektimes.ru/company/intel/blog/289417/ Figura 6.11, 6.12 Intel 8008 datasheet pagina 11

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Figura 6.13 Intel 8008 datasheet pagina 13 Figura 6.14 Intel 8008 datasheet pagina 15

Figura pagina 361 Intel 8080 https://www.cpucollection.ca/Intel8080.htm Figura 6.15 Pinout Intel 8080 datasheet pagina 3

Figura 6.16 http://www.cpu-world.com/CPUs/8080/MANUF-AMD.html Figure fondo pagina 363 varie cpu 8080 prodotte da terzi www.cpu-world.com Figura 6.17 Intel 8080 datasheet pagina 1 e 2

Figura 6.18 Pinout Intel 8080 datasheet pagina 3

Figura pagina 366 Altair MITS 8800 https://it.wikipedia.org/wiki/MITS_Altair_8800 Figura pagina 366 cpu Intel 8085 https://en.wikipedia.org/wiki/Intel_8085 Figura pagina 368 cpu Intel 8085 clone sovietico www.cpu-world.com

Figura 6.19 https://en.wikipedia.org/wiki/Intel_8085 Figura 6.20 Intel 8085A datasheet pagina 1 e 2

Figura pagina 370 Intel MCS8085 Users Manual pagina 28 Figura 6.21 datasheets Intel 8224 ed 8228

Figura 6.22 Intel MCS8085 Users Manual pagina 18 e 19 Figura 6.23 sinistra http://www.cpushack.com/tag/alu/

Figura 6.23 destra http://www.cpushack.com/2010/09/23/arithmetic-processors-then-and-now/ Figura 6.24 https://es.wikipedia.org/wiki/Intel_8237

Figura 6.25 datasheet Intel 8237A Figura 6.26 datasheet Intel 82C55A

Figura pagina 378 modi operativi circuito integrato Intel 82C55A

Capitolo 7:

Figura 7.1 http://visual6502.org/images/pages/Intel_8086_die_shots.html Figura 7.2 datasheet Intel 8086 231455-005

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Figura 7.3 Intel 8086 family Users Manual pagina 16 Figura 7.4, 7.5 datasheet Intel 8086 231455-005

Figura 7.6 http://www.robertagerboni.it/2012-2013/mat_3/SI-Architettura%20interna%20del %20processore%20Intel%208086.pdf

Figura 7.7 datasheet Intel 8086 231455-005 pagina 8 Figura pagina 387 datasheet Intel 8086 231455-005 pagina 7 Figura pagina 388 datasheet Intel 8086 231455-005 pagina 6 Figura 7.8 datasheet Intel 8086 231455-005 pagina 12

Figura pagina 389 Gestione segmentata della memoria centrale https://en.wikipedia.org/wiki/Intel_8086

Figura 7.9 datasheet Intl iAPX 88 pagina 5

Figura pagina 389 Cloni hardware dell’Intel® 8086 https://en.wikipedia.org/wiki/K1810VM86 https://en.wikipedia.org/wiki/Intel_8086

Figura 7.10 Intel 8089 ASSEMBLER USER'S GUIDE 9800938-01

Figura 7.11 Intel 8089 ASSEMBLER USER'S GUIDE 9800938-01 pagina 10 Figura 7.12 Intel 8089 ASSEMBLER USER'S GUIDE 9800938-01 pagina 11 Figura 7.13 Intel 8089 ASSEMBLER USER'S GUIDE 9800938-01 pagina 15

Figura pagina 397 Insieme registri Intel 8089 Intel 8089 ASSEMBLER USER'S GUIDE 9800938-01 pagina 22

Figura pagina 398 Intel 8089 ASSEMBLER USER'S GUIDE 9800938-01 pagina 25, 18 Figura pagina 399 Datasheet Intel 8259A 231468-003

Figura pagina 400 Datasheet Intel 8259A 231468-004 Figura 7.14 Datasheet Intel 8259A pagina 1

Figura 7.15 Datasheet Intel 8259A pagina 2

Figura pagina 404 Immagini sulle interruzioni tratte da un file dell'Istituto Marconi http://www.itimarconi.ct.it/sezioni/didatticaonline/informatica/

Figura 7.16 destra http://www.brokenthorn.com/Resources/OSDevPic.html Figura 7.16 sinistra Immagine tratta da un file dell'Istituto Marconi

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Figura pagina 406 Datasheet Intel 8259A pagina 19

Figura 7.17, tabella 7.1, figura 7.18 datasheet Intel 8086 231455 pagine 26-30 Figura 7.19 http://www.cpu-world.com/CPUs/8088/index.html

Figura 7.20 Schema a blocchi 8088 da datasheet Intel iAPX 88 Immagini varianti 8088 pagine 411 e 412 da www-cpu-world.com

Capitolo 8:

Figura 8.1 Datasheet Intel 80186/80188 272430

Figure 8.2, 8.3 Datasheet Intel 80186/80188 272430

Figura 8.4 https://cpumuseum.jimdo.com/cpu-die-photography/8086-80286/

Figura 8.5 http://canoro.altervista.org/cpu/companies/intel/80186.php

Figura pagina 419 Datasheet Intel 80188

Figura 8.6 https://cpumuseum.jimdo.com/cpu-die-photography/8086-80286/ Figura pagina 421 Datasheet Intel 80188 pagina 11

Figura 8.7 Datasheet Intel 80188 pagina 6

Figura pagina 423 1990_80186_80188_80C186_80C188_Hardware_Reference_Manual pagina 22

Figura 8.8 destra Intel datasheet 80C187 pagina 2

Figura 8.8 sinistra immagine tratta da sito web www.cpu-info.com Capitolo 9:

Figura 9.1 Scheda Intel iSBC 432/100 http://www.intel-vintage.info/intelsystems.htm#879136159

http://www.cpu-world.com/forum/viewtopic.php?t=25173 http://www.datormuseum.se/computers/others/intel-iapx432

Figura 9.2 Capability Based Computer Systems, Henry M. Levy capitolo 9 pagina 2 Figura 9.3 Capability Based Computer Systems, Henry M. Levy capitolo 9 pagine 3,4 Figura 9.4 Capability Based Computer Systems, Henry M. Levy capitolo 9 pagine 5,6

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Figura 9.5 Capability Based Computer Systems, Henry M. Levy capitolo 9 pagine 24,25 Figura 9.6 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 1 Figura 9.7 https://en.wikipedia.org/wiki/Depletion-load_NMOS_logic

Figura 9.8 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 5 Figura 9.9 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 19 Figura 9.10 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 20 Figura 9.11 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 21 Figura 9.12 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 22 Figura 9.13 iAPX 43201 , iAPX_43202 VLSI General Data Processor Feb81 pagina 23

Capitolo 10:

Fotografia pagina 447 https://commons.wikimedia.org/wiki/File:Intel_80860XR_die2.JPG Figura 10.1 http://www.geekdot.com/hardware/intel-80860/

Figura 10.2 Intel 240330-002_i860_64-Bit_Microprocessor_Hardware_Reference_Dec89 pagina 34

Fotografia pagina 452 http://www.geekdot.com/hauppauge-4860/ Figura 10.3 http://ummr.altervista.org/i860.htm

Figura pagina 456 pipeline cinque stadi, slide numero 13 http://slideplayer.com/slide/8785530/

Figure schede madri Intel 80860 pagina 459 http://ummr.altervista.org/i860.htm Figure schede madri Intel 80860 pagina 460 http://ummr.altervista.org/i860.htm

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Figure schede madri Intel 80860 pagina 461 http://ummr.altervista.org/i860.htm Figura 10.8 https://en.wikipedia.org/wiki/Intel_i960

Figura 10.9 https://people.cs.clemson.edu/~mark/330/chronques.html Figura 10.10 Datasheet Intel i960 Processor Linecards

Capitolo 11:

Figura 11.1 http://fadace.developpez.com/cpu/

Figura 11.2 210760-002_80286_Hardware_Reference_Manual_1987 pagina 52 Figura 11.3 sinistra http://canoro.altervista.org/cpu/companies/intel/80286.php

Figura 11.3 destra 210760-002_80286_Hardware_Reference_Manual_1987 pagina 126

Figura 11.4 "THE INTEL MICROPROCESSORS" BARRY B. BREY, Prentice Hall pagina 671 Figura 11.5 210498-001_iAPX_286_Programmers_Reference_1983 pagina 94

Figura 11.6 210760-002_80286_Hardware_Reference_Manual_1987 pagina 42

Figura 11.7 210498-005_80286_and_80287_Programmers_Reference_Manual_1987 pagina 41 Figura 11.8 210498-005_80286_and_80287_Programmers_Reference_Manual_1987 pagina 33 Figura 11.9 "THE INTEL MICROPROCESSORS" BARRY B. BREY, Prentice Hall pagina 673 Figura 11.10 Datasheet 80286_Nov85 03552C pagina 14

Figura 11.11 destra 210498-005_80286_and_80287_Programmers_Reference_Manual_1983 pagina 99

Figura 11.11 sinistra 210498-005_80286_and_80287_Programmers_Reference_Manual_1983 pagina 104

Figura 11.12 210498-005_80286_and_80287_Programmers_Reference_Manual_1983 pagina 106 Figura 11.13 210498-005_80286_and_80287_Programmers_Reference_Manual_1983 pagina 102 Figura 11.14 210498-005_80286_and_80287_Programmers_Reference_Manual_1983 pagina 105 Figura 11.15 destra 210498-005_80286_and_80287_Programmers_Reference_Manual_1983 pagina 120

Figura 11.15 sinistra 210498-001_iAPX_286_Programmers_Reference_1983 pagina 13 Figura 11.16 210498-001_iAPX_286_Programmers_Reference_1983 pagina 128

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Figura 11.17 http://www.ateneonline.it/bucci/Approfondimenti_12_protezione_.pdf pagina 18 Figura 11.18 210498-001_iAPX_286_Programmers_Reference_1983 pagina 137

Figura 11.19 210498-001_iAPX_286_Programmers_Reference_1983 pagina 138 Figura 11.20 210498-001_iAPX_286_Programmers_Reference_1983 pagina 143

Figura 11.21 sinistra 210498-001_iAPX_286_Programmers_Reference_1983 pagina 167 Figura 11.21 destra Datasheet 80286_Nov85 03552C pagina 7

Figura 11.22 210498-001_iAPX_286_Programmers_Reference_1983 pagina 148 Tabella 11.2 210498-001_iAPX_286_Programmers_Reference_1983 pagina 156

Capitolo 12:

Figura 12.1 http://ummr.altervista.org/x86gen.htm Figura 12.2 Datasheet Intel 80386DX 231630

Figura 12.3 Coping with the Complexity of Microprocessor Design at Intel – A CAD History Patrick Gelsinger pagina 4

Figura 12.4 http://xhoba.x86-guide.com/en/collection/Intel-386DX-33-cpu-no5375.html Figura 12.5 destra http://canoro.altervista.org/cpu/companies/intel/80386.php

Figura 12.5 sinistra http://www.cpushack.com/tag/military/

Figura 12.6 http://www.cpu-world.com/Memorabilia/80486/Promotion_kit/index.html Figura 12.7 Datasheet Intel 80386EX 272420

Figura 12.8 http://ummr.altervista.org/x86gen3.htm

Figura 12.9 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 pagina 132 Figura 12.10 231732-001_80386_Hardware_Reference_Manual_1986 pagina 28

Figura 12.11 231746-001_Introduction_to_the_80386_Apr86 pagina 33 Figura 12.12 231746-001_Introduction_to_the_80386_Apr86 pagina 53

Figura 12.13 sinistra 231732-001_80386_Hardware_Reference_Manual_1986 pagina 59 Figura 12.13 destra 231732-001_80386_Hardware_Reference_Manual_1986 pagina 68 Figura 12.14 sinistra 240852-002 386SL Technical Overview 1991 pagina 14

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Figura 12.14 destra Intel datasheet 80386SL pagina 2 Figura 12.15 Datasheet Intel 8254

Figura 12.16 sinistra 290143-001 82385 32 Bit Cache Controller Advance Information Jul87 pagina 1

Figura 12.16 centro https://cpumuseum.jimdo.com/museum/architectures/support-chips/ Figura 12.16 destra https://commons.wikimedia.org/wiki/File:Intel_82385_die.JPG

Figura 12.17 290143-001 82385 32-Bit Cache Controller Advance Information Jul87 pagina 7 Figura 12.18 sinistra 290143-001 82385 32-Bit Cache Controller Advance Information Jul87 pagina 12

Figura 12.18 destra http://download.intel.com/design/intarch/papers/cache6.pdf pagina 7 Figura 12.19 sinistra 290143-001 82385 32-Bit Cache Controller Advance Information Jul87 pagina 14

Figura 12.19 destra http://download.intel.com/design/intarch/papers/cache6.pdf pagina 7 Figura 12.20 290143-001 82385 32-Bit Cache Controller Advance Information Jul87 pagina 8 Figura 12.21 231746-001_Introduction_to_the_80386_Apr86 pagina 54

Figura 12.22 231746-001_Introduction_to_the_80386_Apr86 pagina 14 Figura 12.23 231746-001_Introduction_to_the_80386_Apr86 pagina 15 Figura 12.24 231746-001_Introduction_to_the_80386_Apr86 pagina 41 Figura 12.25 http://www.byclb.com/TR/Tutorials/microprocessors/ch2_1.htm

Figura 12.26 Using CPU System Management Mode to Circumvent Operating System Security Functions pagina 3

Figura 12.27 Intel 386SL microprocessor superset databook 240814 pagina 17

Capitolo 13:

Figura 13.1 http://diephotos.blogspot.it/

Il Coprocessore Matematico Intel 8087Fernando Bianchi Figura pagina 526 https://en.wikipedia.org/wiki/Intel_8087 Figura pagina 526 www.cpu-world.com

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Figura pagina 526 Datasheet Intel 8087 Figura 13.2 Datasheet Intel 8087 pagina 4 Figura 13.3

http://www.tutorialspoint.com/microprocessor/microprocessor_8087_numeric_data_processor.htm Figura 13.4 Datasheet Intel 8087 pagina 2

Figura 13.5 http://www.grix.it/UserFiles/febia001/File/FPU_8087.pdf Figura 13.6 Datasheet Intel 8087 pagina 9

Figura pagina 530 Datasheet Intel 8087 pagina 9 Figura pagina 530 Datasheet Intel 8087 pagina 10 Figura pagina 531 Datasheet Intel 8087 pagina 11 Figura 13.7 Datasheet Intel 8087 pagina 5

Figure pagine 541, 542 https://it.wikipedia.org/wiki/IEEE_754

Figura 13.8 Handbook of Floating-Point Arithmetic (Jean-Michel Muller, et al) 081764704X pagina 80

Figura pagina 543 https://en.wikipedia.org/wiki/IEEE_754

Figura 13.9 Handbook of Floating-Point Arithmetic (Jean-Michel Muller, et al) 081764704X pagina 41

Figura pagina 544 Handbook of Floating-Point Arithmetic (Jean-Michel Muller, et al) 081764704X pagina 44

Figura pagina 546 Handbook of Floating-Point Arithmetic (Jean-Michel Muller, et al) 081764704X pagina 85

Figure pagina 547 Handbook of Floating-Point Arithmetic (Jean-Michel Muller, et al) 081764704X pagina 100, 101, 103

Figure pagina 548 Handbook of Floating-Point Arithmetic (Jean-Michel Muller, et al) 081764704X pagina 104, 112

Figura 13.10 sinistra THE INTEL MICROPROCESSORS BARRY B. BREY pagina 537 Figura 13.10 destra Intel 80287 datasheet Feb83 pagina 1

Figura 13.11 sinistra https://it.wikipedia.org/wiki/Intel_80287 Figura 13.11 destra http://www.wikiwand.com/en/X87

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Figura 13.12 www.cpu-world.com Figura 13.13 Datasheet Intel 287XL/XLT

Immagine nota 26 pagina 550 www.cpu-world.com

Figura 13.14 sinistra Intel 80287 datasheet Feb83 pagina 3 Figura 13.14 destra Intel 80287 datasheet Feb83 pagina 6 Figura pagina 553 Intel 80287 datasheet Feb83 pagine 2, 3 Figura 13.15 Intel 80287 datasheet Feb83 pagina 10

Figura 13.16 Intel 80287 datasheet Feb83 pagina 13 Figura 13.17 Intel 80287 datasheet Feb83 pagina 12

Figura 13.18 210498-005 80286 and 80287 Programmers Reference Manual 1987 pagine 449, 450 Figura 13.19 sinistra https://www.timetoast.com/timelines/generaciones-de-procesadores Figura 13.19 destra http://www.cpu-galaxy.at/cpu/intel%20cpu/coprozessor/intel

%208087%20section.htm

Figura 13.20 Datasheet Intel 80387DX

Figura 13.21 https://en.wikipedia.org/wiki/X87

Figura 13.22 Intel 80387DX datasheet 240448 pagina 5 Figura 13.23 Intel 80387DX datasheet 240448 pagine 9 ed 8 Figura 13.24 Intel 80387DX datasheet 240448 pagine 10, 11

Figura 13.25 https://www.roma1.infn.it/workshop/2006/apenext/Cabibbo_ApeNext.pdf Figure 13.26, 13.27 www.cpu-world.com

Figura 13.28 sinistra http://www.cpu-museo.it/weitek/4167.html Figura 13.28 destra Datasheet Weitek 4167 aprile 89 pagina 8 Figura 13.29 Datasheet Weitek 4167 aprile 89 pagina 10 Figura 13.30 Datasheet Weitek 4167 aprile 89 pagina 11

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Figura 13.32 Datasheet Weitek 3167 pagina 4 Figura 13.33 Datasheet Weitek 3167 pagine 31, 32 Figura 13.34 Datasheet Weitek 3167 pagina 23 Figura 13.35 Datasheet Weitek 3167 pagine 23, 24

Figura 13.36 http://www.cpu-world.com/forum/viewtopic.php?t=25638 schema a blocchi 1167

Capitolo 14:

Figura 14.1 Coping with the Complexity of Microprocessor Design at Intel – A CAD History Patrick Gelsinger pagina 7

Figura 14.2 241731-002_Intel486_Microprocessors_and_Related_Products_Jan95 pagina 63 Figura 14.3 Datasheet 240440-006_486DX pagina 23

Figura 14.4 The i486 CPU: Executing Instructions in One Clock Cycle John H . Crawford pagina 27

Figura 14.5 Clocking In Microprocessors Lecture2005-final Ian Young pagina 19 Figure pagina 577 "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27, NO. I I , NOVEMBER 1992 pagina 3

Figura pagina 578 Filtro di anello "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27, NO. I I ,

NOVEMBER 1992 pagina 3

Figura 14.7 Datasheet 240440-006_486DX pagina 8 Figura 14.8 Datasheet 240440-006_486DX pagina 12

Figura 14.9 The i486 CPU: Executing Instructions in One Clock Cycle John H . Crawford pagina 32

Figura 14.10 THE INTEL MICROPROCESSORS BARRY B. BREY pagina 722

Figura 14.11 241731-002_Intel486_Microprocessors_and_Related_Products_Jan95 pagina 857 controllore 82489DX

Figura 14.12 http://ummr.altervista.org/x86gen3.htm

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Figura 14.14 http://canoro.altervista.org/cpu/companies/intel/80486.php

Figura 14.6 sinistra "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27, NO. I I , NOVEMBER 1992 pagina 1

Figura 14.6 destra "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27, NO. I I , NOVEMBER 1992 pagina 2

Figura 14.15 https://cpumuseum.jimdo.com/cpu-die-photography/80486-5x86/ Figura 14.16 https://hu.wikipedia.org/wiki/Intel_80486_OverDrive

Capitolo 15:

Figura 15.1 Intel Reveals Pentium Implementation Details Vol. 7, No. 4, March 29, 1993 Microprocessor Report pagina 2

Figura 15.2 1993_Intel_Pentium_Processor_Users_Manual_Volume_1 241430 pagina 6

Figura 15.3 http://in.ncu.edu.tw/~ncume_ee/digilogi/uconn-ee215/fall2001/215ln09.pdf pagina 3 "BiCMOS Logic Gates" University of Connecticut

Figura 15.6 Registro EFLAGS da datasheet Intel Pentium http://mcs.uwsuper.edu/sb/224/Intro/flags.html

Figura 15.9 The microarchitecture of Intel, AMD and VIA CPUs An optimization guide for assembly programmers and compiler makers - Agner Fog. Technical University of Denmark pagina 11

Figura 15.10 The microarchitecture of Intel, AMD and VIA CPUs An optimization guide for assembly programmers and compiler makers - Agner Fog. Technical University of Denmark pagina 12

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Figura 15.11 Tesi di laurea Triennale in Ingegneria Elettronica "STUDIO SUGLI ALGORITMI PER BLOCCHI CIRCUITALI ARITMETICI E DIVISORI " Luca Boscolo Galazzo pagina 12 Figura 15.12 Stuart Franklin Oberman DESIGN ISSUES IN HIGH PERFORMANCE FLOATING POINT ARITHMETIC UNITS pagina 60

Figura 15.13 sinistra THE INTEL MICROPROCESSORS BARRY B. BREY pagina 730 Figura 15.13 destra 1993_Intel_Pentium_Processor_Users_Manual_Volume_1 241430 pagina 18

Figura 15.14 https://en.wikipedia.org/wiki/P5_(microarchitecture)#P5 Figura 15.15 https://en.wikipedia.org/wiki/P5_(microarchitecture)#P5

Figura 15.16 Modulo Tillamook http://www.ce.unipr.it/~stocchi/PII/dati/21.htm Figura 15.17 sinistra https://en.wikipedia.org/wiki/Pentium_FDIV_bug

Figura 15.17 destra Prof. Thomas Nicely http://www.trnicely.net/#PENT "Divide and Conquer " pagina 3

Figura 15.18 https://www.cs.earlham.edu/~dusko/cs63/fdiv.html Figura 15.19 Datasheet Intel Pentium MMX 243185 pagina 1

Figura 15.20 THE INTEL MICROPROCESSORS BARRY B. BREY pagina 570

Capitolo 16:

Figura 16.1 Intel’s P6 Uses Decoupled Superscalar Design Microprocessor Report Vol. 9, No. 2, February 16, 1995 pagina 6

Figura 16.2 https://www.researchgate.net/figure/51991666_fig1_Figure-1-ASCI-Red-at-Sandia-National-Laboratories

Figura 16.3 http://www.x86-guide.com/en/cpu/Intel-Pentium%20Pro-2.html Figura 16.4 MindShare Pentium Pro and Pentium II System Architecture pagina 68 Figura 16.5 https://it.wikipedia.org/wiki/Pentium_Pro

Figura 16.6 Datasheets Intel Pentium Pro 242769-003, 243570-001

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February 16, 1995 pagina 5

Figura 16.8 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 34 Figura 16.9 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 33 Figura 16.10 MindShare Pentium Pro and Pentium II System Architecture pagina 236

Figura 16.11 MindShare Pentium Pro and Pentium II System Architecture pagina 234 Figura 16.12 MindShare Pentium Pro and Pentium II System Architecture pagina 238

Figura 16.13 sinistra 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 35

Figura 16.13 destra MindShare Pentium Pro and Pentium II System Architecture pagina 127 Figura 16.14 sinistra 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 37

Figura 16.14 destra 242691-001_Pentium_Pro_Family_Developers_Manual_Volume_2_Jan96 pagina 39

Figura 16.15 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 38 Figura 16.16 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 39 Figura 16.17 THE INTEL MICROPROCESSORS BARRY B. BREY pagina 775

Figura 16.18 242692-01 Pentium Pro Family Developers Manual Volume 3 Jan96 pagina 76 Figura 16.19 242692-01 Pentium Pro Family Developers Manual Volume 3 Jan96 pagina 77 Figura 16.20 242691-001_Pentium_Pro_Family_Developers_Manual_Volume_2_Jan96 pagina 48 Figura 16.21 242692-01 Pentium Pro Family Developers Manual Volume 3 Jan96 pagina 86, 87 Figura pagina 634 specifiche tensioni

242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 201

Figura 16.22 sinistra 242690-001_Pentium_Pro_Family_Developers_Manual_Volume_1_Jan96 pagina 263

Figura 16.22 destra THE INTEL MICROPROCESSORS BARRY B. BREY pagina 747 Figura 16.23 MindShare Pentium Pro and Pentium II System Architecture pagina 526 Figura 16.24 MindShare Pentium Pro and Pentium II System Architecture pagina 558

Figura 16.25 sinistra MindShare Pentium Pro and Pentium II System Architecture pagina 566

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Figura 16.25 destra Datasheet Intel® 440FX PCIset pagina 1

Figure pagina 637 Datasheet Intel® 440FX PCIsetmemcontr pagine 2 e 3 Figura 16.26 https://howlingpixel.com/wiki/Pentium_OverDrive

Figura 16.27 Pentium II Debuts at 300 Mhz Linley Gwennap Microprocessor Report VOLUME 11, NUMBER 6 1997 pagina 4

Figura 16.28 https://it.wikipedia.org/wiki/Slot_1

Figura 16.29 "Klamath Extends P6 Family" Microprocessor Report Volume 11, Numero 2 Febbraio 1997 pagina 2

Figura 16.30 Datasheet Intel Pentium II 24333503

Figura 16.31 Intel 266MHz 32-Bit Pentium II (Klamath) Processor Report Number: SCA 9706-542 ICE pagina 63

Figura 16.32 Datasheet Intel Pentium II 243657002 Figura 16.33 www.cpu-world.com

Immagini pagina 643 Pentium II mobile https://en.wikipedia.org/wiki/Pentium_II http://arch.pconline.com.cn/notebook/guide/unified/0506/641632_2.html

Immagine nucleo Covington pagina 644 http://www.wikiwand.com/en/Celeron

Figura 16.34 Mendocino Improves Celeron Microprocessor Report Volume 12, Numero 11 Agosto 1998 pagina 3

Figura 16.35 MindShare Pentium Pro and Pentium II System Architecture pagina 428 Figura 16.36

https://www.intel.com/content/www/us/en/support/articles/000005670/processors.html Figura 16.37 "Intel’s 0.25 Micron, 2.0 Volts Logic Process Technology" A. Brand, A. Haranahalli, N. Hsieh, Y.C. Lin, G. Sery, N. Stenton, B.J. Woo California Technology and Manufacturing Group, Intel Corp. Pagina 2

Figura 16.38 "Intel’s 0.25 Micron, 2.0 Volts Logic Process Technology" A. Brand, A. Haranahalli, N. Hsieh, Y.C. Lin, G. Sery, N. Stenton, B.J. Woo California Technology and Manufacturing Group, Intel Corp. Pagina 5

Figura 16.39 Pentium III = Pentium II + SSE Microprocessor Report Volume 13, Numero 3 Marzo 1999 pagina 7

Figura 16.40 http://www.wikiwand.com/en/Pentium_III Figura 16.41 http://www.chipsetc.com/intel-paperweights.html

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https://ru.wikipedia.org/wiki/%D0%A4%D0%B0%D0%B9%D0%BB:Coppermine-t.jpg

Figura 16.43 https://howlingpixel.com/wiki/Pentium_III

Figura 16.44 Intel® Architecture Optimization Reference Manual 245127-001 pagina 26 Figura 16.45 Intel® Architecture Optimization Reference Manual 245127-001 pagina 34 Figura 16.46 IMPLEMENTING STREAMING SIMD EXTENSIONS ON THE PENTIUM III PROCESSOR Srinivas K. Raman IEEE 2000 pagina 2

Figura 16.47 Pentium III = Pentium II + SSE Microprocessor Report Volume 13, Numero 3 Marzo 1999 pagina 3

Figura 16.48 Pentium® III Processor Implementation Tradeoffs Jagannath Keshava pagina 5 Figura 16.49 Intel® Architecture Optimization Reference Manual 245127-001 pagina 38 Figura 16.50 http://www.cpu-world.com/CPUs/Pentium-III/index.html

Figura 16.51 destra http://www.cpu-world.com/CPUs/Pentium-III/index.html Figura 16.51 sinistra Datasheet Intel Pentium III mobile 298340-002 pagina 11

Capitolo 17:

Figura 17.1 "A 0.18-m CMOS IA-32 Processor With a 4-GHz Integer Execution Unit" IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001 pagina 3 Figura 17.2 https://it.wikipedia.org/wiki/NetBurst

Figura 17.3 "PENTIUM 4 (PARTIALLY) PREVIEWED Intel Lifts Veil on Hyperpipelined CPU —But Not All the Way" Microprocessor Report agosto 2000 Peter N. Glaskowsky pagina 1

Figura pagina 669

http://chip-architect.com/news/2003_04_20_Looking_at_Intels_Prescott_part2.html

Figura 17.4 http://chip-architect.com/news/2003_04_20_Looking_at_Intels_Prescott_part2.html Figura 17.5 http://pages.hmc.edu/harris/research/advanceddomino.pdf pagina 36

Figura pagina 672 pipeline Willamette e Northwood Pipeline in una macchina reale - Ing. Fabio Fassetti pagina 5

Figura 17.6 "A High Performance 180nm Generation Logic Technology" IEEE 1998 S. Yang pagina 1

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Figura 17.9 "A 130 nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 layers of Cu Interconnects" IEEE 2000 S. Tyagi pagina 4 Figura 17.10 "A 130 nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 layers of Cu Interconnects" IEEE 2000 S. Tyagi pagina 1 Figura 17.11 "A 130 nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 layers of Cu Interconnects" IEEE 2000 S. Tyagi pagina 2

Figura 17.12 sinistra https://commons.wikimedia.org/wiki/File:Intel_Pentium_4_2.80A-4014.jpg Figura 17.12 destra https://commons.wikimedia.org/wiki/File:Socket_775.png

Figura 17.13 https://www.anandtech.com/show/1621/3

Figura 17.14 Documento in formato pdf Intel Global-Intel-Manufacturing_FactSheet pagina 1 Figura 17.15 Prescott New Instructions Software Developer’s Guide pagina 6

Figura 17.16 A 90-nm Logic Technology Featuring Strained-Silicon IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004 pagina 1

Figura 17.17, 17.18 A 90-nm Logic Technology Featuring Strained-Silicon IEEE

TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004 pagina 3 Figura 17.19 A 90-nm Logic Technology Featuring Strained-Silicon IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004 pagina 5

Figura 17.20 A 90-nm Logic Technology Featuring Strained-Silicon IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004 pagina 5

Figura 17.21 Datasheet Intel 306382-003 pagina 9 Figura 17.22 https://www.anandtech.com/show/1621/3

Figura 17.23 https://www.tomshw.it/idf-intel-foto-presler-cedar-mill-7742 Figura 17.24 Datasheet Intel Pentium 4 sequenza 6x1 310308-002 pagina 8 Figura 17.25 https://isite.tw/2016/04/03/15360

Figura 17.26 Datasheet Intel Pentium 4 250686-007 pagina 89

Figura 17.27 https://pc.watch.impress.co.jp/docs/2005/0414/tawada47.htm

Figura 17.28 sinistra datasheet Intel Pentium D 307506-003 pagina 9 Figura 17.28 destra https://isite.tw/2016/01/31/14898

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Figura 17.29 sinistra https://isite.tw/2016/01/31/14898 Figura 17.29 destra https://en.wikipedia.org/wiki/Pentium_D

Capitolo 18:

Figura 18.2 Centrino microarchitecture and performance, Intel Technology journal maggio 2003 pagina 10

Figura 18.3 Branch Prediction Techniques and Optimizations Raj Parihar University of Rochester, NY, USA pagina 2

Figura 18.4 Branch Prediction Techniques and Optimizations Raj Parihar University of Rochester, NY, USA pagina 2

Figura 18.5 https://www.theregister.co.uk/2004/05/10/intel_dothan_launch/

Figura 18.6 Intel® 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 Mhz 252613-001 pagina 13

Figura 18.7 Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) 252615-005 pagine 16 e 18

Figura 18.8 https://en.wikipedia.org/wiki/Centrino

Intel Centrino Mobile Technology Performance Brief pagina 1 logo Centrino Figura 18.9 https://en.wikipedia.org/wiki/Centrino

Figura 18.10 http://www.hardwaresecrets.com/all-core-duo-and-core-solo-models/ Figura 18.11 https://en.wikipedia.org/wiki/Centrino

Capitolo 19:

Figura 19.1 sinistra https://it.wikipedia.org/wiki/File:Core_2_duo_logo_veecchio.jpg Figura 19.1 destra Datasheet Intel 313278-007 pagina 9

Figura 19.2, 19.3 "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain..." IEEE 2004 P. Bai pagina 2

Figura 19.4, 19.5 "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain..." IEEE 2004 P. Bai pagina 3

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Strain..." IEEE 2004 P. Bai pagina 4

Figura 19.7 sinistra Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler pagina 7

Figura 19.7 destra https://www.bit-tech.net/reviews/tech/cpus/intel_core_2_duo_processors/2/ Figura 19.8 sinistra Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler pagina 8

Figura 19.8 destra http://homepages.math.uic.edu/~jan/mcs572/mcs572notes/lec15.html Figura 19.9 Inside Intel® Core™ Microarchitecture and Smart Memory Access Jack Doweck pagina 7

Figura 19.10 Inside Intel® Core™ Microarchitecture and Smart Memory Access Jack Doweck pagina 9

Figura 19.11 Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler pagina 10

Figura 19.13 sinistra https://en.wikipedia.org/wiki/Pentium_Dual-Core Figura 19.13 Datasheet Intel 316981-005 pagina 7

Figura 19.14 https://phys.org/news/2007-07-intel-ships-first-ever-extreme-mobile.html Figura 19.15 Intel 64-ia-32 architectures software developer vol 1 manual pagina 289 Figura 19.16 https://www.pcmag.com/encyclopedia/term/51937/sse

http://www.yourdictionary.com/sse

Figura 19.17 sinistra https://en.wikipedia.org/wiki/Socket_M

Figura 19.17 destra https://commons.wikimedia.org/wiki/File:Socket_P_mPGA478MN-2406.jpg

Figura 19.18 http://www.hardwaresecrets.com/penryn-core-new-features/3/ Figura 19.19 Tesi Elaborato scritto EVOLUZIONE E STATO DELL’ARTE DEI MICROPROCESSORI INTEL - NICOLA FAVERO pagina 51

Figura 19.20 A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon...K. Mistry IEEE 2007 pagina 1

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Figura 19.23 https://it.wikipedia.org/wiki/Core_2_Extreme

Capitolo 20:

Figura 20.1 Datasheet Intel 320834-004 pagina 7

Figura 20.2 Documento Intel Nehalem Deep Dive SSG0203 pagina 4 Figura 20.3 sinistra https://it.wikipedia.org/wiki/Socket_B Figura 20.3 destra https://it.wikipedia.org/wiki/LGA_1156

Figura 20.4 https://pc.watch.impress.co.jp/docs/2008/0403/kaigai_nehaleml.gif

Figura 20.5 Simulation-driven verification Design Automation Summer School, 2009 Bob Bentley pagina 7

Figura 20.6 The microarchitecture of Intel, AMD and VIA CPUs, Agner Fog. Technical University of Denmark pagina 110

Figura 20.7 sinistra "An Introduction to the Intel® QuickPath Interconnect" Intel 2009 320412-001US pagina 8

Figura 20.7 destra "An Introduction to the Intel® QuickPath Interconnect" Intel 2009 320412-001US pagina 7

Figura 20.8 "An Introduction to the Intel® QuickPath Interconnect" Intel 2009 320412-001US pagina 9

Figura 20.12 "The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms" Michael E. Thomadakis, Ph.D. March, 17, 2011 pagina 31

Figura 20.13 https://www.anandtech.com/Show/Index/2594? cPage=3&all=False&sort=0&page=12&slug=

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https://www.anandtech.com/Show/Index/2594?cPage=3&all=False&sort=0&page=12&slug= Figura 20.15 https://archive.benchmarkreviews.com/index.php?

option=com_content&task=view&id=253&Itemid=63&limit=1&limitstart=2 Figura 20.16 https://www.anandtech.com/show/2658

Figura 20.17 "The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms" Michael E. Thomadakis, Ph.D. March, 17, 2011 pagina 32

Figura 20.18 sinistra http://www.hardwaresecrets.com/inside-intel-nehalem-microarchitecture/4/

Figura 20.18 destra https://www.anandtech.com/show/2594/4 Figura 20.19 https://www.realworldtech.com/nehalem/8/

Figura 20.20 Documento Intel Nehalem Deep Dive SSG0203 pagina 12 Figura 20.21 https://en.wikipedia.org/wiki/Intel_X58

Figura 20.22 Datasheet Intel Intel® X58 Express Chipset 320838-004 pagina 18

Figura 20.23 sinistra http://www.hwupgrade.it/articoli/cpu/2274/intel-core-i7-e-core-i5-le-prime-cpu-lynnfield_3.html

Figura 20.23 destra https://techreport.com/review/17513/intel-p55-express-chipset Figura 20.24 Datasheet Intel 322164-004 pagina 22

Figura 20.25 Presentazione Intel Core i5-700 desktop processor Yara Ali Mohamed pagina 7 Figura 20.26

http://www.weiku.com/products/15218456/100_bland_new_and_original_Intel_Core_i5_450M_SL BTY_CPU_Processor_BGA1288_.html

Figura 20.27 sinistra https://www.pcper.com/reviews/Processors/Intel-Westmere-Architecture-and-Clarkdale-Processor-Preview

Figura 20.27 destra https://forum.zwame.pt/threads/intel-clarkdale-core-i3-530-core-i5-661.520065/

Figura 20.28 http://www.hwupgrade.it/articoli/cpu/2288/intel-core-i7-clarksfield-nehalem-anche-nei-notebook_index.html

Figura 20.29 Presentazione sulla piattaforma Intel Calpella Chini Yang 2010

http://slideplayer.com/slide/3254515/ https://www.slideserve.com/malise/intel-platform-calpella-i-ntroduction slide numero 9

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Figura 20.30 http://notebookitalia.it/cpu-intel-westmere-32nm-2009-4696.html Presentazione Intel sul nucleo Westmere a 32 nm di Stephen L. Smith

Figura 20.30 http://www.tankonyvtar.hu/en/tartalom/tamop412A/2011-0063_17_multicore_processors/ch08s03.html

Figura 20.31 https://www.anandtech.com/show/2930

Figura 20.32 Presentazione Intel sul nucleo Westmere a 32 nm di Stephen L. Smith pagine 9 e 10 Figura 20.33, 20.34 "A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors..." 2009 IEEE Xplore S. Natarajan pagina 2

Figura 20.35 Intel HM55 chipset family pagina 1

Figura 20.36 https://www.notebookcheck.it/Intel-Core-i7-920XM-Notebook-Processor.29311.0.html

Figura 20.37 "SANDY BRIDGE SPANS GENERATIONS" Microprocessor Report Linley Gwennap Settembre 2010 pagina 5

Figura 20.38 "Introducing Sandy Bridge Sandy Bridge - Intel® Next Generation Microarchitecture" Bob Valentine pagina 28

Figura 20.39 "Introducing Sandy Bridge Sandy Bridge - Intel® Next Generation Microarchitecture" Bob Valentine pagina 46

Figura 20.40 https://isite.tw/2016/05/08/15783/4 https://isite.tw/wp-content/uploads/2016/05/3960X.jpg

Figura 20.41 sinistra "Introducing Sandy Bridge Sandy Bridge - Intel® Next Generation Microarchitecture" Bob Valentine pagina 9

Figura 20.41 destra "SANDY BRIDGE SPANS GENERATIONS" Microprocessor Report Linley Gwennap Settembre 2010 pagina 4

Figura 20.42 "SANDY BRIDGE SPANS GENERATIONS" Microprocessor Report Linley Gwennap Settembre 2010 pagina 13 e 23

Figura 20.43 Intel datasheet 2nd generation Core desktop 324641-008 pagina 44

Figura 20.44 "Power management architecture of the 2nd generation..." Intel Efi Rotem pagina 25 Figura 20.45 https://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/5 Figura 20.46 https://it.wikipedia.org/wiki/OpenGL

Figura pagina 773 chipset Intel LGA 1155