SVT 2002 Shutdown documentation:
electric and readout tests
This document describes the tests that have been performed on the SVT to control and verify its functionality from the extraction of the support tube to the reassembly and installation at ir2. It includes also the description of the tests on malfunctioning modules.
It is useful to report here the temporal sequence of the tests performed:
•At IR2
•Digital test, calibrations
•IV Characteristic curves
•In Clean Room, SVT still on B1's
•Resistance Test before disassembly outer ST (everything still connected)
•Resistance test on problematic module during uncabling tails from matching card
•SVT on assembly fixture:
•Complete test on problematic module while on assembly fixture
•Test on several modules after the small water accident
•SVT back on B1's:
•Resistance test DURING the insertion of the tails on matching card
•Resistance test after all tails were connected to matching card
•Digital test and Calibration BEFORE ST outer shell on (ES shield on)
•found problems on some modules: (fast digital test after removal of ES shield and tail reinsertion, digital test/calibration on problematics modules after reinstallation of ES shield)
•Resistance test after ST outer shell on
1 Preliminary tests at ir2
Before the extraction of the support tube from IR2 we made a complete set of tests on the detector as a reference for the subsequent tests.
1 Digital tests and calibration
The digital functionality has been verified in two ways: a) using the SvtTestStand program [2] and b)with the somewhat more sophisticated Sts test Suite [3].
In the first case the test verifies the ability to write and read back correctly the control register, the channel mask and the calibration mask, using both the A/B clock line and the left/right readout.
To perform the test is necessary that:
•the front end electronic of the detector must be powered up
•the SVT partition of the Dataflow System must not be in use The procedure consists in
•connecting with a terminal to the serial line of each of the 14 SVT Read Out Modules (xyplex -f odf-svtX-Y where X=0..6, Y=1,2)
•launching the test program SvtTestStand(1)and testing all the readout sections connected to the Read Out Module s32t
•logging the result in a text file.
We performed two calibrations: a noise calibration to measure the noise of each channel and a charge injection calibration to determine its gain. The shape of the noise and the gain as a function of the channel number is different for each readout section and can be considered as its signature.
We followed the usual procedure for a standalone calibration which requires to have the front-end-electronics powered up and the silicon polarized with the nominal bias voltage.
2 Current Voltage Characteristic curves
Current Voltage characteristic curves for each silicon half modules were determined.
This is useful to precisely measure the silicon inverse leakage current after the exposition to the IR ionizing radiation and to verify the basic operational parameters and
functionality of the silicon sensors: strip and guard ring inverse leakage current, depletion voltage.
The instruments needed in order to perform these measurements are[0]:
•Scanner: Keithley 2001
•Programmable source unit (Keithley 230) with two cables to connect to the IV-box.
•One portable computer (IBM think pad) with a GPIB (PCMCIA) board and LabView 5.1 installed and the LabView code for the IV measurement.
•The IV-box and the connector going from the box to the Scanner
•GBIP to PCMCIA cable The procedure is the following
•Switch the SVT OFF and turn off manually the Power Supplies (keys OFF!).
•Keep a log of the HDIs temperature and air temperature/humidity at the IP during the measurements.
•Start Labview and open the SVTIV.vi program. The panel shows three buttons:
CALIBRATE, MEASURE, STOP
•Use a wrist strap to ground yourself
•Calibrate the resistors: make sure the white cables are unplugged from the IV-box to avoid unwanted voltages to the HDIs, press the CALIBRATE button: wait for the message "calibration successfully done";
•Disconnect the data cable from the HDI link card to avoid damaga to the AC capacitors
on the silicon sensors.
• Press MEASURE: when the program prompts you that is safe to plug the white cables out of the HDI link card and plug only the bias white cable in the IV-box.
• Put the numbers on the front panels (such as half-module id, maximum Voltage and value of the step in the Voltage), the defaults should be appropriate for mosts cases.
• Log the time of the measurement! This will help you to find the temperature and
humidity information from the unix script in case there are strong changes due to other people working.
• Start the measurement: on the front panel you can see the current values of IBiasN. In case you want to stop the measurement press the stop button (don't stop the vi with the LabView icon). This causes the voltage source ramping down properly. This
measurement is lost. A software protection causes the ramping down of the voltage if one of the currents has a value grater then 100 uA.
• If you want to see the plot of the three currents, click the VIEW buttons. Updating the plot on the screen slows down the execution of the program. Close this panel as soon as you checked that all is ok.
• The programs prompts you when the measurement is completed . You can unplug the white cable from the IV box and replug it the data and the power cable in the HDI link card.
• If you don't close the principal vi, it is not mandatory to calibrate again. You can do the calibration to take into account the difference in the temperature of the resistors: goto 1, otherwise goto 2.
A reasonable man power is four people divided in two groups. Each measurement takes about five minutes but it took about two days to complete all the 104 half modules. A lot of time was spent interpreting the results from a few "strange" modules (high current)
2 Resistance tests at the clean room
During the transportation from ir2 to the clean room the position monitors ensured that the B1 magnets did not get too close to the SVT to cause any damage, nevertheless we measured the resistances the FEE power and data lines to verify its integrity.
1 Resistance tests with the UCSB cable tester before the extraction of the outer shell of the Support Tube
The material needed for the test is
•UCSB test box
•Breakout box
•One pair of white “test cables” (with female 25 and 37 pins connector and male Burndy connector)
•laptop with LabView 5.1 and custom software to control the UCSB box
•PCMCIA readout card
•wrist strap for grounding
The detailed procedure for the test is described in Appendix ???.
After the initial setup the operations can be conducted by two persons: one examining the results and logging the data on the computer, the other finding the correct SVT support tube cables and and plugging them into the “test cables”. The operation took two shifts of 6 hours each (5,6 Aug. 2002) in part used for the preliminary setup, in part used to
investigate in detail the results that were different from what was expected.
The test showed two unexpected results:
BL2M03-p: we were expecting
R(Data Left+/Data Right+) = short R(Data Left-/CmdA) = short
while we found
R(Data Left+/Data Right+) = 197Ohm R(Data Left-/CmdA) = MOhm
FL4M14-n:we were expecting R(A0/A5) = 1.9kOhm R(D0/D5) = 1.9kOhm while we found
R(A0/A5) =~ MOhm R(D0/D5) =~ MOhm
We interpreted this as the rersult of a movement of the tail during the transportation of the support tube. Other than this the test confirmed the known problems on 5 modules:
FL3M03, FL3M04,BL2M01, BL5M10, BL2M03.
2 Resistance tests during the uncabling of the capton tails
During the extraction of the capton tails from the matching cards we repeated the resistance tests on a the malfunctioning modules in order to learn the exact cause of the failures:
•FL3M03: all the lines were showing open connection.
From visual inspection the cable looked slipped off,
after the Milpac connector was reinserted the resistance values became normal.
•BL5M10-p: R(Data Left+/Data Left+) = 8Ohm
After the tail was wiggled the resistances went to normal values, we concluded that (?) the berg connector was not completely closed.
•BL2M03-p: R(Data Left+/Data Right+) = short R(Data Left-/CmdA) = short
The tail appeared rotated, after reinserting it into the berg connector the resistances went to normal values.
•FL3M04, BL2M01: the shorts on the power lines were not fixed by reinserting the tail nor the Milpac connector, we concluded that the short must be in the connection from the tail to the HDI or on the HDI itself.
•FL4M14: Ground connection was found loose, signal cable was found tilted at the insertion in the matching card. Resistance test showed no problems and the module was functioning properly.
•BL4M10-p:tail was found inserted ?cracked? Resistance test shows no problems and the module was functioning properly.
Illustration 1FL3M03 Milpac connector slipped off (data)
Illustration 2BL2M03-p side tail rotated
3Setup of the SVT test-stand in the clean room
The SVT test stand is needed for the readout and digital tests at the clean room and has to be prepared well in advance. All the boards has to be extracted from the crates and transported in paper boxes, while the rack has to be transferred to bld 31 with a small truck (arrange the transfer with Ray Rodriguez).
It was necessary to request new IP addresses for the ROM, the IOC, the PC and the SUN workstation and prepare a network connection for the HUB from which we derived the other necessary connections.
The test stand is composed of the following parts:
•Power supply: 1 CAEN PS main frame, 1 CAEN A526 board, 1 MUX cable, 2 CAEN A522A board, 1 power cable (black cable)
•Data acquisition: 2 white cables (2 power and 2 data), 1 "middle plane", 1 HDI link card, 1 DAQ link card, 1 VME crate, 1 ROM, 1 FCDM, 1 Partition Master, 1 optical fiber
•Cooling/dry air: 1 chiller (with interlock and labeled hoses), 1 pressure regulator
•SlowControl/Monitoring/Interlock: 1 HTEMP, 2 SIAM, 1 IOC, 1 CAEN V288, 1 computer with at least 3 serial lines
Special attention was needed to setup the permissions to write in the odf nfs space (/nfs/bbr-srv02/dataflow) for the ROM since the module was part of subnet different from the one at IR2. In addition a SUN machine in the same subnet of the ROM was needed to run the standard calibration program.
The test-stand functionality was verified comparing digital tests and calibration of the commissioning module with a reference taken at ir2.
4Tests on the assembly fixture
When the SVT is on the assembly fixture the phi(p) side of layer 5 modules as well as the phi side of layer 5 HDI is visible and we have access to all the capton tails (but there are no matching cards attached to them). With this setup the SVT is extremely vulnerable so the maximum level of care is necessary even for banal operations. A few rules need to be always respected:
•the presence of two people is required for any work on SVT
•when the silicon sensors are exposed you need to wear lab coats
•when working close to the crystals you need to wear face masks
•When connecting cables or touching pins you need to wear ESD protection
1 Rotation
In order to perform the test it is necessary to rotate the SVT and place the tail close to the mounting point for the matching card. To do that you need to:
•open the black box completely
•release the brass bolt on the right side close to the steering wheel that brakes the rotation mechanism,
•Rotate slowly using the steering wheel with one person on each side of the box making sure that the tails do not get caught somewere.
•watch the water lines and make sure they are not pulled out
•when finished secure the brass bolt (brake) and close the black box
•after closing the box wait a few minutes to fill it up with nitrogen.
2 Connecting the matching card
This work requires getting close tho the silicon and the FEE so place one person to watch over your shoulders.
Run a white cable trough the openings on the side of the black-box and make sure the box is light tight. Connect the other end of the white cable to the hdi link card ( which should have a soft link to earth of 5-50kOhms so that the cable itself is grounded).
Prepare the capton tail: bring it close to the berg connector without modifying the existing bends which have been studied to fit well on the B1 magnets. If the tail cannot reach the berg connectors you can modify the position where the matching card is mounted by rotating the mounting piece by 180o or by inserting some spacers under it. Ground the matching card ( for example by touching the pins of the Milpac connector with an aluminum stripe and grounding the stripe).
Insert the capton tail into the berg connector, pay attention not to scratch the metal pads on the tail and use the proper tools to close the connector. This operation looks very simple but most of the times the resulting electrical connection is not correct and you need to reinsert the tail. You really need to get used to it and “get the feeling” before you can do it right. It is quite helpful to make some experience with test pieces that have a berg connector mounted on.
Connect the Milpac connector to the matching card and perform a resistances test to verify the proper insertion of the tail, reinsert it if there is bad connection. Never power up the FEE if the resistance test is not positive since the ATOM chip could be damaged in case of shorted lines.
3 Running a calibration
The readout tests and threshold scans are essential to verify the digital and analog functionality of the FEE. It allows also to verify the basic operational parameters of the detector: noise, gain, thresholds, signal/noise ratio.
The tests have been performed using the “sts test suite” integrated with the "svt test-stand e-logbook" [Error: Reference source not found] . Using Sts for the tests has the advantage of better book keeping, more sophisticated digital tests and ability to run two tests in parallel, it has the disadvantage that root crashes once in a while and there is not yet an automatic comparison with a reference calibration. The complete procedure used in the tests is reported below.
=PREPARE FOR TEST
-When in clean room wear a lab coat -When silicon is exposed wear face mask -When connecting cables wear ESD protection -Find the tail number corresponding to the HM to test -Identify the geometrical position of the module to test (look at drawing on the wall)
=CABLE CONNECTION
-Check ( once per shift) the ground connection of the DAQ rack (MUX-COMMON to earth should be ~5kOhm)
-Connect the white cable to the HDI-link card (matching card side disconnected)
=POWER UP THE MODULE
-Check that the CAEN PS is OFF (key in the OFF position)
-Change the position of jumpers J25,J34,J35 on the A522A board if needed (L1,2 have a different setting
wrt L3,4,5)
-Connect Roy's white cable to the Burndy connector
Connect one or two modules at a time, connect L5/L3/L1-odd_tail_number to RED labeled cable,
L4/L2/L1-even_tail_number to YELLOW cable to avoid confusion. Lookup tail number in
~babarsvt/tail.list
-Check dry air flow ( should be around 9 l/min = 18 cubic feets/hour)
-Disconnect the CAENET lemo cable from the CAEN crate, turn on the the crate, wait
untill bootstrap is finished (the green light “check passed” goes on), reconnect the CAENET
-Check the temperature setpoint on the chiller (16 C) -The chiller has 2 lines labeled on the chiller.
-Open the water valves and set the flux to 2.5 Gallons/hour (in the real SVT we use 5 G/hour but the line is split in two) check the chiller interlock on the SIAM panel ( should be green at this point) and reset it.
-Open the epics panels (if needed) from the babarsvt account on svt-cl-sun [svt-cl-sun]> cleanEpics
-check the termistor reading unsing the convertion table in
http://www.slac.stanford.edu/BFROOT/www/Detector/SVT/Shutdown2002/resist- temp_conv.txt
(remember that there is a 2k series resistance and the convertion table is not calibrated better than 10%)
-Power up the MUX
-Set the bias voltage V0 = 0.0 V
-Check the A2 voltage setting (A2=2.2 V for L1,2,3; A2=2.0 V for L4,5) -Lookup the nominal Bias ( in ~babarsvt/links/svt-lv/bias.list, or
http://www.slac.stanford.edu/BFROOT/www/Detector/SVT/Operations/Maps/ModulesD B.html)
-Power up the forward & backward module.
-Raise the Bias voltage to nominal voltage (1V->10V->nominal voltage) -From this moment do not unplug or wiggle the wite cable
=RUN CALIBRATION TEST
-Power up the ROM crate (if necessary)
-Check that the ROM bootstrap file "startup" in
/nfs/bbr-srv02/dataflow/19/svt/app/ points to the correct file startup -> sts/startup.sts for sts test SW -Bootstrap the ROM (if startup changed since last boot) -log on bbr-dev20 and runSts
-Log currents in the test-stand e-log [Error: Reference source not found] and in the paper logbook, compare them
with the reference currents taken at ir2.
-test digital functionality (read test + loop test) -run calibration
-run the final evaluation
-visit the e-log web page relative to the module
and look at noise and gain w.r.t. the reference calib (run 1597) (or look at ps files in the e-logbook if using STS)
-add a note containig the text "test ok"
=WHEN FINISHED -Set the bias voltage to 0 -Power down the module -power down the MUX.
-Check that the "channel ON" indicator on the CAEN crate is OFF -Turn off the CAEN PS (key in off position)
-Unplug the white cables from the burndy connector.
-exit from root (if using STS)
Performing a full digital test and calibration on the assembly fixture, including the insertion of the tails takes an average of 3 hours. Aat least two people are needed: one actively makes the work, the other whatches over his shoulders. I would not recommend more than two tests per person per day with this setup because of the additional stress involved in this work due to working close to the silicon sensors.
4 Tests on modules with problems 1 Visual inspection
In order to investigate the high bias currents that we see in FL5M17 and FL4M01 we performed a careful visual inspection of those two modules.
To avoid getting close to the silicon at the beginning we used an "alignment monoculus"
that was giving just enough zoom power to see the bondings on the detector.
Much better vision was obtained with a stereo microscope mounted directly on the granite table were the SVT was sitting. Since this kind of microscope needs to reach quite close to the silicon (about 15 cm) you need to:
•fix very well the base to the table so that it cannot slide even if pushed
•tighten all the junctions of the microscope to avoid unwanted movements toward the silicon when positioning the eye on the ocular
•make sure that the microscope is clean from small pieces of dirt that can fall down
•keep one person looking over the shoulders to ensure that you maintain a security distance from the silicon even when looking into the ocular.
Necessary expertise: in order to identify the possible damaged regions the persons
actually looking into the microscope need to have a good previous experience with silicon detectors.
The preparation work and the inspections took about one day, the manpower needed is at least two people.
2 FL5M17
The story of this module can be summarized in the following table:
Date Location I_Bias Digital 5P Calibration
'98 Production @ Pisa IB=2A ID5p=250mA Fine
May '99 – Sept '99
Commissioning @ IR2 IB=2A ID5p=190mA Noisy
Sept '99 – Jul '02
Run1 & Run2 @ IR2 IB>100A ID5p=190mA* (not available) Jul '02 –
Nov '02
Test @ Clean Room IB=160A ID5p=250mA Fine
Nov '02 Run3 @ IR2 IB=160A ID5p=190mA Noisy
Dec '02 – Feb '03
Run3 @ IR2 IB=2A ID5p=190mA Noisy
* Extracted from Ambient DB
The high currents suggest a problem on the silicon sensors like a bonding touching the silicon in the wedge region. After careful visual inspection of the p(phi) side we have concluded that there aren't damages like cracks or scratches on the surface of the silicon nor on the HDI and that the bias bondings on the phi side are not detached.
All the measured resistances on the power and data lines of the FEE are normal. Apart from the high current we noticed that when the HDI is powered up the bias current (160
A) increases with time with a time constant of a few minutes, while when the HDI is off the bias current is stable and lower (IB=60 A).
The calibrations showed completely normal noise and gain levels. Even when using a non standard configuration of jumpers J24,J34,J35 on the A522 CAEN PS board to
investigate the effects of the FEE power on the bias current the analog parameters does not deviation from normal values.
3 FL4M1
The problem on this module is that the bias current is very high (800A @ 18V).
The resistance test didn't any deviation from normal values. The IV measurement on 7 Oct 1999 was already showing a turn on point of the bias current at 5 V with FEE off. IV measurements at the clean room showed also a turn on point at 5 volts.
When the FEE is off the current is lower (100 uA @ 22 V) while with FEE on the current
is higher (100 uA @ 6 V). The limitation of the bias current on the A522 boards did not allow the module to go above 10 volts and thus suggests that the detectors are not completely depleted (V_op=24V, 16V, 42V).
A modified version of the A522 has made possible to calibrate ( at ir2) the module even with 40V bias. The calibration is normal on the phi side while the zed (n) side shows high noise on channels with x2 ganging suggesting that the strips on the second detector are not isolated even at high voltages. The big increase in noise in the first channels of chip 3- z side suggests that most of the bias current goes trough the third detector.
Illustration 3FL4M01 zed side noise and threshold @ 5 V (calib. 20339)
5 Burning the shorts
We also tried to burn the shorts on BL2M01-n and FL3M04-p using a current generator limited in voltage. We generated a current of 1.5 Amp trough the short but this didn't eliminate it.
6 Tests on recovered modules
We verified the complete digital and analog functionality of the recovered modules FL3M03, FL3M05, BL2M03, BL5M10. In the case of FL3M05 the problem at ir2 was digital errors and a low current on D5P (since 3/May/'99). The fix to this problem was
initially thought to be the reinsertion of the tail but we learned eventually that the HDI link card was malfunctioning and after the replacement of the card the module started working correctly.
7 Additional tests/repairs
Before remounting the SVT on the beam pipe we took the chance to inspect with the stereo microscope a few modules on the split plane.
We noticed an aluminum debris sitting on FL3M06 z-side. The debris could have moved and created shorts or other damages to the microbondings thus we decided to remove it out. A tweezer and a firm hand was enough to remove the debris.
Illustration 4FL4M01 zed noise and threshold @ 40 V (caib. 1626)
On FL4M13 z side we noticed a wire bond sticking out from the edge of the silicon but we didn't take any action to remove it since the half module was working properly.
5 Re cabling of the capton tails
1 Resistance tests during the insertion of the tails
As a matter of fact it is quite difficult to establish a good electrical connection between the capton tails and the matching card with the berg connector. For this reason we
checked the electrical connection of each tail with the UCSB cable tester after each insertion. The test was done in parallel to the insertion as soon as the modules become ready. About 12% of the insertions resulted in a bad electrical connection requiring at least a repositioning of the tail into the berg connector. On a total of of 208 tails 25 had to be reinserted, some of them even 5 times before obtaining a good connection.
The testing operation took place as usual with one person operating the computer and one person connecting the cables. The whole operation took two days.
It was very useful to have the big labels on the cables showing the tail number, rather than looking at the tiny labels on the cable itself as well as having printed maps of the
correspondence between tail numbers and modules.
When all the tails were connected we performed another complete resistance test on all the modules. In this case we didn't encounter unexpected values and the operation was finished in about 3 hours per side.
2 Readout tests and missing data R+
In order to test the complete functionality of each module was necessary to readout the front end electronics with the silicon sensors powered up. To do this the dry air lines need to be connected to the nitrogen supply (with pressure regulator), the cooling lines need to be connected to the chiller and the aluminum electrostatic shield need to be installed in order to prevent illumination of the silicon.
We connected two modules at a time and performed the digital test/calibration in parallel from two different working stations. The procedure followed is the same as described in sec. 3 [running a calibration].
Surprisingly enough a few modules failed the "Read from Right"digital test [table 1].
Given that any other parameter was normal, included the resistances, we ended up looking with an oscilloscope on the HDI link card test points at the signals coming back from the ATOM chips. We discovered that in all cases the positive polarity of the signal was missing. The data lines are terminated with a 512 Ohms resistor on the matching card and they usually have high (Mohms) resistance with any other line. If the data lines were actually open on the berg connector (or on the tail) the UCSB cable tester would have not seen any effect because of the terminating resistor.
Lesson learned: to ensure the proper electrical connection between the tail and the matching card is necessary to perform a readout test.
Module Signal Action Result
FL1M01-p Read Left positive polarity missing Read Right positive polarity missing
Tail repositioned Tail repositioned
Fixed Fixed
FL5M17-p Read Right positive polarity missing
The data-right + line on the tail has a scratch that interrupts the trace
BL1M05-n Read Right positive
polarity missing Tail repositioned Fixed
BL5M05-n Read Right positive polarity missing
Tail repositioned problem on hdi side, not possible to fix.
BL5M07-p Read Right positive polarity missing
Berg connector secured
The berg connector was found not completely closed, after closing it the problem was fixed.
Table 1Read right problem after the cabling of the capton tails
6 Summary of the status after internal cabling at ir2
After the digital and readout test the summary of the status of the SVT is the following:
•Six non functioning read-out sections have been fixed:
•FL3M03(phi/z-side): signal cable slipped off, fixed by re-plugging signal cable
•FL3M5(z-side): I(D5p low), fixed (problem discovered on hdi link card at ir2)
•FL5M17(phi-z-side): didn’t hold bias, fixed itself
•BL2M03(z-side): DL-/CmdA short, fixed after tail reinsertion
•Only 3 non functioning read-out sections could not be fixed:
•
FL4M01: Silicon doesn't hold bias n-side not readout
•
FL3M04: A2p-A5p short p-side not readout
•
BL2M01: A2n-A0n short n-side not readout
•No new non functioning read-out sections were introduced.
•We've lost two redundancies
•FL5M17 [p-side] read right: the tail was scratched probably inserting the tail into the berg connector during the tests in the assembly fixture
•BL5M05 [n-side] read right: we suppose that the tail moved into the berg connector on the hdi.
•and we have two new single chip problems
•BL4M01 n-side chip 1 ClkA
•BL2M02 p-side chip 6 ClkA: a possible explanation for the failure is that the other half of the SVT (BL2M03) has touched chip 6 damaging the micro-bondings of clock A since this chip stis right on the split plane.
7references
[0] http://www.slac.stanford.edu/~calderin/IVMeasurements/IV_measurements.html [1]http://www.slac.stanford.edu/BFROOT/www/Detector/SVT/
[2]http://www.slac.stanford.edu/BFROOT/www/Detector/SVT/Operations/Manual/tools.
html#teststand
[3] http://www.slac.stanford.edu/BFROOT/www/Detector/SVT/Shutdown2002/Sts_Help.
html
