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[2] B. Moyer “Low-Power Design for Embedded Processors”, Proceedings of the IEEE, Vol. 89, No. 11, November 2001, Pages: 1576 – 1587.

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Bibliografia.

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[3] V. Tiwari, S. Malik, P. Ashar “Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 10, October 1998, Pages:

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[16] G. Sutter, E. Todorovich, S. Lopez-Buedo, E. Boemo “Low -Power FSMs in FPGA: Encoding Alternatives”, INCA, Universidad Nacional del Centro, Tandil, Argentina and Computer Engineering School, Universidad Autonoma de Madrid, Spain.

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Synopsys User Group, San Jose, March 2000.

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