Control System Implementation on Vivado and Simulations
3.2 ADC Implementation and Test
enable the IGBTs driving signals only if a protection action is not necessary, as will be more clear in the following.
ADC
Vin ADC
I
Current Controller
PWM Modulator
Modules Protection Control System
DAC 4 DAC 3 DAC 2
DAC 1 Oscilloscope CH1
Oscilloscope CH2 DAC
Gate T1
Emergency Button FAULT Signals
Control
Voltage Gate HS
Gate LS Gate T2
Gate T3 Gate T4
Gate T6 Gate T5
Gate T7 Moving
Average
Figure 3.4: System components implemented on the FPGA.
data is available. Referring to Figure 3.5, the following important timing specifications need to be respected:
• minimum t1: 3 ns;
• minimum tQUIET: 4 ns;
• minimum t2: 6 ns.
Figure 3.5: AD7276 SPI protocol timing diagram from [13].
The implemented ADC manager is composed of a Finite State Machine (FMS) whose state diagram is depicted in Figure 3.6. In particular, Figure 3.6a highlights the input signals which determine the next state depending on the current state, whereas Figure 3.6b reports the FSM outputs as functions of current state and inputs. The whole ADC manager scheme, depicted in Figure 3.7, highlights the presence of the various entity inputs and outputs, the FSM and the Execution Unit (EU). The latter is responsible for the correct signals timing specifications required by the SPI protocol besides the 12-bit word reconstruction. For this reason, it is composed of the following elements:
• a counter to set the correct SCLK signal frequency;
• a counter to compute the transitions of the SCLK signal, and consequently its cycles, to manage the transmission length;
• a counter to guarantee that the 𝐶𝑆 signal stays high for the minimum amount of time between two transmissions;
• a shift register, whose input is the SDATA signal, to receive and store all the 14 transmission bits;
• an output register, to provide the correct 12-bit data at the output;
• an edge-triggered D Flip-Flop, to generate the ADC_data_ready signal when the output data is available.
IDLE reset = 0
START
SCLK_DOWN SCLK_UP
ADC_start = 1
ADC_start = 0
SCLK_transition = 1 last_bit = 0
SCLK_transition = 1 last_bit = 1
SCLK_transition = 0
SPI_WAIT SCLK_transition = 1
SCLK_transition = 0
CS_up_time_elapsed = 0
CS_up_time_elapsed = 1 ADC_start = 1
CS_up_time_elapsed = 1 ADC_start = 0
(a)
ADC_CSn = 1 ADC_SCLK = 1 run_counter = 0 wait_SPI = 0 shift = 0
ADC_CSn = 0 ADC_SCLK = 1 run_counter = 0 wait_SPI = 0 shift = 1
ADC_CSn = 0 ADC_SCLK = 0 run_counter = 1 wait_SPI = 0 shift = 0 ADC_CSn = 0
ADC_SCLK = 1 run_counter = 1 wait_SPI = 0 shift = 0
ADC_CSn = 1 ADC_SCLK = 1 run_counter = 0 wait_SPI = 1 shift = 0
IDLE
START
SCLK_DOWN SCLK_UP
SPI_WAIT ADC_CSn = 0 ADC_SCLK = 0 run_counter = 1 wait_SPI = 0 shift = 0 ADC_CSn = 1 ADC_SCLK = 1 run_counter = 0 wait_SPI = 0 shift = 0
ADC_CSn = 0 ADC_SCLK = 1 run_counter = 1 wait_SPI = 0 shift = 1
ADC_CSn = 0 ADC_SCLK = 0 run_counter = 1 wait_SPI = 0 shift = 0
ADC_CSn = 1 ADC_SCLK = 1 run_counter = 0 wait_SPI = 1 shift = 0
ADC_CSn = 1 ADC_SCLK = 1 run_counter = 0 wait_SPI = 1 shift = 0
(b)
Figure 3.6: AD7276 manager FSM state updates (a) and outputs (b).
Depending on the FSM outputs, the blocks in the EU are accordingly enabled. On the other hand, the outputs of the different counters are exploited to trigger the FSM
FSM
>
EN reset
SCLK_counter counter_SCLK
CLRn = counter_SCLK_limit
SCLK_transition run_counter
counter_SCLK_CLRn
>
EN reset
Transition_counter counter_transitions
CLRn = counter_transitions_limit counter_transitions_CLRn
= counter_transitions_limit-1 last_bit
>
EN
EN reset
CSn_UP_counter counter_CSn_UP
CLRn = counter_CSn_UP_limit
counter_CSn_UP_CLRn CSn_up_time_elapsed
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
DresetQ EN
>
ADC_SDATA
shift wait_SPI
0 1 2 3 4 5 6 7 8 9 10 11 12 13
REGISTER
>
reset
12 ADC_DATA
end_transmission
DresetQ EN
>
SresetQ R
>
ADC_data_ready
Data_ready Output_data
SHIFT_REGISTER ADC_start ADC_CSn
ADC_SCLK
Figure 3.7: AD7276 manager entity organization.
state updates. In the figure, also an edge-triggered SR Flip-Flop is present: this is due to the fact that every ADC, when experimentally tested, generates a wrong first sampled data. For this reason, the inserted SR Flip-Flop goal is to neglect the first transmission, enabling the ADC_data_ready signal starting from the second conversion. For simplicity, the reset and clock signal lines are not indicated in the figure.
The ADC manager operation can be easily explained by noticing that, when the 𝐶𝑆 signal goes low, each transmission bit is provided by the ADC in correspondence of every SCLK falling-edge, therefore the shift register enable signal is provided on every SCLK rising-edge so that the input bit is correctly received. When all the 14 transmission bits are transferred, the output register is enabled to provide at the output the corresponding 12-bit data and the ADC_data_ready signal is driven high for one system clock cycle; at the same time, the 𝐶𝑆 signal is driven high for 12.5 ns.
In the figure, different programmable variables can be seen. In the following discus-sions, the hereby reported specific values are used:
• counter_SCLK_limit = 0;
• counter_transistions_limit = 27;
• counter_CSn_UP_limit = 0.
Considering a 80 MHz system clock frequency, these parameters values correspond to the generation of a 40 MHz SCLK signal, characterized by 14 cycles inside a transmission.
The obtained t1and t2are both equal to 12.5 ns. Finally, it is important to underline that
a single ADC has been considered in Figure 3.7; anyway, since on the PCB, as already discussed, only the B-grade AD7276 ADCs are present, by deploying other shift and output registers and SDATA signal lines, the same manager can simultaneously handle more than one transmission at the same rate by providing the ADCs with the same SCLK and 𝐶𝑆 signals.
The ADC manager block design implemented in Vivado is reported in Figure 3.8.
As shown, a Clocking Wizard IP generates the 80 MHz system clock frequency, whereas the VIO IP provides the ADC manager entity with the active low reset signal and with the always active ADC_start signal which triggers the conversion whenever possible.
The ADC sampled data corresponds to the current flowing in the Guasch power stack node U, underlined in Figure 3.3, and is therefore expected to be approximately equal to 2047, since no current is flowing in the circuit. Then, the outputs of the manager can be visualized in Figure 3.9 by exploiting the ILA IP. In particular, in the figure, the 𝐶𝑆, SCLK, ADC_data_ready signals and the 12-bit data are reported in this order:
as can be seen, the wanted operation is verified. Anyway, the obtained data does not exactly correspond to expected value: this is mainly due to the tolerances in the ADCs conditioning circuits which introduce an error in the sampled quantities. In the setup which is exploited for the control system experimental validation, this error magnitude is negligible for what concerns the sampled currents, whereas it is compensated for the input voltage one. For this reason, in the following discussions a proper multiplication factor will be considered in the Vin_GAIN term highlighted in Figure 2.17.
clk_in1_0 ADC_SDATA1_0
clk_wiz_0
Clocking Wizard reset clk_in1
clk_out1 locked
vio_0
VIO (Virtual Input/Output) clk probe_out0[0:0]
probe_out1[0:0]
ADC_AD7276B_0
ADC_AD7276B_v1_0 clk
reset ADC_start ADC_SDATA1
ADC_CSn ADC_SCLK ADC_DATA1[11:0]
ADC_data_ready
ila_0
ILA (Integrated Logic Analyzer) clk
probe0[0:0]
probe1[0:0]
probe2[0:0]
probe3[11:0]
ADC_CSn_0 ADC_SCLK_0
Figure 3.8: AD7276 manager block design in Vivado.
Figure 3.9: AD7276 manager operation waveforms.
It is important to compute the total conversion time in order to justify the previously reported multisampling factor NMS choice. The maximum allowed time for the ADC conversion, hence the sampling trigger period, is computed in (3.1) recalling (2.2).
𝑡𝐴 𝐷𝐶 , 𝑀 𝐴 𝑋 = 32𝑇𝑐𝑙 𝑘 = 32 1
80 MHz = 400 ns (3.1)
The ADC conversion time can be in turn derived in (3.2) considering that the START state duration is equal to a system clock period and that the 𝐶𝑆 signal is brought high during the last SCLK signal rising-edge, as also highlighted in Figure 3.9. As computed, its value is below the maximum one and the chosen multisampling factor can be used.
𝑡𝐴 𝐷𝐶 = 𝑡𝑆𝑇 𝐴 𝑅𝑇 + 14𝑇𝑆𝐶 𝐿 𝐾 = 12.5 ns + 14 · 1
40 MHz = 362.5 ns < 400 ns (3.2) Considering a given sampling instant, it is impossible, in the designed control system, to compute the average based on the most recent samples and to execute the current controller before the following sampling instant. For this reason, as mentioned in the previous chapter, the averager output data is updated on every sampling instant whereas the current controller is executed after the last sampling instant before the control voltage updating one. This strategy allows a whole sampling period for the current controller termination.