Three-Phase Inverter Average Current Control Implementation
4.4 Clarke’s and Park’s Transforms Implementation and TestTest
a 100 Hz reference frequency. The experiment result is reported in Figure 4.7. As can be seen, the wanted waveforms are correctly generated.
Figure 4.5: Sine and cosine generator block scheme top-level view.
clk_in1_0
clk_wiz_0
Clocking Wizard reset clk_in1
clk_out1 locked
vio_0
VIO (Virtual Input/Output) clk probe_out0[0:0]
probe_out1[15:0]
PWM_MODULATOR_0
PWM_MODULATOR_v1_0 reset
CLK_80MHz Control_voltage[15:0]
Gate_HS Gate_LS Sampling_trigger Controller_execution Vcontr_update
Sin_cos_0
Sin_cos_v1_0 reset clk_1 f_ref[15:0]
sin[11:0]
cos[11:0]
DAC124S805_0
DAC124S805_v1_0 clk
reset data_ready DATA_CH1[11:0]
DATA_CH2[11:0]
DATA_CH3[11:0]
DATA_CH4[11:0]
DAC_SYNCn DAC_SCLK DAC_DIN
ila_0
ILA (Integrated Logic Analyzer) clk
probe0[0:0]
probe1[11:0]
probe2[11:0]
DAC_SYNCn_0 DAC_SCLK_0 DAC_DIN_0
Figure 4.6: Sine and cosine generator block design in Vivado.
4.4 Clarke’s and Park’s Transforms Implementation and
(a)
(b)
(c)
Figure 4.7: Sine and cosine generator oscilloscope waveforms with reference frequency set to (a) 50 Hz, (b) 60 Hz and 100 Hz (c).
Figure 4.8: Inverse Clarke’s and Park’s transforms block scheme in Simulink.
Figure 4.9: Inverse Clarke’s transform block scheme in Simulink.
Figure 4.10: Inverse Park’s transform block scheme in Simulink.
The top-level view is reported in Figure 4.11 to highlight the presence of blocks needed to correctly plot the generated waveforms on the oscilloscope through the DAC:
in particular, the expected outcome is to obtain three-phase sinusoidal waveforms at the given reference frequency whose amplitude depends on the dq-frame reference currents values, provided in single floating point precision. If Iqis kept null, the amplitude of the three waveforms needs to be equal to the Id value, as can be derived by recalling (4.14) and (4.16).
Figure 4.11: Inverse transforms top-level view block scheme in Simulink.
The VHDL code is then automatically generated and imported in Vivado to deploy the block design depicted in Figure 4.12: as shown, the PWM modulator block is exploited to produce the controller execution trigger signal to correctly generate the sine and cosine waveforms. The dq-frame reference current and the reference frequency values are provided by the VIO IP. An example of experimentally obtained waveforms is reported in Figure 4.13, where the reference frequency, Iq and Id values are respectively set to 50 Hz, 0 A and 10 A. In particular, the oscilloscope data has been converted accordingly in order to show the measurements in terms of current instead of voltage. As shown, the expected behavior is obtained.
clk_in1_0
clk_wiz_0
Clocking Wizard reset clk_in1
clk_out1
locked vio_0
VIO (Virtual Input/Output) clk
probe_out0[0:0]
probe_out1[31:0]
probe_out2[31:0]
probe_out3[15:0]
PWM_MODULATOR_0
PWM_MODULATOR_v1_0 reset
CLK_80MHz Control_voltage[15:0]
Gate_HS Gate_LS Sampling_trigger Controller_execution Vcontr_update
inverse_0
inverse_v1_0 reset Trigger Id[31:0]
Iq[31:0]
fref[15:0]
Ia[11:0]
Ib[11:0]
Ic[11:0]
DAC124S805_0
DAC124S805_v1_0 clk
reset data_ready DATA_CH1[11:0]
DATA_CH2[11:0]
DATA_CH3[11:0]
DATA_CH4[11:0]
DAC_SYNCn DAC_SCLK DAC_DIN
ila_0
ILA (Integrated Logic Analyzer) clk
probe0[0:0]
probe1[11:0]
probe2[11:0]
probe3[11:0]
DAC_SYNCn_0 DAC_SCLK_0 DAC_DIN_0
Figure 4.12: Inverse Clarke’s and Park’s transforms block design in Vivado.
The direct Clarke’s and Park’s transforms correct operation is validated by exploiting the inverse transforms previously designed, as shown by the block scheme reported in Figure 4.14: the idea is to provide specific reference values at the input and obtain the same values at the output. The implementation of the direct Clarke’s and Park’s transforms is based on (4.13) and (4.15), as shown in Figure 4.15 and Figure 4.16 respectively.
As before, a triggered subsystem is exploited, as highlighted in Figure 4.17, to properly generate the sine and cosine functions depending on the input reference frequency.
Figure 4.13: Inverse Clarke’s and Park’s transforms oscilloscope waveforms.
Figure 4.14: Inverse and direct Clarke’s and Park’s transforms block scheme in Simulink.
Figure 4.15: Direct Clarke’s transform block scheme in Simulink.
Figure 4.16: Direct Park’s transform block scheme in Simulink.
Figure 4.17: Inverse and direct Clarke’s and Park’s transforms top-level view block scheme in Simulink.
The automatically generated VHDL code is then imported in Vivado to deploy the block design depicted in Figure 4.18. As can be seen, the Clocking Wizard IP provides the 80 MHz frequency system clock, the PWM modulator block generates the controller execution signal to trigger the transforms operation, whereas the VIO IP is exploited to provide the dq-frame reference signals in single floating point precision and the reference frequency values. An example of the obtained values visualized on the ILA is reported in Figure 4.19, where the Controller_execution signal, the dq-frame reference values and the Id and Iq values at the output of the block are depicted in this order, exploiting the hexadecimal representation. In particular, fref, Iq_ref and Id_ref are respectively set to 50 Hz, 0 A and 5 A. As can be noticed, the obtained values are identical to the corresponding reference, proving the direct transforms implementation correct operation.
clk_in1_0
clk_wiz_0
Clocking Wizard reset clk_in1
clk_out1 locked
vio_0
VIO (Virtual Input/Output) clk
probe_out0[0:0]
probe_out1[31:0]
probe_out2[31:0]
probe_out3[15:0]
PWM_MODULATOR_0
PWM_MODULATOR_v1_0 reset
CLK_80MHz Control_voltage[15:0]
Gate_HS Gate_LS Sampling_trigger Controller_execution Vcontr_update
inverse_direct_0
inverse_direct_v1_0 reset
Trigger Id_ref[31:0]
Iq_ref[31:0]
fref[15:0]
Id[31:0]
Iq[31:0]
ila_0
ILA (Integrated Logic Analyzer) clk
probe0[0:0]
probe1[31:0]
probe2[31:0]
probe3[31:0]
probe4[31:0]
Figure 4.18: Inverse and direct Clarke’s and Park’s transforms block design in Vivado.
Figure 4.19: Inverse and direct Clarke’s and Park’s transforms ILA values.