AER input request signal
3.8 The Integrate–and–Fire Silicon Neuron
Figure 3.16: Normalized EPSP amplitude in response to the first ten pulses of a 20Hz train of spikes for three different values of V wd (see lower left inset in graph). The data were measured with all other parameters set to the same values as reported in Fig. 3.15.
ferent values of the depressing weight (V wd = 4.13 V , 4.15 V , 4.17 V , 4.19 V , 4.21 V and 4.23 V ). The measurement was repeated 5 times for each value of the depressing weight. Each data point is the mean over the five measurements; the error bar represents the maximum maximum of the measurement error and the standard deviation of the mea-sured values. Both the EPSP meamea-sured at the steady state and the rate at which the steady state is reached are sensitive to this parameter.
3.8 The Integrate–and–Fire Silicon Neuron
The implementation of the single neuronal cell can be done at different level of complex-ity. The analog circuit can model the dynamics of ionic currents [99], implementing the Hodgkin–Huxley model [58] to produce a detailed simulation of the integration of inputs and the spike generation. This type of circuit usually requires a large number of transistors and bias parameters, and hence is not suitable to build large arrays of neurons. On the other extreme, it is possible to model the neuron as a Linear Threshold Unit (LTU): the output of the cell is zero for low inputs and it is a linear function of the input for inputs higher than a fixed threshold. The output of the cell can be seen as a mean firing rate. This is a very simple model, which can be implemented with a few transistors and needs a small number of bias parameters [55]. The main disadvantage of the LTU is that temporally cor-related activity cannot be simulated to explore temporal dynamics of neuronal interaction.
In between this two extremes we have the Integrate–and–Fire (I&F) neuron. It is a spiking model, but does not try to mimic the mechanisms for the generation of spikes of biological cells.
−+Iin Vrfr
Vthr Vpw Cr
Vpb
Cfb Vleak
CmVout
Vsoma /Vout (a)
τadap
Iadap
Vsoma Cadap
/Vout Vadap (b) Figure3.17:Schematicdiagramoftheintegrate–and–fireneuron.(a)WhenVout=0(nooutputspike),theinputcurrentIinislinearlyintegratedbythe somacapacitanceC=Cm+Cfb.AsVmemcrossesfrombelowthethresholdvoltage,Vthr,theoutputvoltageisdriventoVdd,andanoutputspikeis emitted.Theoutputvoltageisthendriventoground,andthetimeneededtoresetitiscontrolledbythebiasvoltagesVpw(whichsetsthedurationofthe outputspike)andVrfr(whichsetsthedurationoftherefractoryperiod).ThebiasvoltageVleakisusedtocontroltheleakcurrent,whichisactiveonlyin absenceofspikes(thespikedurationdoesnotdependontheleakcurrent).(b)SpikefrequencyadaptationisimplementedbyaCMIwhichintegratesthe outputspikesandgeneratesanegativecurrentIadaptoreducethespikingfrequency.
3.8. The Integrate–and–Fire Silicon Neuron 43 Networks of I&F neurons have been shown to exhibit a wide range of useful com-putational properties, including feature binding, segmentation, pattern recognition, onset detection, input prediction, etc. [82]. These types of networks are very well suited for VLSI implementation [47]. Recent and growing interest in pulse–based neural networks (for which detailed simulations are CPU–intensive), together with the emergence of a standard that allows VLSI neurons to communicate using asynchronous pulse–frequency modulated events (see chapter 2), have led to the development of a large number of VLSI implemen-tations of networks of I&F neurons [28, 65, 66, 79, 85, 91].
The neuron circuit I use is an I&F leaky neuron based on circuits proposed by Mead [88] and by van Shaik et al. [117]. The neuron linearly integrates the total afferent current, and when a threshold is crossed it emits a spike and the integrated voltage (or membrane voltage) is reset to its initial value. The subthreshold dynamics can be described by the equation governing the voltage across a capacitor (which represents the membrane voltage of the cell): where I(t) is the sum of all excitatory and inhibitory input currents, Ileak is the leak current and C is the soma capacitance. As Vsoma crosses the threshold, θ, a spike is emitted and the membrane potential is reset to Vreset. Equation 3.14 must be complemented by the condition that Vsoma cannot go below a minimal value Vrest, which represents the resting potential of the neuron.
A schematic diagram of the circuit implementing the neuronal dynamics is shown in Fig. 3.17. The total dendritic input current, I(t) = Iexc− Iinh, is injected into the soma capacitance, C = Cm + Cf b (as shown in Fig. 3.17(a)). The leak current, Ileak, is set by the bias voltage Vleak, and is turned off during the emission of a spike such that the duration of the spike does not depend on the leak current. As Vmem crosses from below the threshold voltage, Vthr, the output of the comparator switches from ground to the positive power supply rail, Vdd (spike activation). A positive feed–back loop, implemented by the capacitive divider Cm-Cf b, increases Vmem by V ddCmC+Cf b
f b (see section 3.3). The positive feed–back guarantees that small fluctuation of Vmem around Vthr are not possible. When Vout is high, the current set by the bias voltage Vpw can flow and discharge the capacitor Cm causing the membrane voltage Vmem to decay linearly. As Vmem crosses again (this time from above) the threshold voltage, the output of the comparator goes back to the ground level. As a consequence, the first inverter sets its output high and switches on the n–type transistor of the second inverter, allowing the capacitor Cr to be discharged at a rate controlled by Vrf r. This bias voltage controls the length of the neuron’s refractory period:
the current flowing into the node Vmem is discharged to ground, and the membrane voltage does not increase for as long as the voltage on Cr (Vout) is high enough. Figure 3.17(b) shows the CMI (see section 3.5) implementing spike–frequency adaptation. In [61] Hynna and Boahen demonstrated how to implement spike–frequency adaptation by connecting a CMI in negative–feedback mode to any I&F circuit. A negative current Iadap is generated by the CMI as the adaptation capacitor, Cadap, integrate the current set by Vadapin response
to output spikes generated by the I&F neuron.
3.9 Discussion
In this chapter I described the main elementary circuits widely used in neuromorphic en-gineering, and which I use to implement the VLSI spiking neural network described in Chap. 5. Although the silicon neuron circuit I described has been used for quite some time by the neuromorphic community, the adaptive synaptic circuit I proposed is an original con-tribution. To analytically characterize the synaptic circuit used in the network, I proposed a mathematical description of the CMI dynamics in response to input spikes, extending the analysis presented in [61]. I used the equations describing the CMI dynamics to simulate the synaptic response in the neural network software simulation described in section 4.4, predicting the behavior of the VLSI neural network described in section 5.1 as accurately as possible.
The measurements performed on the synaptic circuit by varying the input frequency and the bias voltages are consistent with the mathematical analysis, confirming that second order effects can be safely neglected when simulating the circuit behavior in software. The mathematical formulation presented here can be useful to aid the design of novel circuits comprising instances of CMIs.