The PCI–AER Board

The need for a custom device to easily interact with neuromorphic chips with spiking neu-ral networks quickly increased with the emergence of the AER protocol as a standard for communication between these chips. In 2000, at the Physics Laboratory of the Italian Insti-tute of Health (Rome, Italy) the PCI–AER project was started to provide flexible and easy interaction between a standard personal computer and an interconnected system of possi-bly heterogeneous AER chips. The PCI–AER board provides real–time routing between neuromorphic chips, with programmable connectivity, monitoring and stimulation of up to four chips and a communication bridge between AER and the PCI bus. The PCI-AER board takes the form of a 33MHz, 32-bit, 5V PCI bus add-in card (see Fig. 2.5) installed in a host personal computer. A 68-way cable is used to connect the PCI–AER board to a small header board (see Fig. 2.6) which can be conveniently located on the benchtop, and provides connectors for up to four AER receivers and four AER senders. The header board also electrically buffers the signals to and from the receivers and senders. Senders must use

2CAVIAR is the acronym of the European funded project IST–2001–34124: Convolution AER Vision Architecture for Real Time.

Mapper FIFOFPGA 2Monitor FIFOSequencer FIFO FPGA 1PCI InterfaceSRAM68 Pin Cable Connector Figure2.5:PCI–AERboard.Thedevicesinvolvedintheimplementationofthethreemajorfunctionalblocks(seeFig.2.7)arehighlighted:MONITOR, MAPPER,andSEQUENCERFIFOs,FPGA1,andFPGA2.TheSRAMisusedtoholdthemapper’slook–uptable.A68pincableconnectorisusedto connecttotheheaderboard(seeFig.2.6).ThePCIinterfacemanagesthecommunicationwiththehostpersonalcomputerthroughthePCIbus.

2.5. The PCI–AER Hardware Infrastructure 17

68 Pin Cable Connector

Cable Driver

External Power Supply To Receiver

Chips Sequencer Connector From Sender Chips

Status LEDs

Figure 2.6: PCI–AER header board. The header board is connected to the PCI–AER board through a 68-way cable and it can be conveniently located on the benchtop. The header board provides connectors for up to four AER receivers and four AER senders plus the SEQUENCER connector.

The external board has five LEDs, three yellow and four red. Close to the 68 pin connector there is the Power ON LED. Next to it there are FIFO Full alert LEDs for the MAPPER, MONITOR and SEQUENCER respectively. The yellow LEDs are used to indicate the status (LED on means enabled) of the three functional blocks (SEQUENCER, MONITOR, and MAPPER respectively).

the SCX multi-sender AER protocol [36], in which request and acknowledge signals are active low, and the bus may only be driven while the acknowledge signal is active. Receivers may use either this SCX protocol, or they may choose to use a P2P protocol [1] in which request and acknowledge are active high and the bus is driven while request is active. Which protocol is generated by the board may be selected under software control.

As illustrated in Fig. 2.7, the PCIAER board can perform three functions which are executed by blocks we refer to as the monitor, sequencer, and mapper. These blocks are controlled by two FPGAs (FPGA1 and FPGA2 in Fig. 2.5) on the board.

The PCI–AER board has four main components:

Arbiter Up to four sender chips can be connected to the PCI–AER board. The on board arbiter implements arbitration of events generated by the different sender chips. This allows multiple sender devices to access the AE bus.

Monitor Arbitrated events generated by the sender chips are time–stamped and recorded by the monitor. Stored events can be then accessed from the personal computer via the PCI bus. This is useful for logging data, and it allows the user to analyze the activity of the connected devices off–line, without affecting the performance of the system.

Sequencer Using the sequencer, up to four receiver chips can be stimulated with pre–

defined spike trains. Synthetic spike trains can be generated using the personal com-puter and downloaded to the board via the PCI bus.

Mapper The connectivity pattern between up to four sender chips and up to four receiver chips is implemented by the mapper. Transceiver chips can be connected as sender

FPGA 1

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Figure 2.7: Block diagram of the PCI–AER interface board showing its three major functional blocks, i.e. the MONITOR, the SEQUENCER, and the MAPPER (divided into MAPPER–IN and MAPPER–OUT). These (and other blocks) are implemented in two FPGAs on the PCI–AER board.

Also shown are the FIFOs, the interface to the PCI bus, the SRAM used to hold the mapper’s look–

up table, the cable buffers, and the interconnecting buses.

and receiver at the same time, using the PCI–AER to externally configure their “in-ternal” connectivity. Arbitrary network topologies can therefore be implemented and reprogrammed on–line.

Using these components the board implements the functions described below.

Monitoring

The PCI–AER board can monitor the spiking activity of up to four sender chips. The monitor captures and timestamps events coming from the attached AER senders via an arbiter, and makes those events available to the personal computer for further processing.

A timer is implemented in one of the FPGAs, and when an incoming address–event is read, a timestamp is stored along with the address in an 8KWord First–In First–Out (FIFO) memory. This FIFO decouples the management of the incoming address–events from read operations on the PCI bus, the bandwidth of which must be shared with other peripherals in the personal computer such as the network card. Interrupts to the host personal computer can be generated when the FIFO becomes half–full and/or full, and in the ideal case, the driver will read time stamped address–events from the monitor FIFO whenever the host

2.5. The PCI–AER Hardware Infrastructure 19 CPU receives a FIFO half–full interrupt at a rate sufficient that the FIFO never fills or overruns, given the rate of incoming address–events. Each event is stored in the form of three successive 18 bits words. The two most significant bits of the word encode the type of information stored in the other 16 bits. A word can contain four different type of information: AE, Time High (16 most significant bits of the 32 bits word encoding the time–stamp), Time Low (16 less significant bits of the 32 bits word encoding the time–

stamp), Error or Control code. The time resolution can be set to four different values: 1, 10, 50 or 100 µs. The AE is coded differently depending on the number of sender chips:

1 sender chip 16 bit address word.

2 sender chips The most significant bit of the AER address encodes the chip label. The address word is encoded by the remaining 15 less significant bits.

4 sender chips The two most significant bits of the AER address encode the chip label.

The address word is encoded by the remaining 14 less significant bits.

Stimulating

The PCI–AER board can be used to stimulate receiver chips using synthetic trains of AEs.

This function is implemented by the sequencer. These events may for example represent a pre–computed buffered stimulus pattern, but they might also be the result of a real time computation. This allows, for instance, software simulations of VLSI devices to provide input to real VLSI hardware while the former VLSI devices are still under development.

As soon as the real device is available, the software simulation can be seamlessly replaced.

Like the monitor, the sequencer is decoupled from the PCI bus using an 8KWord FIFO. The host writes an interleaved sequence of words representing addresses and time delays to the sequencer FIFO. The sequencer then reads these words one at a time from the FIFO and either emits an address–event or waits the indicated number of microseconds. The events generated can be transmitted on any of the four output channels.

Mapping

Events coming from sender chips can be mapped to receiver chips using the PCI–AER board. The use of a transceiver chip combined with this function allows programmable connectivity between neurons on the same chip. Different chips can also be interfaced by defining a connection table among their neurons. The mapper can operate in three different modes:

Pass–through The input address events are simply replicated on the output.

One–to–one The input address events are used as pointers to a look–up table stored in the mapper SRAM. The retrieved content of the table for each input address is the target address on the output.

One–to–many Each input address event generate multiple output events to different targets. The input address is used as a pointer to the first memory location (in the mapper SRAM) of a list of targets.

The mapper has a FIFO which decouples the asynchronous reception of the incoming ad-dress events from the generation of outgoing adad-dress events. Once configured and after the look–up table has been filled with the required mappings, the mapper operates entirely independent of the host personal computer. All of the necessary operations, including table look–up, are performed by one of the FPGAs on the PCI–AER board.