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Figure 4.1: VI Components: front panel on the left, block diagram on the top right, connector pane (highlighted on the bottom right) for creating and using a SubVI inside another VI.

The used graphical language is called “G”, and the development approach is very intuitive because it enables nonprogrammers to build programs by dragging and dropping virtual representations of laboratory equipment. In this way, users can be more familiar with the design and with the basic blocks used in the VI. LabVIEW allows interfacing with different devices, instruments for measurement, vision systems, etc. User can communicate with the hardware by writing direct bus commands or using high-level device-specific drivers that recall the native functions for correctly controlling the connected board. A compiler – included in LabVIEW – provides the latter functionality: the executable machine code is generated in this way, translating the graphical code according to hardware native functions.

The presence of many different and large libraries permits to manage a huge number of functions for signal generation or acquisition, mathematics, statistics, signal conditioning, filtering and other specialized abilities. Another fundamental aspect is the possibility to program multiple tasks that are performed in parallel, for example using two while loops –

one for the plant and the other one for the control algorithm. Some critical aspects are related to the use of LabVIEW for programming: first, only small applications can start in the run-time environment, due to its slowness; second, the G language is non-textual, needing specific additional tools for making comparison or merging code.

For the project in the laboratory of Teoresi Group S.p.A., the adopted versions are LabVIEW 2014, LabVIEW FPGA Module 2014 and LabVIEW Real-Time Module 2014.

Concerning the drivers, on the host the following drivers have been installed: NI CompactRIO 14.5, NI-RIO 14.5, NI FPGA Compile Farm 2014, NI LabVIEW FPGA Xilinx Vivado 2013.4 Tools, NI MAX 18.5, Embedded CAN for RIO Real Time 15.0, NI-XNET 17.5 and NI-VISA 14.0.1. For the compilation of the VIs on the FPGA integrated circuit of SPARK engine control unit and for the automatic generation of the HDL files, the version 2013.4 of Xilinx Vivado has been used.

Figure 4.2: The LabVIEW project tree.

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4.1.1 LabVIEW FPGA

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Regarding LabVIEW FPGA Module, it is used for developing and debugging custom hardware logic that are compiled and then deployed on the NI FPGA hardware. This is a software add-on for LabVIEW that can be used for designing efficiently FPGA-based systems in an integrated development environment, that includes IP libraries, simulator and debugging features. In this way, FPGA VIs can be created for combining the user-defined applications with the board used for running and testing the project.

The principal uses of this module are related to digital protocol communication and to rapid control prototyping hardware-in-the-loop (HIL) validation – the two functionalities have been exploited for developing and then debugging the project. Concerning the HIL, it is a technique used to test complex real-time embedded systems. The effective computing platform – the Alma Automotive SPARK board, used in Teoresi laboratory – runs the controller and it is tested by adding the complexity of the plant, i.e. the mathematical representation of the dynamic system under control – in this case the model of the electric motor is deployed together with the control algorithm on the same hardware. By the combination of the LabVIEW FPGA Module with Xilinx Vivado compiler, from the selected virtual instrument the corresponding hardware description language (HDL) programming file is generated; the latter is then used in the real-time user interface for running the program on the target board – in this case the SPARK engine control unit.

One of the major advantages of this module is the possibility of optimizing the use of the resources that are present in the hardware: the high throughput mathematical blocks allow selecting the width of each fixed-point value. Once defined the number of bits associated to a certain word, it is possible to choose how many bits are reserved to the integer part, in order to determine the maximum range and the delta of a certain number – the delta, called also resolution, is the minimum interval between two consecutive values. Moreover, the fixed-point number can be defined as signed or unsigned.

198 National Instruments, Retrieved from What Is the LabVIEW FPGA Module?: http://www.ni.com/en- gb/shop/electronic-test-instrumentation/add-ons-for-electronic-test-and-instrumentation/what-is-labview-fpga-module.html.

Figure 4.3: High throughput mathematical blocks.

Figure 4.4: Example of FPGA VI, with controllers and indicators connected to high throughput blocks.

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Figure 4.5: Numeric properties of the controller input 1 of previous figure 4.4; here it is possible to choose the word length and the integer word length for establishing the range and the delta.

The first step of the design process is to define the width of each input parameter – fixed or controllable – of the FPGA VI; afterwards, the values are wired to the high throughput mathematical blocks, where for all the operations – addition, subtraction, multiplication, division, reciprocal, square root, sine and cosine, exponential and natural logarithm, etc. – the output number of bits can be manually set or automatically established.

Consequently, by deciding the maximum range and the adequate resolution for each parameter inside the models of controller and plant, it is possible to reduce the amount of unnecessary bits and to optimize the use of the FPGA integrated circuit resources.

Alternatively, the different fixed-step parameters are connected to blocks that are already present in standard LabVIEW environment, to filters, to discrete nonlinear blocks – hysteresis, saturation, signal analysis and processing (as Boolean crossing or zero crossing), trigger, etc. – to other predefined discrete linear systems – discrete normalized integrator, unit delay, discrete transfer function, etc. – or to SubVIs, where all the previous elements can be inserted to process the data.

Figure 4.6: Configuration of the multiplier high throughput block, where the word length and the integer word length can be modified or adapted to the source signals.

Figure 4.7: Discrete linear and nonlinear systems used in LabVIEW FPGA.

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