Synchronous Clock Work-Around
In a synchronous design, simultaneous operation can be avoided by offsetting the read and write clocks by about 1 ns. This is easily achieved by using opposite clock edges for the read and write clocks. In most applications, this requires data resynchronization registers to bring read and write back together in the same clock domain. Figure 4-24 illustrates the concept.
This resynchronization must be done on the input side so that the critical EMPTY flag avoids any latency. The FULL flag is eliminated, as it would not be useful with its 2-clock latency; ALMOSTFULL should be used instead. The connections between the input registers and the FIFO16 must be tightly constrained, as this part of the circuit effectively runs at twice the clock rate.
Figure 4-24: Synchronous Clock Work-Around
DO/DOP
Asynchronous Clock Work-Around
In an asynchronous design, it is inevitable that the two clocks occasionally come very close (<500 ps) to each other, which might cause the problem described above, and no clock delay manipulation can then avoid this problem. For this case, Xilinx has developed a solution that uses additional circuitry to ensure that the FIFO16 never gets into the erred state. This solution operates in a similar manner to the basic FIFO16, and works under all conditions and clock frequencies.
The composite FIFO adds a small LUTFIFO, acting as an asynchronous buffer, that allows the FIFO16 to always operate in synchronous mode. It is necessary to connect the faster clock to the FIFO16 port so that the smaller LUTFIFO never becomes a bottleneck. This constraint leads to two separate designs, as shown in Figure 4-25 and Figure 4-26.
In a case where it is unknown which clock is faster, the “WRCLK faster than RDCLK”
design should be used. This design works for any clock frequency combination, including WRCLK faster than RDCLK, WRCLK identical to and/or phase-shifted with respect to RDCLK, and even if the WRCLK and RDCLK relationship is unknown. When this design is used, and RDCLK is faster than WRCLK in the system, it is possible for the EMPTY flag to assert before the ALMOSTEMPTY flag asserts (note that if the two clocks are nominally the same, this does not occur). This is because the intra-FIFO control logic is running off of WRCLK which is designated as the faster clock, but is really the slower clock in the system.
This does not cause data corruption or incorrect FIFO behavior in any other manner. If this situation exists and this behavior is not acceptable, the CORE Generator FIFO Generator Block RAM work-around described below is recommended.
Some additional logic controls the transfer of data between the two FIFOs for both designs.
Resynchronization of specific signals and handshaking between the two FIFOs results in a small uncertainty of the composite FIFO depth and of the ALMOST_FULL_OFFSET and ALMOST_EMPTY_OFFSET. Refer to Table 4-15 for details.
WRCLK Faster than RDCLK Design
In this case (shown in Figure 4-25), the FIFO WRCLK is connected to WRCLKFIFO16.
RDCLKFIFO16 and WRCLKLUTFIFO are driven from WRCLKbar, which is a 180-degree phase-shifted version of WRCLK. The FIFO RDCLK is connected to RDCLKLUTFIFO.
FIFO16 forms the write interface of the composite FIFO; its read side is clocked by the inverted write clock, which is also used to write into the small LUTFIFO.
Figure 4-25: WRCLK Faster than RDCLK Design DI/DIP
FIFO16 Error Condition and Work-Arounds
R
RDCLK Faster than WRCLK Design
In this case (shown in Figure 4-26), the WRCLK of the FIFO is connected to
WRCLKLUTFIFO. The RDCLKLUTFIFO and WRCLKFIFO16 are driven from RDCLKbar, which is a 180-degree phase-shifted version of RDCLK. The RDCLK of the FIFO is connected to RDCLKFIFO16. The LUTFIFO forms the write interface of the composite FIFO; its read side is clocked by the inverted read clock, which is also used to write into the FIFO16. LUTFIFO flags are combined and synchronized to the write clock to generate the ALMOSTFULL flag.
User-Programmable Flag Settings in the Composite FIFO
The offset ranges for user-programmable ALMOSTEMPTY and ALMOSTFULL flags along with the FIFO capacity are listed in Table 4-15. Since the full capacity of any FIFO is normally not critical, most applications use the ALMOSTFULL flag not only as a warning but also as a signal to stop writing. The ALMOSTEMPTY flag can be used as a warning that the FIFO is approaching EMPTY, but to ensure that the very last entries in the FIFO are read out, reading should be continued until EMPTY is asserted.
When setting the offset ranges in the provided Perl script (refer to Design Files below), use decimal notation.
All values can vary by up to 3 words, depending on the read/write clock rates and the read/write patterns.
Figure 4-26: RDCLK Faster than WRCLK Design DI/DIP
Table 4-15: FIFO Capacity and Effective ALMOSTFULL/ALMOSTEMPTY Flag Offsets
FIFO Type Standard/FWFT
FIFO Depth FIFO16(1) + 15
Clock Style WRCLK > RDCLK RDCLK > WRCLK
ALMOST_FULL_OFFSET AFFIFO16(2) + 15 15
ALMOST_EMPTY_OFFSET AEFIFO16(3) + 15 AEFIFO16(3)
Notes:
1. FIFO16 = Capacity of FIFO16. Refer to Table 4-9, “FIFO Capacity.”
2. AFFIFO16 = Set by user in Perl script. Sets the FIFO16 ALMOST_FULL_OFFSET. Refer to Table 4-13.
3. AEFIFO16 = Set by user in Perl script. Sets the FIFO16 ALMOST_EMPTY_OFFSET. Refer to Table 4-13.
Status Flags
Although the functionality of the status flags on the composite FIFO remain the same, the assertion/deassertion latencies for some of the signals have increased. The assertion values for key signals have remained the same as on the FIFO16 (EMPTY, FULL, ALMOSTEMPTY, ALMOSTFULL, RDERR, and WRERR). Table 4-16 lists the latency values for the status flags. Also note that the values have an uncertainty that is affected by the frequency ratios of the read/write clock, as well as the read/write patterns.
Resource Utilization
The design was implemented using the ISE 8.1i software with default settings for MAP, Place, and Route. The approximate LUT count for a x4 design varies from 55 to 70 LUTs.
For a x9 design, the LUT count varies from 65 to 80 LUTs, and for a x18 design the LUT count varies from 85 to 100 LUTs. The LUT count for a x36 design varies from 125 to 130 LUTs.
Performance Expressed in Maximum Read and/or Write Clock Frequency
The maximum read and/or write clock rate is >500 MHz for all configurations and modes, except for the 512 x 36 configuration with write clock > read clock, where the max frequency for standard mode is 473 MHz, and for FWFT mode it is 488 MHz.
CORE Generator Tool Implementation
The CORE Generator tool should be used to implement this solution. FIFO Generator (v3.2 and above) automatically implements the work-arounds detailed above. The device utilization is detailed in the core data sheet, which can be accessed from:
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/fifo_generator_ds317.pdf Both synchronous and asynchronous FIFOs can be implemented using FIFO Generator block RAM FIFOs available from the CORE Generator tool instead of using the FIFO16 primitives. The block RAM-based implementations are slower than FIFO16-based implementations because the FIFO control logic is implemented in the fabric of the device.
Table 4-16: Clock Cycle Latency for Status Flag Assertion and Deassertion
FIFO Type Standard/FWFT
Clock Style WRCLK > RDCLK RDCLK > WRCLK Clock Cycle Latency Assertion Deassertion Assertion Deassertion
EMPTY 0 10 / 12(1) 0 10 / 11
FULL 1 9 0 9
ALMOSTEMPTY 10 4 1 10
ALMOSTFULL 1 9 11 5
RDERR 0 0 0 0
WRERR 0 0 0 0
Notes:
1. Latency values in bold vary with the ratio between the read/write clock frequencies and read/write pattern. In certain conditions for WRCLK > RDCLK, the ALMOSTEMPTY flag deasserts before the EMPTY flag. This behavior is reflected in simulations, and increasing the ALMOST_EMPTY_OFFSET rectifies the behavior.
FIFO16 Error Condition and Work-Arounds
R
The FIFO16 built-in FIFO configurations from the FIFO Generator Core incurs the same issues described above.
Note: When the script is used, RDCOUNT and WRCOUNT might not be an accurate representation of the number of bits read from and written to the FIFO.
Please review the FIFO Generator Data Sheet for more information:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNa vPick=PRODUCTS&sSecondaryNavPick=Intellectual+Property&key=FIFO_Generator
Software Updates
Starting with ISE 8.1i Service Pack 1 software, the tools automatically detect when a synchronous FIFO16 (RDCLK and WRCLK are connected) has been inserted into a design and issue the following warning:
WARNING:PhysDesignRules:1447 - FIFO16 XLXI_1 has been found to have both RDCLK and WRCLK input pins connected to the same source XLXN_5_BUFGP. Under certain circumstances, the flag behavior to the FIFO may be undeterministic. Please consult the Xilinx website for more details.
To remove this warning, use the CORE Generator FIFO solution or the Synchronous FIFO work-around described above.
Software IP Cores
For information on what software IP cores are affected by this issue, check the following page:
http://www.xilinx.com/ipcenter/coregen/advisories/ip_cores_impacted_by_fifo16_ar2 2462_issue.htm