If the frequencies of WRCLK and RDCLK are low enough, it is possible to synchronize FIFO reads and writes to a third asynchronous fast clock (FASTCLK). The ALMOSTFULL and ALMOSTEMPTY flags are generated in this fast clock domain. These flags are then resynchronized to their respective clocks.
The system described in this solution requires a minimum of 2 and a maximum of 3 fast clock cycles to process a single read or write cycle. To handle back-to-back read or writes, the fast process must complete within one RDCLK or WRCLK period. Thus, the fast clock must be at least three times faster than the faster of WRCLK and RDCLK.
For example, if the fastest RDCLK or WRCLK is 125 MHz, then FASTCLK could be 400 MHz (400/125 = 3.2).
Design Description
The circuit shown in Figure 4-27 is used to generate the “words in FIFO” (WIF) signal. The Up/Down counter must be large enough to hold the maximum number of words in the FIFO; e.g., 10 bits wide if the FIFO depth is 512 words.
The WIF signal is used along with the ALMOST_EMPTY_OFFSET to generate the ALMOST_FULL and ALMOST_EMPTY flags, as shown in Figure 4-28.
Figure 4-27: WIF Signal Generation
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FIFO16 Error Condition and Work-Arounds
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For this design to work, the ALMOST_FULL_OFFSET and ALMOST_EMPTY_OFFSET for the FIFO16 instantiations must be fixed values as shown below:
defparam fifo16.ALMOST_FULL_OFFSET = 12'h001; // do not change this line defparam fifo16.ALMOST_EMPTY_OFFSET = 12'h1FE; // set this to FIFO16 depth - 2 The FIFO16 configurations supported are 4K x 4, 2K x 9, 1K x 18, and 512 x 36.
Two DCMs can be used to generate the FASTCLK as shown in Figure 4-29.
In some cases, only one DCM is needed to generate FASTCLK. The FASTCLK signal should be connected to all instances of module fifo_third_clk_flags in the design.
The output RST signal is connected to all FIFOs and all instances of module
fifo_third_clk_flags. Clock feedback must be specified as NONE on both DCMs (defparam dcm.CLK_FEEDBACK = “NONE”).
Figure 4-28: ALMOSTFULL and ALMOSTEMPTY Signal Generation
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RST
ALMOSTFULL WIF [9:0]
Depth - ALMOST_FULL_OFFSET Depth is 3 less than
depth of the FIFO16;
e.g., 509 rather than
Notes:
• The ALMOSTEMPTY flag is delayed from 1 to 2 RDCLK periods after the condition is detected.
• The ALMOSTFULL flag is delayed from 1 to 2 WRCLK periods after the condition is detected.
• The DCM generating the FASTCLK clock must be locked before the FIFOs can be used. (The STARTUP_WAIT attribute can be used to make sure that the DCMs are locked before the configuration is done.)
• The FASTCLK clock must be continuously available when any of the FIFOs in the system are being used. (Monitor the LOCK signals from all the DCMs to make sure that the FASTCLK clock is running. If LOCK goes Low, the DCMs should be reset.)
• For this design to work properly the maximum words in the FIFO16 must never exceed the nominal maximum - 3; e.g., a 512 word FIFO must never contain more than 509 words.
• This work-around does not currently provide a FULL flag. However, the EMPTY flag from the FIFO16 can be used.
Timing Diagram
The timing diagram for the worst-case write condition is shown in Figure 4-30. The diagram depicts two back-to-back FIFO write cycles. This is a “worst-case” diagram, because the rising edge of WRCLK slightly trails the rising edge of FASTCLK when write enable (WREN) is TRUE. Please refer to Figure 4-27 for signals Wr and WM. Signal Wr is asynchronous to FASTCLK and the leading edge of WM might be metastable. FASTCLK and WRCLK depictions are drawn to scale, relative to each other.
The Read timing is similar to the Write timing shown in Figure 4-30.
Figure 4-30: Write Timing Diagram FASTCLK (400 MHz)
WRCLK (125 MHz)
Wr
UG070_c4_31_020307
WM
Writ WREN (From User)
FIFO16 Error Condition and Work-Arounds
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Resource Utilization
The resources used in implementing the solution described above with a 400 MHz FASTCLK are as follows.
The design was implemented using the ISE 8.1i software with default settings for MAP, Place, and Route. The approximate resource count was 20 LUTs and 24 flip-flops per FIFO.
One DCM is required to generate a 400 MHz clock if a 200 MHz input clock is available.
Two DCMs are needed if only a 100 MHz input clock is available. One extra BUFG was used per device.
Performance
The maximum FASTCLK frequency for each speed grade is Global Clock Tree FMAX, as given in the Virtex-4 Data Sheet. If any back-to-back reads or writes occur, the maximum RDCLK and WRCLK frequency is 1/3 the FASTCLK frequency. If the system design guarantees that there is at least one clock cycle between all reads and all writes, then the maximum RDCLK and WRCLK frequency is 2/3 the FASTCLK frequency. If the system design guarantees that there are at least two clock cycles between all reads and all writes, then the RDCLK and WRCLK frequency can be equal to the FASTCLK frequency.
Design Files
All the necessary files required for the above design are contained in a ZIP archive downloadable from the Xilinx website at:
https://secure.xilinx.com/webreg/clickthrough.do?cid=30163 Open the ZIP archive and extract FIFO16_solution2.zip.