A High Performance 2.4GHz Linear Power Amplifier in
Enhancement-mode GaAs pHEMT Technology
Yut-Hoong Chow and Thomas Chong
Wireless Semiconductor Division, Agilent Technologies (Malaysia)
Bayan Lepas Free Industrial Zone, 11900 Bayan Lepas
Penang, Malaysia
Tel: 60-4-6430611
Fax: 60-4-6423732
Email: yut-hoong_chow@agilent.com, thomas-ck_chong@agilent.com
Abstract — This paper describes the design and
realization of a high performance linear power amplifier in the 2.4GHz band for the IEEE 802.11b/g WLAN (Wireless Local Area Network) and ISM (Industrial Scientific and Medical) applications using a proprietary 0.5um enhancement-mode Pseudomorphic High-Electron-Mobility Transistor (e-pHEMT) technology. The amplifier exhibits a linear power output of 18.5dBm at 5% Error Vector magnitude (EVM) and efficiency of 30% at 2.45GHz at 3.3V supply in a chip-on-board (COB) module. The design also includes an integrated power detector.
I. INTRODUCTION
With the ever-increasing demand for higher data rates in wireless applications, e.g. 802.11 WLAN, designers have an uphill challenge to design linear amplifiers to meet ever more demanding performance goals such as lower current (hence efficiency), higher power output and improved linearity. For example, the 802.11g (2.4GHz) specification enables up to 54Mbps of data rate employing Orthogonal Frequency Division Multiplexing (OFDM) 64-QAM modulation while maintaining a total system EVM of not more than 5.6%. This is a vast difference compared to current 802.11b Wi-Fi standard which provides up to only 11Mbps using Direct Sequence Spread Spectrum (DSSS) and Complementary Code Keying (CCK) modulation.
Significant improvements in this PA linearity-vs-efficiency trade-off have been realized in this respect with Agilent’s proprietary 0.5um GaAs e-pHEMT process [1]. This paper demonstrates that with this technology and optimum device biasing and matching, a high-linearity, high-efficiency PA (power amplifier) can be designed without resorting to fancy linearization techniques. We describe a WLAN PA that achieves 30% efficiency with a linear output power of 18.5dBm for a 54Mbps OFDM-modulated signal using a single 3.3V supply. The PA includes shutdown circuitry as well as on-chip RF power detection functionality. The chip occupies an area of 1.25mm x 0.525mm.
II. GAAS E-PHEMT CHARACTERISTICS
Typical output power vs input power curves for a pHEMT are shown in Fig. 1 below for different bias conditions. Notice both gain expansion and gain compression are possible, depending on the bias used. By a judicious combination of gain expansion and compression in a multi-stage amplifier it is possible to maximize the maximum output power while maintaining minimal bias currents in a Class A-B amplifier. This is accomplished via optimizing pHEMT bias currents and impedance matching circuitry on- and off–chip.
Fig. 1. Gain for different bias currents of a 800um e-pHEMT
III. THE DIE-LEVELAMPLIFIER DESIGN
Figure 2 shows the circuit of the amplifier. For brevity, the bias circuits are not shown. A single shunt inductor provides input match by resonating with the
input capacitance of the 1st stage device (Q1). Inter-stage
match is accomplished by means of a drain inductor at Q1, and a series inductor-capacitor between Q1 and Q2. A drain inductor and output shunt capacitor at Q2, and associated output bond wires and surface-mount capacitors form the output match. Figures 3 and 4 below show the topologies for the bias circuits and power detector respectively. 12 13 14 15 16 17 18 19 20 21 -18 -8 2 12 22 Gain_5mA Gain_10mA Gain_20mA Gain_40mA Gain_80mA
Fig. 2. Die level schematic of the amplifier
Fig. 3. Bias circuit Fig. 4. Power Detector
The bias circuit consists of a dual-pHEMT self-compensating current source which tracks the changes in
each of the devices over temperature so that the voltages at the gates of the amplifying devices remain constant [2]. By selecting the bias currents and device sizes appropriately, it is possible to achieve flat gain versus output power characteristics for very high output powers close to minimal back-off of the power amplifier. In this way, the PA can operate in minimal bias class-B mode while attaining the linearity required. The actual values of the bias currents and device sizes are dependent on the process characteristics. The enhancement-mode pHEMT process used showed high linearity across a wide input power, supply voltage and bias current range. This is important to determine the maximum power output attainable for a given quiescent bias and efficiency. The power detector is made up of a diode-connected pHEMT with current mirror bias as shown in Fig. 4. The output is almost linear with input power in dBm (see also Fig.13.)
Fig. 5. Die level layout
Fig. 6. Simulation schematic of the amplifier with matching components, transmission lines and package parasitics.
R R1 R R2 HP_FET Q1 HP_FET Q2 Det out RFin Bias C C1 C C3 HP_FET Q3 HP_FET Q1 C C2 R R3 Diode DIODE1 R R1 HP_FET Q2 R R2 Vreflect_in Vin Vsupply Vout Vsupply Vdd+ OPTIMIZATION Vsupply Vout_det Goal OptimGoal1 RangeMax[1]=10 RangeMin[1]=5 RangeVar[1]="pin" Weight= Max =30 Min=28 SimInstanceName="HB2" Expr="Power" GOAL Goal OptimGoal2 RangeMax[1]=-4 RangeMin[1]=-5 RangeVar[1]="pin" Weight= Max=21 Min=19 SimInstanceName="HB3" Ex pr="Power" GOAL HarmonicBalance HB3 Step= Stop=-4 Start=-5 SweepVar="pin" UseKrylov=auto Oversample[1]=4 FundOv ersample=4 Order[1]=9 Freq[1]=rf_freq GHz HARMONIC BALANCE HarmonicBalance HB2 Step= Stop=10 Start=5 SweepVar="pin" Us eKrylov=auto Ov ersample[1]=4 FundOversample=4 Order[1]=9 Freq[1]=rf_freq GHz HARMONIC BALANCE Optim Optim1 SaveCurrentEF=no UseAllGoals=yes OptVar[1]= UseAllOptVars=yes SaveAllIterations=y es SaveNominal=yes UpdateDataset=yes SaveOptimVars =yes SaveGoals=yes SaveSolns=yes Seed= SetBestValues=yes NormalizeGoals=no FinalAnalysis="None" Status Level=4 DesiredError=0.0 P=2 MaxIters=25 ErrorForm=L2 OptimType=Random OPT IM MLOC TL16 L=178 um W=178 um Subst="MSub1" PCTRACE TL96 L=33 um W=4 mil Subst="PCSub1" MCURVE2 Curve28 Radius=4 mil Angle=90 W=4 mil Subst="MSub1" Circ ulator CIR1 Isolat=100. dB VSWR1=1. Los s1=0. dB R R25 R=50 Ohm P_1Tone PORT4 Freq=rf_freq GHz P=polar(dbmtow(pin),0) Z=50 Ohm Num=4 CPWG CPW1 L=678 mil G=12.8 mil W=18 mil Subst="CPWSub1" INDQ L25 Q=20.0 L=3.3 nH VIAFC V25 T=25 um H=15 mil D=200 um PCTRACE TL65 L=172 um W=356 um Subst="PCSub1" PCTRACE TL8 L=449 um W=356 um Subst="PCSub1" BONDW1 WIRESET16 W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 PCTRACE TL93 L=401 um W=4 mil Subst="PCSub1" PCTRACE TL38 L=211 mil W=4 mil Subst="PCSub1" MLIN TL99 L=166 um W=4 mil Subst="MSub1" MLIN TL98 L=166 um W=4 mil Subst="MSub1" PCSUB1 PCSub1 TanD=0 Sigma=0 W=1000 mil T=25 um Hl=0 mil Hu=1000.0 mil Cond=5.8E+7 Er=3.9 H[1]=15 mil PCSub1 Harmonic Balance HB1 Step=0.5 Stop=15 Start=-20 SweepVar="pin" UseKrylov =auto Oversample[1]=4 FundOversample=4 Order[1]=9 Freq[1]=rf_freq GHz HARMONIC BALANCE BONDW2 WIRESET14 W2_Shape="Shape1" W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 2 BONDW2 WIRESET15 W2_Shape="Shape1" W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 2 I_Probe Ibias3 MLOC TL48 L=279 um W=330 um Subst="MSub1" MLOC TL49 L=279 um W=330 um Subst="MSub1" VIAFC V23 T=25 um H=15 mil D=200 um C C4 C=100 pF MLOC TL67 L=569 um W=511 um Subst="MSub2" CPWG CPW2 L=678 mil G=12.8 mil W=18 mil Subst="CPWSub1" R R6 R=50 Ohm C C31 C=1 pF VIAFC V21 T=25 um H=15 mil D=200 um PCTRACE TL92 L=1315 um W=645 um Subst="PCSub1" PCTRACE TL44 L=170 um W=4 mil Subst="PCSub1" VIAFC V18 T=25 um H=15 mil D=200 um MLOC TL66 L=569 um W=511 um Subst="MSub2" I_Probe Imain2 V_DC SRC4 Vdc=Vdd V I_Probe Itotal MLOC TL42 L=279 um W=330 um Subst="MSub1" PCTRACE TL55 L=161 um W=4 mil Subst="PCSub1" MLOC TL75 L=254 um W=178 um Subst="MSub1" MCLIN CLin8 L=493 um S=4 mil W=4 mil Subst="MSub1" MLOC TL77 L=279 um W=330 um Subst="MSub1" MCURVE2 Curve29 Radius=4 mil Angle=90 W=4 mil Subst="MSub1" INDQ L28 Q=20.0 L=1.0 nH MCURVE2 Curve30 Radius=4 mil Angle=90 W=4 mil Subst="MSub1" CPWSUB CPWSub2 Rough=0 mil TanD=0 T=1 mil Cond=5.8e7 Mur=1 Er=3.9 H=15 mil CPWSub CPWSUB CPWSub1 Rough=0 mil TanD=0 T=1 mil Cond=5.8e7 Mur=1 Er=4.3 H=10 mil CPWSub MSUB MSub1 Rough=0 mil TanD=0 T=1 mil Hu=1000 mil Cond=5.8e7 Mur=1 Er=3.9 H=15 mil MSub MSUB MSub2 Rough=0 mil TanD=0 T=1 mil Hu=1000 mil Cond=5.8e7 Mur=1 Er=4.3 H=10 mil MSub BONDW_Shape Shape1 FlipX=1 StopH=0 um Stretch=0 um Tilt=0.6 mil MaxH=9.5 mil StartH=4.5 mil Gap=19 mil Rw=0.5 mil MeasEqn Meas1 InputRetLoss =HB.Vreflect_in[1]/HB.Vtransmit_in[1] PAE=Voutrms _watt/(Vdd*(HB.Itotal.i[0])) Voutrms_watt=((10**((dbm(HB.Vout[1]))/10))/1000) Power=dBm(HB.Vout[1]) Powergain=(dBm(HB.Vout[1]))-(pin) Eq n M e a s VAR VAR_sources pin=0 rf_freq=2.452 Vdd=3.3 Eq nVa r DC DC1 Step= Stop= Start= SweepVar= DC VIAFC V26 T=25 um H=15 mil D=200 um C C26 C=1.2 pF MLOC TL85 L=279 um W=330 um Subst="MSub1" MLOC TL82 L=279 um W=330 um Subst="MSub1" MLOC TL83 L=279 um W=330 um Subst="MSub1" MLOC TL43 L=279 um W=330 um Subst="MSub1" PCTRACE TL63 L=294 um W=236 um Subst="PCSub1" PCTRACE TL81 L=221 um W=4 mil Subst="PCSub1" PCTRACE TL87 L=330 um W=279 um Subst="PCSub1" MLOC TL24 L=7 mil W=7 mil Subst="MSub1" MLOC TL11 L=569 um W=511 um Subst="MSub2" VIAFC V22 T=25 um H=15 mil D=200 um PCTRACE TL84 L=221 um W=151 um Subst="PCSub1" C C30 C=100 pF MLOC TL88 L=279 um W=330 um Subst="MSub1" MLOC TL72 L=254 um W=178 um Subst="MSub1" MLOC TL17 L=254 um W=178 um Subst="MSub1" MCURVE2 Curve32 Radius=4 mil Angle=90 W=4 mil Subst="MSub1" MLOC TL68 L=279 um W=330 um Subst="MSub2" I_Probe Imain1 C C28 C=100 pF chow_dot11g_die_ver0 X2 S_D RF_out Det Vdd2 Vdd1 RF_in BONDW2 WIRESET11 W2_Shape="Shape1" W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 2 BONDW2 WIRESET7 W2_Shape="Shape1" W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 2 R R26 R=25 kOhm BONDW1 WIRESET10 W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 BONDW2 WIRESET13 W2_Shape="Shape1" W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 2 MCURVE2 Curve27 Radius=4 mil Angle=90 W=4 mil Subst="MSub1" BONDW2 WIRESET12 W2_Shape="Shape1" W1_Shape="Shape1" Cond=4.1e7 S Radw=0.5 mil 1 2 PCTRACE TL29 L=407 um W=246 um Subst="PCSub1"
Figure 5 shows the layout of the die in Agilent’s proprietary 0.5um enhancement-mode GaAs-AlGaAs pHEMT process. The die measures 1.25mm x 0.525mm.
IV.THE MODULE AND PACKAGING DESIGN
The Agilent Technologies Advanced Design System (ADS) simulator was used extensively to predict and optimize the performance when the die is packaged in a COB module. The simulation schematic was carefully constructed to include all the board traces, wirebond pads, component pads, vias and module solder pads. Agilent’s Root Model [3] was used for the active devices. The simulation schematic is shown in Fig. 6 and the swept power, gain and current results are shown in Fig.7. Using the same values as that obtained from simulation, good correlation was noted for gain and power (within 1dB). For the current drain, good correlation was obtained in the trend beyond the 18dBm power output level, but not in the low level (linear) region. Nevertheless, the simulation exercise was very important in determining the matching topology and component values, thus reducing cycle time tremendously. The printed circuit board (PCB) layout is shown in Fig. 8.
Fig. 7. Simulation results.
Fig. 8. PCB layout of the amplifier showing MMIC, transmission lines and matching components.
Fig. 9. Module mounted on evaluation board
The module PCB is a 0.015” thick Getek® material with a dielectric constant of 3.9. The dimensions are
5x6x1.1mm3. (Note: The module is actually bigger than
it needed to be as it was designed to accommodate two circuits, but only one of the circuits is discussed here). The choice of COB over other packaging options such as plastic leadless chip carrier (PLCC) or ceramic LCC is so that the matching surface mount components can be integrated, and for cost reasons. Figure 9 shows the final encapsulated COB module mounted on a polyimide evaluation board.
V.MEASURED PERFORMANCE
The module was measured for its performance using standard techniques. For EVM measurements the OFDM signal source is an Agilent ESG 4438C Vector Signal Generator, and the analysis is performed by an Agilent E4440A Performance Spectrum Analyzer (PSA) (E444XA/AU option K70) in conjunction with Agilent 89611A Vector Signal Analyzer (VSA) 70MHz IF module. The supply voltage is 3.3V.
Results: Frequency: 2.452GHz Gain: 20.6dB Psat/Current: 25.5dBm/203mA @5.0%EVM,Pout/Current/PAE: 18.5dBm/70mA/30% @3.0%EVM,Pout/Current/PAE: 17.4dBm/64mA/26% OIP3: 24dBm 2nd /3rd /4th harmonics: 34/44/68dBc
Input Return Loss: -19dB
Output Return Loss: -8dB
Figures 10 and 11 show the swept-power measurements of the module. In Fig. 10, notice the flat gain, close to 21dB, up to a very high output power level (22dBm). The shape of the curves mirror that obtained through simulation (see Fig.7).
Fig.10. Swept power measurement of the PA module
CW Pout, Gain & Current vs Pin @ 2.452GHz
10 12 14 16 18 20 22 24 26 28 30 -10 -8 -6 -4 -2 0 2 4 6 8 10 Pin (dBm) P o ut ,G a in in dB m ,dB 50 70 90 110 130 150 170 190 210 230 250 Cu rr e n t ( m A)
Pout(dBm) Gain (dB) Current (mA)
Fig. 11. EVM and current vs Pout plot of the PA module
Figure 11 show typical EVM and current vs Pout curves. Typically, at 3% EVM, the Pout is 17.0 to 18dBm. At 5% EVM, the Pout is 18.5 to 19.5dBm with a 70 to 80mA current drain. Figure 12 below shows the modulated signal measured using the WLAN analyzer. Finally, the power detector output versus power is shown in Fig. 13 which shows a high degree of linearity.
Fig. 12. Plot of PA module output at Pout=+18dBm @EVM=3% with 802.11g 54Mbps 64-QAM OFDM
modulation
Fig. 13. Plot of detector output vs output power
VI. CONCLUSION
The design and measured performance of a high-linearity, high-efficiency power amplifier at 2.45GHz employing Agilent’s proprietary GaAs e-pHEMT fabrication technology has been presented. The power amplifier was designed primarily for the IEEE 802.11g WLAN standard employing OFDM modulation at 54Mbps. With internal matching, an easy-to-use module has been realized giving 21dB gain with a 2-stage topology. An unprecedented efficiency of 30% at a linear output of 18.5dBm, at 5% EVM, has been demonstrated. This level of performance holds good potential for current-constrained products like WLAN NIC cards, and wireless-enabled Personal Digital Assistants (PDA).
ACKNOWLEDGEMENT
We would like to thank our managers, Lau Yat-Por and Ho King-Pieng, for their leadership in this project. Thanks are also due to Henrik Morkner and his group for their valuable technical advice. Thanks are also due to Lee Hang Kiong for helping with data measurement.
REFERENCES
[1] Wu et al, “An Enhancement-Mode pHEMT for Single- Supply Power Amplifiers”, HP Journal, Feb 1998, pp39- 51.
[2] P. R. Gray et al, “ Analysis and Design of Analog Integrated Circuits,” 4ed, pp 308-309, Wiley, 2001. [3] D E Root, S Fan, J Meyer, “Technology-independent large-signal non-quasi-static FET models by direct construction from automatically characterized device data”, 21st EuMC, 927-932 (1991)
EVM & Current vs Modulated Pout
0 1 2 3 4 5 6 7 8 9 10 11 12 -1 .0 0.0 1.0 2.0 3.0 04. 4.9 6.1 7.0 7.9 8.9 10 .0 11 .0 12 .0 13 .0 14 .0 15 .0 15 .9 16 .9 17 .4 17 .9 18 .5 19 .0 19 .5 Modulated Pout (dBm) EV M (% ) 30 35 40 45 50 55 60 65 70 75 80 Cu rr en t (m A) EVM Current Detector @ 2.452GHz 0 0.5 1 1.5 2 2.5 3 3.5 4 15 16 17 18 19 20 21 22 23 24 25 26 Pout (dBm) Vd et ( V)
