Paper submitted for presentation at PIXEL 2005 Corresponding Author:
International Workshop on Semiconductor Pixel Detector Giuliana Rizzo for Particles and Imaging, Bonn (Germany), September 5-8, 2005. tel. +39 050 2214274
Oral Presentation Preferred. email: [email protected]
A Novel Monolithic Active Pixel Detector in 0.13 µm Triple Well CMOS Technology with Pixel Level Analog Processing
S. Bettarini1, L. Bosisio2, G. Calderini1, R. Cenci1, F. Forti1, M.A. Giorgi1, M. Manghisoni 3, F. Morsani1, L. Ratti4, V. Re3, G. Rizzo1, V. Speziali4, G. Traversi3,
1INFN-Pisa and Universit`a di Pisa,2INFN-Trieste and Universit`a di Trieste,
3INFN-Pavia and Universit`a di Bergamo,4INFN-Pavia and Universit`a di Pavia,
Vertex Detectors for future high energy physics experiments will need to fulfill more stringent re- quirements with respect to the presently operating tracking detectors. The choice of silicon detectors is mandatory to reach the high spatial resolution needed to perform optimal momentum and vertex resolution. At the same time the high occupancy, due to machine background, or the high granular- ity required by the track density in jets, force the adoption of pixel detectors for innermost tracking layers. Furthermore in experiments suited for the SuperBfactory or the Linear Collider, the relatively low particle momenta (1 GeV) set another stringent requirement on the material budget to avoid spa- tial resolution deterioration due to multiple scattering. For all these reasons the application of CMOS monolithic active pixel sensors (MAPS) as tracking detectors for future experiments has been widely investigated in the last few years.
These devices offer several potential advantages with respect to hybrid pixel or charge-coupled devices. The integration of the sensor and the readout electronics on the same substrate greatly reduces the detector material budget, reducing multiple scattering and improving spatial resolution, while at the same time simplifying detector assembly. The use of a standard deep submicron CMOS tecnology and the integration of readout electronics at pixel level result in high readout speed, low power consumption, and low fabrication costs.
The CMOS MAPS, developed by other groups for this purpose, employ a low resistivity p-type wafer with a thin (10-20 µm) p-type epitaxial layer. The charge released by MIPs in the epi layer is collected via diffusion by the n-type well and subsequently read out via a source follower and sent to peripheral electronics. Since the collecting electrode is used for charge-to-voltage conversion, its size needs to be kept to a mininum, limiting the typical dimension of the sensitive element to a few microns and causing connectivity and readout speed problems for large area detectors.
To overcome this limitation and increase the sensitive element area, we designed and fabricated a novel CMOS MAPS pixel, exploiting ST 0.13 µm triple well CMOS technology (HCMOS9GP) to integrate at the pixel level the analog readout electronics, which includes a charge preamplifier, a shaper, a discriminator and some elementary logic functionality. With the use of a charge preamplifier as a front-end element the charge sensitivity is independent of the capacitance of the charge collecting electrode, whose area can thus be extended.
The concept of our MAPS sensor is illustrated in Fig. 1. In triple well CMOS processes an n-type well with a deep junction is available to ensure a better insulation of the analog n-channel devices from the substrate and the neighboring digital devices. In our design the deep n-type well is used as charge collecting electrode, and its area can cover a large fraction of the elementary cell. This is possible since the n-channel devices of the analog readout electronics are located in the p-type well, physically overlapped with the area of the sensitive element. The area of the other n-type well (containing the p-channel devices for the analog and the digital part) is minimized, since they could subtract charge to the deep n-well collecting electrode, thereby degrading charge collection efficiency. The deep n-well is connected to the gate of the preamplifier input device. Due to its relatively high doping concentration (with respect to material used for radiation detectors) the epitaxial layer is not significantly depleted and the charge is collected mainly by diffusion. A detailed simulation of the pixel sensor performed with
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Figure 1: Cross section of the monolithic pixel detector with pixel level processing
the ISE-TCAD package indicates a typical collection time of 30 ns. Since the thickness of the active element is only about 10 microns (the p-epitaxial layer) and the expected signal is only about 1000 e−, particular care has been taken to design a very low noise charge preamplifier to mantain acceptable values for the S/N ratio.
The charge preamplifier is followed by an RC-CR shaper with programmable peaking time (0.5-1-2 µs). The signal at the shaper output is compared to a threshold voltage by a discriminator. A latch is used to store the digital information of the comparator output and can be externally reset.
A test chip containing single pixel elements with different sizes of the collecting electrode, between 400 and 2000 µm2, has been fabricated and is currently under test. Measurements of gain and noise of the preamplifier channel show a gain of about 600 mV/fC (Fig.2-left) and an equivalent noise charge of about 80 e- rms with a detector capacitance of 100 fF, in good agreement with simulation. Measurements
Figure 2: Left - Charge sensitivity of the processing channel (stand alone channel, without the deep n-well connected), Right - Signal deposited on the pixel by infrared light pulses from a laser (shaper peaking time 2µs).
of the signal generated by infrared light pulses from a laser (Fig.2-right) demonstrate the functionality of the system (pixel sensor + readout electronics). The first signals with a beta source (Sr 90) have been observed and further measurements of the response to ionizing radiation are on the way. The paper will discuss in detail the performance of the system, including detailed response to infrared light pulses and ionizing radiation.
We will also present our plans to optimize these devices and implement them in a matrix with a readout architecture suitable to be used in a trigger system based on associative memories. We plan to use these devices along with thin silicon strip detectors in a test thin silicon tracker that we are developing.
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