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Table of Contents

INTRODUCTION ...4

1

THE FF-LYNX PROJECT ...6

1.1

Genesis of the project...6

1.1.1 High Energy Physics experiments ... 6

1.1.2 The Large Hadron Collider at CERN and its experiments ... 10

1.1.2.1 CMS ... 11

1.1.2.2 ATLAS... 14

1.1.3 Requirements of DAQ/TTC systems for HEP experiments ... 15

1.2

Purposes of the project...18

1.3

Methodology and design flow ...20

2

THE FF-LYNX PROTOCOL...23

2.1

General characteristics ...23

2.2

The THS channel ...25

2.2.1 TRG and HDR scheduling... 26

2.2.2 Synchronization... 27

2.2.3 The THS encoding... 29

2.2.3.1 Elements of coding theory ... 29

2.2.3.2 TRG/HDR/SYN encoding ... 34

2.2.3.3 TRG/HDR balanced encoding ... 37

2.3

The FF-LYNX frame ...38

2.3.1 The Frame Descriptor... 40

2.3.1.1 The H(12,7) encoding ... 40

2.3.2 Payload and label... 46

2.3.3 Trigger data frames... 47

2.4

Future protocol versions...48

2.5

Protocol validation ...50

2.5.1 Synchronization algorithm selection ... 52

3

FF-LYNX INTERFACES...56

3.1

FF_TX...56

3.1.1 External specifications... 56 3.1.2 Internal architecture... 59

3.2

FF_RX...61

3.2.1 External specifications... 61 3.2.2 Internal architecture... 65

4

VHDL MODELING AND SIMULATION...67

4.1

General description of the model ...68

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4.1.2 Counter_N ... 70 4.1.3 ffd ... 70 4.1.4 Register_N... 71 4.1.5 Shift Registers ... 72

4.2

FF_TX...73

4.2.1 TX Buffer ... 73 4.2.2 sel_THS Generator TX... 74 4.2.3 Frame Builder... 76 4.2.3.1 FB_Control1 ... 78 4.2.3.2 FB_Control2 ... 82 4.2.3.3 FD Encoder ... 86 4.2.4 THS Scheduler... 86 4.2.5 Serializer... 90 4.2.5.1 THS load controller... 93 4.2.5.2 THS command selector... 95 4.2.5.3 Pulse Shrinker ... 95 4.2.5.4 Ser_Control ... 97

4.3

FF_RX...104

4.3.1 Deserializer... 104 4.3.1.1 Des_control ... 108 4.3.2 THS Detector... 111 4.3.3 Synchronizer... 112 4.3.3.1 Clock Splitter ... 115 4.3.3.2 Sync Counter... 115 4.3.4 Frame Analyser... 118 4.3.4.1 FA_Control1 ... 120 4.3.4.2 FA_Control2 ... 124 4.3.4.3 FD Decoder... 126 4.3.5 sel_THS Generator RX... 127 4.3.6 TRG stretcher ... 128 4.3.7 RX Buffer ... 130

4.4

Test bench ...131

4.4.1 TX Host Emulator ... 132 4.4.2 RX Host Emulator ... 134 4.4.3 Comparison of files ... 135 4.4.4 Test results... 136

5

FPGA PROTOTYPING...138

5.1

FF-LYNX Emulator...138

5.2

Development board...139

5.3

FPGA synthesis of FF-LYNX interfaces...140

CONCLUSIONS AND FUTURE DEVELOPMENTS...142

BIBLIOGRAPHY...146

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