1
Development on Deep N Well MAPS in a 130 nm CMOS Technology and Beam Test Results on a 4k-Pixel Matrix with Digital Sparsified Readout
G. Rizzo
a,C. Avanzini
a, G. Batignani
a, S. Bettarini
a, F. Bosi
a, G. Calderini
a, M. Ceccanti
a, R. Cenci
a, A. Cervelli
a, M. Dell’Orso
a, F. Forti
a, P. Giannetti
a, M.A. Giorgi
a, A.Lusiani
a, S. Gregucci
a, P. Mammini
a, G. Marchiori
a, M. Massa
a, F. Morsani
a, N. Neri
a, E. Paoloni
a, J. Walsh
a, E. Yurtsev
a, C. Andreoli
c, L. Gaioni
c, E. Pozzati
c, L. Ratti
c, V. Speziali
c, M. Manghisoni
d, V. Re
d, G. Traversi
d, M. Bomben
e, L. Bosisio
e, P. Cristaudo
e,
G. Giacomini
e, L. Lanceri
e, I. Rachevskaia
e, L. Vitale
e, G.F. Dalla Betta
f, G. Soncini
f, G. Fontana
f, L. Pancheri
f, G. Verzellesi
g, D. Gamba
h, G. Giraudo
h, P. Mereu
h, M. Bruschi
i,R. Di Sipio
i,B. Giacobbe
iA. Gabrielli
i, F. Giorgi
i,C. Sbarra
i, N. Semprini
i, R. Spighi
i, S. Valentinetti
i, M. Villa
i, A. Zoccoli
iAbstract—We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep nwell (DNW) MAPS sensor, by exploiting the triple well option of a CMOS 0.13 µm process. The optimization of the collecting electrode geometry and the re-design of the analog cir- cuit to decrease the power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1”
and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel noise equivalent charge (ENC) of 36e- and 46 e- have been measured for the two versions of the front-end implemented toghether with Signal- to-Noise ratios for MIPs between 20 and 30. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timestamp informations for the hits has been im- plemented in the prototype chip “APSEL4D”, having 4096 pixels.
The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data- driven and scalable to chip larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successfull beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.
Index Terms—Monolithic active pixel sensors, MAPS, CMOS pixels, charged particle tracking.
Manuscript received November 14, 2008. This work was supported by the Italian Ministry for Education, University and Research and the Istituto Nazionale di Fisica Nucleare.
(a) Universit`a degli Studi di Pisa and INFN-Pisa, Italy (e-mail: giu- [email protected]).
(b) Scuola Normale Superiore, Pisa-Italy.
(c)Universit`a degli Studi di Pavia and INFN-Pavia, Italy.
(d) Universit`a degli Studi di Bergamo and INFN-Pavia, Italy.
(e)Universit`a degli Studi di Trieste and INFN-Trieste, Italy.
(f )Universit`a degli Studi di Trento and INFN-Padova, Italy.
(g) Universit`a degli Studi di Modena and Reggio and INFN-Padova, Italy.
(h)Universit`a degli Studi di Torino and INFN-Torino, Italy.
(i)Universit`a degli Studi di Bologna and INFN-Bologna, Italy.
I. INTRODUCTION
V
ERTEX detectors for experiments at future colliders such as the SuperB Factory or the International Linear Collider will need to fulfill very stringent requirements on position resolution, readout speed, material budget and radia- tion tolerance. New CMOS Monolithic Active Pixel Sensors (MAPS) are a promising candidate for such applications [1]:they incorporate on the same substrate the readout electronics and a very thin sensor, with the possibility to reduce the detector material budget down to 50µm. The MAPS device uses an n-well/p-epitaxial diode to collect, through thermal diffusion, the charge generated by the impinging particle in the thin epitaxial layer underneath the readout electronics. In this technology the signal collected is only few hundreds of electrons, for typical p-epitaxial thickness of about 10µm.
CMOS MAPS prototypes have been developed by several groups over the last few years [2], [3], [4], [5]. These designs follow the very simple readout scheme already adopted for imaging applications, based on the use of only three transistors on the pixel cell (3T), with a sequential readout. In this baseline MAPS the n-well collecting electrode should be as small as possible (typically only a few microns squared), since charge to voltage conversion is performed using the sensor capacitance. The use of PMOS in additional n-well regions inside the pixel cell, needed to develop a more complex in- pixel signal processing, is forbidden with this design approach.
These “competitive” n-wells could in fact subtract charge from the main collecting n-well electrode causing an efficiency loss. Although these prototypes have shown excellent tracking performance, their readout speed, limited by the sequential processing, is one of their major limitations for future appli- cations.
A different approach to the design of CMOS MAPS has recently been proposed by the SLIM5 Collaboration [6] to improve the readout speed potential of these devices and at the same time to increase the sensitive element area. By exploiting the triple well option of CMOS commercial processes, a full signal processing chain has been implemented at the pixel
Fig. 1. Cross section of the triple well active pixel sensor with in-pixel signal processing.
level (charge preamplifier, shaper, discriminator and a latch), building a monolithic pixel with a readout scheme easily compatible with data sparsification.
The concept of the new design is illustrated in Fig.1: the deep n-well (DNW) of the triple well process is used as a charge collecting electrode and also contains part of the front- end stage. This is physically overlapped with the area of the sensitive element, allowing a more complex in-pixel readout electronics. Furthermore, since the voltage gain is now deter- mined by the feedback capacitance of the charge preamplifier, the size of the collecting electrode can be increased (up to about 900 µm2 in a pixel cell with a 50 µm pitch). Thus it is possible to include in the pixel cell some small competitive n-well regions, crucials to develop the logic for the sparsified readout, still keeping the fill factor of the sensor at the level of 90%.
II. THEAPSELCHIPS
Several prototype chips (the “APSEL” series) have been realized with the STMicroelectronics, 130 nm triple well technology, including single pixel cells and small pixel matrix with a simple sequential readout. Results on these prototypes [8] [9] [10], proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr.
Further developments on this design approach brought to the design of a third “generation” of the APSEL pixels and to the APSEL4D chip, a first MAPS matrix with sparsification at the pixel level that also provides the timestamp information for the hits.
For the APSEL3 pixel a substantial redesign of the front-end and the sensor has been carried out to improve the Signal-to Noise ratio and to reduce the power consumption. The total sensor capacitance has been reduced significantly by using for the new collecting electrode a combination of a deep n-well region and a standard n-well area, having a smaller specific capacitance. With the large reduction of the total capacitance, from 500 fF to 300 fF, a better balance between noise and power consumption has been achieved: the power dissipation has been lowered by a factor two (down to 30 µW/ch) reducing also the pixel noise equivalent charge by
Fig. 2. Cluster signal of the 3x3 pixel matrix for MIPs for a90Sr source.
10%-30%. Furthermore to cure the digital cross-talk effects present in the previous APSEL series, in the new pixel layout one of the six metal layers, available in the 130 nm ST process, has been used as a shield between the sensor and the digital lines.
In the APSEL3 chips two different versions for the shaper have been implemented, adopting as feedback either a transconductor (APSEL3T1) or a current mirror circuit (APSEL3T2).
The characterization of the APSEL3 chips with radioactive sources confirmed the expected improvements: for the two front-end versions Signal-to-Noise ratios between 20 and 30 have been measured for MIP from a beta source. An example of the response of the APSEL3T1 chips to electrons from90Sr is shown in Fig. 2: the cluster signal has been fitted with a Landau distribution with a most probable value of 128 mV, corresponding to a Signal-to-Noise of 24 (average pixel noise
= 5.3 mV).
The absolute gain calibration has been measured with the 5.9 keV line from a 55Fe source. With this calibration the average cluster signal for a MIP corresponds to about 1000 e- (MPV), while the average pixel noise equivalent charge (ENC) in the two versions of the front-end is respectively of 46 e- and 36 e-.
III. THEAPSEL4DMATRIX
For several future applications it is crucial to develop a fast readout for the MAPS matrix. Based on the new DNW pixel design a dedicated readout architecture to perform on- chip data sparsification has been implemented. The readout logic also provides the timestamp information for the hits.
The architecture is data-driven to permit the use of the tracker information to generate a first level trigger.
The key issues in this development are 1) to minimize log- ical blocks with PMOS inside the active area, to preserve the collection efficiency, and 2) to reduce to a minimum the digital lines crossing the sensor area, to allow the readout scalability to larger matrices and to reduce the residual crosstalk effects.
With these criteria a readout logic in the periphery of the
Fig. 3. Schematic concept of the architecture for MAPS matrix readout.
Fig. 4. The APSEL4D chip bonded to the chip carrier.
matrix has been developed, as schematically shown in Fig.3.
To minimize the digital lines crossing the active area the matrix is organized in MacroPixels (MP) with 4x4 pixels. Each MP has only two private lines for point to point connection to the readout logic: one line is used to comunicate to the readout that the MP has got hits, while the second private line is used to freeze the MP until it has been read out. When the matrix has some hits the readout logic sweeps the matrix by searching for fired MPs, then it enables the readout of an entire column of pixels using a shared vertical line. Common horizonthal lines are shared among pixels in the same row to bring data from the pixels to the periphery readout logic where the association with the prorper timestamp is performed before sending the formatted data word to the output bus.
The APSEL4D chip, shown in Fig. 4, has been realized following the concept described earlier. It includes a 4096 pixel matrix, based on the APSEL3T1 cell (transconductor in the shaper), with a data driven sparsified readout in the chip periphery. Fig. 4. It includes a 4096 pixel matrix The chip has been realized with a mixed mode design approach.
While the pixel matrix has a full custom design and layout, the periphery readout architecture has been synthetized in standard cell starting from a VHDL model; automatic place-and-route tools have been used for the layout of the readout logic [11].
The APSEL4D matrix has been fully characterized showing very uniform performance over the twenty chips measured.
The basic functionality of the readout has been tested, with a readout clock up to 50 MHz, using a dummy digital matrix
Fig. 5. Noise distribution for the 4096 pixels of the apsel4D matrix
.
implemented for this purpose at the chip periphery, and it works as expected even with 100 % occupancy.
APSEL4D - Fe55 - allpixels
Fig. 6. Response of the APSEL4D matrxi to55Fe source: differential rate vs discriminator threshold. The 5.9 keV calibration peak shown is obtained summing up all the 4096 pixels of the matrix.
Noise measurements and evaluation of the threshold dis- persion have been performed on the 32x128 pixel matrix, measuring the hit rate as a function of the discriminator threshold. With a fit to the turn-on curve we reported a pixel average ENC of about 75 e- (10.5 mV) with 20 % dispersion inside the matrix, and a thresold dispersion of about 60 e- (8 mV). These figures were obtained with a readout clock of 20 MHz. A typical noise distribution for the 4096 pixels of the matrix is shown in Fig. 5.
The absolute gain calibration of the APSEL4D matrix has been performed using the 5.9 keV line from a 55Fe source.
Since no analog information is available, the photo-peak is reconstructed from the differential rate as a funtion of the
discriminator threshold. With this technique an average gain of 890 mV/fC has been measured with a tipical dispersion of about 6 % inside the matrix. The 55Fe calibration peak is shown in Fig. 6, summing up the contribution of all the pixels of a matrix.
Measurements performed on dedicated test structures indi- cate that the metal shield inserted in the new pixel layout design is effective in reducing at the level of the noise the cross-talk due to the capacitive coupling between the digital lines and the sensor. Neverthless new effects of digital cross- talk have been observed in the APSEL4D,apparently correlated with the readout activity, and still under investigation. A new version of the chip will be submitted by the end of 2009 with more diagnostic features and modifications introduced to reduce some potential sources of the new cross-talk effects.
By reducing the digital voltage (from 1.2V to 1 V) this effect has been reduced to an acceptable level, still beeing able to operate efficiently the matrix and the readout. Results shown for the APSEL4D have been obtained with the reduced digital voltage.
IV. BEAMTESTPRELIMINARYRESULTS
In September 2008 the SLIM5 experiment has performed a successfull beam test of a “demonstrator” for a low material budget silicon tracker at the T9 station of the CERN PS, where hadrons of momentum of 12 GeV/c were available.
The main goal of this test was to measure the efficiency and the resolution of the DNW MAPS sensor in APSEL4D.
The other device under measurement were double sided high resistivity silicon detectors, 200 µm thick with short strips, read out by the FSRR2 chip (the other option for the SuperB layer0 silicon tracker [12]). The device under test were po- sitioned in the center of a reference telescope, made of four double sided silicon strip detectors also read out by FSSR2 chips. The setup of the beam test is schematically shown in Fig. 7. The data driven approach of the readout chips has been used to demonstrate for the first time the possibility to build a level1 trigger system based on an Associative Memory board connected to the DAQ system [13].
Fig. 7. The SLIM5 Testbeam Setup.
During the beam test, with a DAQ rate of about 30 kHz, about 90 millions of events were written on disk with different trigger configurations. The data analysis is still ongoing but
preliminary results on MAPS hit efficiency and resolution confirmed the DNW device is working well.
Fig. 8. Residual distribution (y coordinate) after alignment. Real hits contribute to the peak while fake noise hit are uniformly distributed in the tails.
Tracks reconstructed with the reference telescope were used to extract the APSEL4D hit efficiency with the following technique. For each track, whose extrapolated impact point is inside the MAPS fiducial region, the distance between the expected and the measured hit (residual) is calculated. In the residual distribution, whose an example is shown in Fig. 8, real hits tend to peak while fake noise hits are uniformly distributed in the tails. The hit efficiency is evaluated with the ratio between the number of real hits, extracted from a fit to the residual distribution, and the number of tracks extrapolated in the MAPS fiducial region.
Fig. 9. APSEL4D hit efficiency as a function of the discriminator threshold.
Results from a device simulation are superimposed to testbeam data. Prelim- inary result.
Preliminary results on APSEL4D hit efficiency as a function of the discriminator threshold are shown in Fig. 9. Three chips with different thicknesses (300 and 100 µm) were measured giving similar results. With a threshold of about 450 e- (thr ' 4σnoise+ 2σthresholddispertion) an efficiency of about 90%
has been reached, which is agreement with what is expected taking into account the presence of competitive nwells in the pixel layout and a cell fill factor of about 90% (shown in Fig. 10.a). In the APSEL4D matrix the sensor geometry has not yet been optimized, although there are indications from
Fig. 10. a) Schematic drawing of the APSEL4D cell layout showing the central collecting electrode and the competitive nwells. b) Cell with improved sensor geometry: multiple nwells collecting electrodes around the competitive nwells connected to the main DNW central sensor.
Fig. 11. Hit efficiency inside the pixel cell (threshold = 0.67 MIP).
Preliminary result.
a fast device simulation, developed for this pourpose, that it is possible to improve the hit efficiency still keeping the same fill factor. Improvement in the efficiency are expected for example inserting in the cell multiple collecting electrodes around the competitive nwells (Fig. 10.b). Test structures with the improved cell design have been already implemented.
The fast device simulation developed to optimize the sensor geometry takes into account the ionization process, charge diffusion, and the front-end response. The response of the sim- ulation is in good agreement with the measured hit efficiency, as shown in Fig. 9.
The effect of competitive nwells on the collection efficiency has been studied on data measuring the hit efficiency inside the pixel subdivided into 3 × 3 subcells. The efficiency map for the pixel is shown in Fig. 11 and it is clearly correlated with the cell layout shown in Fig. 10.a. The central region, fully covered with the DNW sensor, reaches 100% efficiency, even with a quite high threshold applied of about 0.67 MIP, while the pixel periphery has a lower efficiency, expecially in subcells where the competitive nwells are located (top side of the pixel).
The response uniformity across the chip has been checked with tracks. The hit efficiency for the matrix subdivided in regions of 8 × 16 pixels is shown in Fig. 12. The observed spread of about 10% in the efficiency is consistent with the average gain and threshold dispersion of about 6%: since a single threshold is applied across the entire chip a similar dispersion in the effective threshold applied on each pixel is expected.
The MAPS intrinsic resolution (σint) has been extracted
Fig. 12. APSEL4D hit efficiency across the matrix. Preliminary result.
Fig. 13. APSEL4D intrinsic resolution as a function of the discriminator threshold. Preliminary result.
from the width of the residual plot (σres ' 15µm in Fig. 8), taking into account the contribution from multiple scattering (σM S ' 6µm) and from the error on track extrapolation (σtrk ' 5µm). According to: σ2int = σ2res− σtrk2 − σ2M S, the results for the intrisic resolution is shown in Fig. 13 for the y coordinate. This preliminary result is roughly consistent with 50µm pitch and the digital readout.
V. CONCLUSIONS ANDPERSPECTIVES
Several DNW CMOS MAPS chips have been fabricated with the STMicroelectronics 130 nm triple well technology.
They implement a full in-pixel signal processing chain allow- ing the realization of a sparsified readout for thin MAPS sen- sors. Good progress have been achieved in the third generation of the APSEL chips with a substantial redesign of the pixel cell (sensor and front-end) to improve the Signal-to-Noise ratio and at the same time to reduce the power consumption.
The APSEL4D a first MAPS matrix (4k pixels, 50µm pitch) featuring in-pixel sparsification and providing timestamp infor- mation for the hits has been realized. The chip has been fully characterized in lab and recently measured with beams. Data analysis is still ongoing but preliminary results on efficiency and resolution confirmed the DNW device is working well.
Further improvement on collection efficiency are under study with a better optimization of the sensor geometry.
The new approach in the design of DNW MAPS, proposed by the SLIM5 Collaboration, is very promising to develop a thin pixel system with a fast sparsified readout for applications in silicon vertex trackers at future colliders. Within the SuperB
effort a prototype multichip MAPS module based on an evolution of the APSEL4D DNW matrix will be realized in the next two years.
Furthermore in the near future improvements on DNW MAPS performance will be investigated exploiting Vertical Scale Integration processes now commercially available.
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