Universitá di Pisa
Facoltá di Ingegneria
Corso di Laurea Specialistica in Ingegneria Elettronica
Tesi di Laurea
Analysis and Architecture Design of DSPACE,
a Digital Signal Processor for space applications
Candidato
Alessandro Vincenzi
Relatore
Prof. Luca Fanucci
Relatore
Prof. Sergio Saponara
A B S T R A C T
The request of digital signal processing performed on satellites or spacecraft is greatly increased in past years, however the European Space Agency (ESA) has not got a suitable device for these applications made in Europe area. ESA is currently forced to address to United States (US) made alternatives but the exportation of those devices is restricted by the International Traffic in Arms Regulations (ITAR) and this places ESA in a dependent position.
The DSPACE project aim to solve this lack providing a new Digital Signal Processor (DSP), as an intellectual property, and a software tool-chain to exploit its features.
The first part of this thesis work regarded an analysis of the state-of-the-art and the practical solutions in order to identify a target technology and a reference architecture.
The second part of this work concerned a detailed definitions of the DSPACE core architecture and features. Moreover a com-plete decode & dispatch VHDL model, with a formal functional verification, was realized.
The third part of this work regarded two caches modelling, the instruction and the data cache, that are two essential components of the DSPACE core.
This thesis work was concluded with the first functional sim-ulations coming from the DSPACE model and considerations about the resource occupation of the core.
C O N T E N T S
1 introduction 1
1.1 Overview . . . 1
1.2 Hardware and Software concurrent design . . . 2
1.3 Consortium description . . . 5
2 state of the art 7 2.1 DSP for ground applications . . . 8
2.1.1 Analog DevicesSHARC . . . 9
2.1.2 Texas InstrumentsTMS320C67x . . . 16
2.2 Devices for space application . . . 21
2.2.1 Devices from Atmel . . . 23
2.2.2 RTAX-DSPfrom Actel . . . 24
2.2.3 Virtex-4QVandVirtex-5QVfrom Xilinx . . 26
2.2.4 DSP from TI . . . 27
2.2.5 ST Microelectronics 65 nm technology . . . . 28
3 dspace architecture and instructions 30 3.1 Consolidation of requirements . . . 30
3.2 Architecture overview . . . 31
3.2.1 Data Processing Unit . . . 31
3.2.2 Interrupts . . . 43
3.2.3 Caches . . . 43
3.2.4 Memory interface . . . 44
3.2.5 Direct Memory Access . . . 45
3.3 Operations performed . . . 45 3.3.1 Op-codes formats . . . 45 3.3.2 Instructions syntax . . . 48 3.3.3 Instructions Set . . . 49 3.3.4 Conditional execution . . . 62 3.4 Dispatch tree . . . 62 4 caches modelling 65 4.1 Instruction cache . . . 65
4.1.1 The instruction cache contents . . . 67
4.2 Data Cache . . . 68
4.3 Functional simulations . . . 69
5 conclusions 72 a radiation effects and device hardening 75 a.1 Device hardening . . . 78 b tms320c67x instruction analysis 81
c dispatch model 87
contents iv
bibliography 90
L I S T O F F I G U R E S
Figure 1 Possible DSPACE project approaches . . . . 3
Figure 2 Synopsys Processor Designer work flow . . 4
Figure 3 TigerSHARCfunctional block diagram . . . 8
Figure 4 SHARCgenerations . . . 10
Figure 5 ADSP21469functional block view . . . 11
Figure 6 Texas Instruments floating-point DSPs . . . 17
Figure 7 TMS320C6713functional block view . . . 18
Figure 8 ADSP21020Fuctional Block Diagram . . . . 22
Figure 9 RTAX-DSPArchitecture . . . 25
Figure 10 RTAX-DSPmathblock . . . 25
Figure 11 Cross-section for commercialSRAM . . . 28
Figure 12 DSPACE core . . . 32
Figure 13 DSPACE data-path . . . 33
Figure 14 DSPACE program flow . . . 34
Figure 15 Control and status registers 1 . . . 36
Figure 16 Control and status registers 2 . . . 36
Figure 17 Control and status registers 3 . . . 37
Figure 18 Control and status registers 4 . . . 38
Figure 19 Control and status registers 5 . . . 39
Figure 20 Control and status registers 6 . . . 39
Figure 21 Control and status registers 7 . . . 40
Figure 22 Control and status registers 8 . . . 41
Figure 23 Control and status registers 9 . . . 42
Figure 24 Control and status registers 10 . . . 42
Figure 25 Fixed opcode fields . . . 46
Figure 26 DSPACE opcode types . . . 47
Figure 27 DSPACE opcode example . . . 62
Figure 28 Dispatch tree . . . 64
Figure 29 Direct mapped principle . . . 66
Figure 30 Instruction cache scheme . . . 66
Figure 31 Instruction cache block view . . . 68
Figure 32 Data cache block view . . . 70
Figure 33 Waveform output and code coverage . . . . 71
Figure 34 Van Allen radiation belts . . . 75
Figure 35 Cumulative effects and sensitive devices . . 77
Figure 36 Single event effects . . . 78
Figure 38 Computational unit resource occupation
onXilinx Virtex-6 VLX75T . . . 82
Figure 39 Computational unit resource occupation on ActelRTAX-2000 . . . 82
Figure 40 Simulation strategy of dispatch model . . . 88
Figure 41 Dispatch model screen-shot . . . 89
L I S T O F T A B L E S
Table 1 GroundDSPsmain features . . . 21Table 2 Atmel spaceFPGA main features . . . 23
Table 3 Atmel spaceASICmain features . . . 24
Table 4 ActelRTAX-DSPmain features . . . 26
Table 5 XilinxVirtex-4QVmain features . . . 27
Table 6 XilinxVirtex-5QVmain features . . . 27
Table 7 SMJ320C6701-SPmain features . . . 28
Table 8 DSPACE instruction types . . . 35
Table 9 Floating-point arithmetic-logic unit . . . 50
Table 10 Floating-point arithmetic-logic unit . . . 51
Table 11 Floating-point arithmetic-logic unit . . . 52
Table 12 Floating-point arithmetic-logic unit . . . 53
Table 13 Floating-point multiplier unit . . . 54
Table 14 Floating-point multiplier unit . . . 55
Table 15 Address generation unit . . . 56
Table 16 Address generation unit . . . 57
Table 17 Floating-point multiplier unit . . . 58
Table 18 Floating-point multiplier unit . . . 59
Table 19 Address generation unit . . . 60
Table 20 Address generation unit . . . 61
