Design of a rail-to-rail chopper instrumentation amplifier with input impedance boosting

(1)

Dipartimento di Ingegneria dell'Informazione

Informatica, Elettronica e Telecomunicazioni

Corso di studi in

Ingegneria Elettronica

Tesi di Laurea Magistrale

Design of a rail-to-rail chopper instrumentation

amplier with input impedance boosting

Candidata:

Miaosen Zhang

Relatori:

Prof. Paolo Bruschi

Prof. Massimo Piotto

Anno Accademico 2018/2019

(2)

Abstract

With electronics being so pervasive in almost every eld of human experi-ence, research and development are extremely active. Many applications are available thanks to a very wide variety of sensors, that can measure phys-ical quantities that include, but are not limited to: temperature, velocity, acceleration, pressure, radiation, chemical compounds and strain. In this eld, analog electronics plays crucial and irreplaceable role: the information provided by sensors is frequently converted into a digital form by means of an Analog-Digital Converter (ADC), so that it can be handled by a CPU for further signal processing. In order to accomplish this task, an Analog Front End (AFE) is needed. Its purpose is to adapt the sensor's output so that it can be well processed by the ADC.

Instrumentation Ampliers (often shortened as InAmps or IAs) are often employed as part of the AFE. This work focuses on designing an Indirect Current Feedback Instrumentation Amplier (ICFIA), a topology that can be eectively adapted to implement some techniques that greatly improve the device's performance and exibility. As a matter of fact, the main focus of the design is versatility: its input common mode (CM) range is rail-to-rail, and two dierent values of gain, 100 and 5, are available. In this way, the amplier can interface a wider variety of sensors, that produce both a relatively high and low output dierential voltage, regardless of their output common mode voltage.

The amplier is implemented in a CMOS UMC 0.18 µm process, that typ-ically suers from oset and icker noise. The technique implemented in this work, so as to counteract this problem, is called Chopper Stabilization (CHS). Since this solution introduces a chopper ripple, i.e. an additional disturbance at the chopping frequency, a third order low-pass Bessel lter is embedded in the amplier in order to reject it. It is implemented with three Gm-C integrators that constitute a State Variable Filter (SVF).

Despite the ecacy of chopper stabilization, it comes with its own draw-i

(3)

backs. Firstly, it introduces an additional residual oset proportional to the chopping frequency fch, that must not reach an excessively high value. At

the same time, a low chopping frequency limits the amplier's bandwidth. A trade o must be made when choosing the value of fch. The second

disadvan-tage that chopper stabilization introduces is a considerable decrease of input impedance, caused by the necessity of periodically charging and discharging the amplier's input capacitance. This issue can be eectively counteracted thanks to a technique called Port Swapping. Its main purpose is to reduce the amplier's gain error, as it depends on a mismatch between the input and the feedback ports. Port swapping periodically swaps the two ports so that the mismatch eect is reduced, and the two ports are equalized. As an ad-ditional benet, port swapping counteracts the decrease of input impedance due to chopper stabilization, boosting it by many orders of magnitude. In order to function eciently, port swapping requires the input and feedback signals to have the same common mode voltage. The output and feedback signals are connected through a resistive voltage divider, that sets the ampli-er's overall dierential gain. The voltage divider keeps the common mode voltage unaltered, thus the feedback and output CM would be the same and coincide with half the supply voltage. In order to guarantee equalization of the input and feedback's common mode voltage, a specic circuit must be implemented to accomplish this task.

Lastly, a thorough set of simulations were performed in order to verify the performance of the amplier. In particular, the input impedance is boosted from hundreds of kΩ (in only chopper stabilization was performed) to tens of GΩ. The input referred voltage noise density reaches 11.6 nV/√Hz, with a icker corner of 2.57 mHz and a 2.5 kHz bandwidth.

(4)

Introduction

Nowadays, electronics is pervasive in almost every eld of human experi-ence and many applications are available thanks to a very wide variety of sensors. Temperature, velocity, acceleration, pressure, radiation, chemical compounds, strain are just some of the physical quantities that can be mea-sured and monitored thanks to specic sensors that have been developed. In this eld, analog electronics plays an important and irreplaceable role: while the information provided by sensors is frequently analysed by digital electronics, in order to adapt it and convert it into a digital code an Analog Front End (AFE), that is a readout interface, is strictly necessary.

Instrumentation Ampliers (InAmp or IA) are often employed as part of the AFE. These devices are characterized by a highly precise dierential gain and a high input impedance.

This work focuses on designing an instrumentation amplier whose archi-tecture is based on a Indirect Current Feedback (ICFIA). This topology is characterized by a high CMRR, and with the adjustments implemented in this project, its performance and exibility can be greatly improved.

The rst and most critical issue that this topology suer from is a relatively high gain error, due to mismatch of its input stages. This problem is mit-igated in this work thanks to a technique Port Swapping. A second issue, that is known to aect CMOS analog circuits, is a high oset and icker noise. To reject them, various solutions have been found. This work very eectively implements the Chopper Stabilization technique. The consequent drawback, that is an additional disturbance at the chopping frequency, is rejected thanks to an embedded third order low-pass State Variable Filter, that implements a Bessel lter.

The conjoined eect of port swapping and chopper stabilization is also able to boost the input impedance of this amplier, that would otherwise be at-tenuated excessively if only chopper stabilization was performed.

Besides the improvements accomplished thanks to these two techniques, the key feature that this design tries to achieve is exibility: its input common mode range is rail-to-rail, and two values of gain, 100 and 5, are available.

(8)

As a consequence, this amplier is able to interface a larger variety of sensors and becomes suitable for a broader range of applications.

Chapter 1 presents a description on instrumentation ampliers, along with the reasons behind their importance and the main characteristics that they need to have in order to guarantee a good performance. Moreover, an overview on the dierent topologies that have been developed is presented. Lastly, a description of the low frequency errors and the most common tech-niques that rejects them is added.

Chapter 2 is devoted to the detailed discussion of the reference work that this thesis is based on. In particular, its main original strategies and the consequent advantages are presented, as well as the aws and the weaknesses that need to be improved.

Chapter 3 focuses on the description of this work's goal. The new feature that it introduces, as well as its high level behaviour are thoroughly discussed. Chapter 4 delves into the details of this project. The transistor level design of each block that constitute the amplier is presented, along with its topology and its main constraints. The sizing and role of each device is justied and examined.

Lastly, chapter 5 discusses the main simulations that can be performed on the complete circuit. The results are evaluated and compared to this work's original goals, along with its main electrical characteristics.

(9)

Chapter 1 Instrumentation amplier

1.1 Introduction to instrumentation ampliers

The term "instrumentation amplier", often shortened as In-Amp or IA, is used to describe a class of ampliers that feature specic characteristics. To fully understand them, it is useful to rst have a better grasp of why and how they are used.

Their main application resides in sensor readout. While many dierent kinds of sensor are designed according to the specic physical quantity that has to be measured, often-times their analog output is converted into a digital one by means of an Analog-Digital Converter (ADC), so that it can be handled by a CPU for further signal processing. To accomplish this task, an Analog Front End (AFE) has to be implemented, that is an analog block whose role is to adapt the sensor's output, which is not necessarily a voltage, so that it can be well processed by the ADC.

Sensors whose AFE incorporate an In-Amp include, but are not limited to, those who provide a voltage as output. In fact, while this category already comprises a vast range of dierent types of sensors, In-Amps are also suitable for those with resistance as output. By biasing the resistor with a constant current, or by including it inside a Wheatstone bridge, the voltage across it is eectively read by an In-Amp.

The reason behind the choice of In-Amps lies in an important quantity called Dynamic Range, in short DR. It is dened as the ratio between the maximum range and the minimum value that can be measured, that is

DR = ∆VF S

δV (1.1)

In this expression, ∆VF Sis the dierence between the greatest and the

(10)

est value that can be detected, namely it represents the range of voltage where the input can vary. Outside this range, the sensor's output is no longer meaningful, as it exceeds the limits of the sensor itself. Instead, the term δV denes the smallest dierence that can be detected between two dierent voltage values, that is the resolution, and it is determined by the noise that all electronic signals inevitably carry. Noise is a random signal generated by the thermal agitation of the charge carriers and it can be mod-elled by its probability distribution, which is not limited to a specic interval of voltages, but rather it spreads over the entire voltage spectrum. However, in practical applications it is possible to neglect a big part of the distribution and to focus on a nite interval of values that, statistically, will include a certain percentage of the voltage noise.

To be exact, an electric signal has a specic mean value and carries the meaningful information that has to be read. As the noise is added, the signal is actually located within a so called noise band, i.e. an interval of values centred around its mean value, and whose amplitude is determined by the noise's peak-to-peak magnitude, vn_pp. For a Gaussian noise, by choosing

a vn_pp value equal to two times 2σ (where σ is the distribution's standard

deviation), the probability that the noise will reside in that range can be calculated and it is equal to 95.4%. Higher values of vn_pp correspond to

a larger noise band, but also to an increased probability and accuracy of nding the signal within it.

Figure 1.1: Noise bands around two signals determine resolution

Figure 1.1 shows two signals and their respective noise bands. The reason why noise determines resolution is clearly depicted: if the noise bands over-lap, it is not possible to distinguish between the two signals, as there is an interval of voltages that likely contains both of them. Instead, if they are well separated, this uncertainty disappears and the minimum interval that allows this condition is exactly the chosen vn_pp.

(11)

coin-cides with the number of dierent values that the following ADC can recog-nize, and it controls the overall performance of the sensor reading. In fact, the DR of the whole system is limited by the smallest one among the single blocks that form it: each block added to the system inherently contributes its noise, degrading the total DR, including the ADC. Here the In-Amp plays an important role: rst let us consider a system lacking an amplier. In this case, the DR is given by

DR = ∆VF S_s vn_tot

(1.2) with

v_{n_tot} = v_{n_s}+ v_{n_ADC} (1.3) where ∆VF S_s is the sensor's full scale range, vn_tot is the total noise made

up of vn_s and vn_ADC, the sensor's peak-to-peak noise and the ADC noise,

that can not be smaller that the quantization noise. Since a large variety of sensors produce signals of very small magnitude (order of a few millivolts), so their ∆VF S_s is comparable to the ADC noise, the overall DR would be

too small, thus not acceptable. It is worth noting that the intrinsic sensor noise is generally much smaller than the ADC noise.

By inserting an In-Amp inside the system, before the ADC, the total noise becomes

vn_tot = vn_s+ vn_In−Amp+

vn_ADC

A ≈ vn_s (1.4) with A being the amplier's gain and vn_In−Amp its noise. Since the noise is

Referred To Input (RTI), the ADC's noise is signicantly lowered thanks to a large enough A, and if the In-Amp itself brings little contribution by having a negligible noise with respect to the sensor's, it's clear that the overall DR remains virtually the maximum value allowed by the sensor.

DR = ∆VF S_s vn_tot

≈ ∆VF S_s vn_s

(1.5) Though a high A is an advantage from the noise point of view, it can not be made too large, as the amplier's output would exceed the ADC's input range. The gain should be adjusted so that most of the converter's input range can be exploited.

After having understood why In-Amps are so useful, which main features, as well as secondary ones, they ought to have in order to obtain a good per-formance, become clear. These characteristics are discussed in the following sections.

(12)

• Gain

Gain is dened as the ratio between the output and the input volt-age of the amplier. Given In-Amps application, their gain has to be known throughout their entire bandwidth. It should be as precise and as constant as possible, since its variations result in dierent estimated input than the one actually given by the sensor or the block preceding the In-Amp, causing an error in the signal processing.

To accomplish this, it is a good rule to design the amplier so that his gain is set by the ratio of homogeneous quantities. In fact, if it was dependent on the absolute value of certain components, its error would be much greater. That is because, normally, process's imprecisions and dependence on temperature variations cause a rather large variation of the actual value produced, compared to the nominal one. Even though their inuence is still present when setting gain as a ratio, they are mit-igated by the fact that in this case they aect the components in the same way, that is their matching error is usually quite small. There-fore, variations with respect to the nominal value cancel out in a ratio, making the gain much more precise.

If the resulting error still exceeds the system's objective, it can be minimized by adjusting it through other strategies, for instance laser trimming. It consists of burning part of an electronic component with a laser beam, in order to change his actual value until it reaches the desired one. This procedure has to be done for every critical component of every single chip, making it time consuming and expensive. There-fore, nding solutions that obtain small gain errors that do not require trimming is a great advantage.

• High input impedance

The amplier has a voltage as input, therefore the sensor preceding it should act like a voltage source. However, more often than not this source shows a rather high output impedance, making it non-ideal. This implies that the amplier needs a very large input impedance, so that, when connected to the voltage source, it will not load it exces-sively. Otherwise the actual voltage it receives becomes rather dierent than the one provided by the sensor, causing a large error when reading it.

Typical values of input impedance can vary from 107 _{up to 10}12_Ω_.

• Dierential input

Having a dierential input makes the amplier much more versatile in various applications, since it can be used with all types of sensor.

(13)

Moreover, even though it is not an explicit requirement for instrumen-tation ampliers, if they are equipped with a dierential output as well, the numerous advantages introduced make them signicantly preferable compared to Single Ended (SE) ones. This type of ampliers is called Fully Dierential (FD).

FD ampliers oer several advantages, but before discussing them, it is worth introducing some denitions of signals and gains involved in a fully dierential circuit. Given a signal, let vp and vn be its positive

and negative terminal, both referred to ground. Then, two auxiliary signals can be dened as

vd= vp− vn (1.6)

vcm =

vp+ vn

2 (1.7)

These quantities are respectively called dierential mode and common mode.

Moreover, let us consider a FD amplier as shown in gure 1.2.

Figure 1.2: A fully dierential amplier

Of course, dierential and common mode can be dened for both input and output ports. Now, based on these signals, four dierent gains can be dened: Add = vd−out vd−in (1.8) Acd = vd−out vcm−in (1.9) Adc = vcm−out vd−in (1.10) Acc = vcm−out vcm−in (1.11)

(14)

Among these, Add is the gain previously mentioned and, as such, it is

of utmost importance and it has to be precise and well designed. Given these denitions, let us turn attention to the benets granted by a FD system. First of all, their immunity against interferences increases compared to SE ones. This robustness is eective against various types of disturbances. For instance, in a circuit the ground voltage is not nec-essarily constant across the whole PCB, since there might be parasitic resistances on the ground distribution wires. This implies that dierent components might receive a ground voltage that is not the same for all of them. While for a single ended circuit this is a rather important disturbance, as it changes the eective voltage values, in the case of a fully dierential system the additional potential drop aects both the terminals of a signal, hence changing the common mode voltage but leaving the same useful dierential signal. Of course, to keep a good-functioning circuit, a high Common Mode Rejection Ratio (CMRR) is required, so that the common mode voltage change produces no signif-icant eects.

Similarly, if the circuit undergoes a variation in supply voltage, only a common mode disturbance is created and the useful dierential signal is unaected. In this case, the Power Supply Rejection Ratio (PSRR) has to be high enough.

It is worth mentioning that FD systems inherently have higher CMRR and PSRR compared to SE circuits, due to their intrinsic symmetric. Therefore, these quantities are mostly aected by matching errors. Another advantage of FD circuits is increased immunity against capac-itive coupling. This eect is created by the presence of a disturbing signal running on a interference line, that could inuence some signal lines through a parasitic capacitance. In this case, the eective signals received by a device undergo a variation, given by the divider made up of the parasitic capacitance and the impedance between the terminal of interest and ground. For FD systems, this disturbance mainly aects the common mode, while the dierential mode is virtually unchanged. However two terminals of a signal can not be coincident, therefore they might be inuenced by dierent parasitic capacitance, creating a dif-ferential mode variation that is small, but possibly not negligible. A careful layout can decrease this eect: if the interfering line is doubled and runs symmetrically with respect to the circuit, the parasitic capac-itance seen by the terminals will be the same and the disturbance will not be able to aect the dierential mode.

(15)

Another type of interference that is rejected is substrate noise. This eect is created by an electric component that undergoes a large and fast voltage swing (for instance, a digital MOSFETs commuting). Since the substrate can be modelled as a resistive mesh, this swing propa-gates, though attenuated, through the network until it reaches another component. Here, it can inuence it in two dierent ways: it can be injected through the junction capacitance inside both drain and source, or it can change substrate potential, hence modifying the component's threshold voltage. In a FD system, if some components are suciently distant from the disturbance's source, substrate noise will be rather constant for all of them, creating only a common mode variation. Lastly, FD circuits have additional advantages that do not concern interference, but the signals themselves. If we assume that a single terminal can vary between Vmax and Vmin, than the output swing for a

single terminal is Vd−max= Vmax− Vmin, while the total one will be

∆V = Vd−max− Vd−min = Vmax− Vmin− (Vmin− Vmax) =

= 2(Vmax− Vmin)

(1.12) Clearly, the output swing is doubled compared to a SE circuit.

Moreover, within this interval it is possible to obtain improved linearity, which for an amplier is a good feature to have. The reason behind this lies, again, in symmetry. If the positive output terminal is given by a generic vout−p = f (vin−d), that is a function of the dierential

input, then the negative one will be vout−n= f (−vin−d). Therefore the

dierential output is vout−d = f (vin−d) − f (−vin−d). This is clearly an

anti-symmetric function, hence it lacks even order terms in its Fourier expansion. Given a generic signal, its linearity is measured thanks to its Total Harmonic Distortion (THD). This quantity is mainly inuenced by the second harmonic, which is not present in an anti-symmetric function. Therefore, FD circuits show increased linearity within their output range.

• High CMRR

As mentioned previously, a high CMRR over the range of input fre-quencies is necessary in order to well exploit the advantages granted by a FD system. It is dened as CM RR = Add Acd (1.13)

(16)

therefore, it quanties how much the output depends on the dierential mode input with respect to the common mode input.

Often, this quantity is expressed in decibels (dB), that is

CM RR|dB = 20 log10(CM RR) (1.14)

as it usually has a large value. In fact, typical CMRR values range from 70dB up to 100dB, and it can reach 120dB.

A small CMRR is detrimental not only because it spoils the natural ad-vantages of In-Amps mentioned above, but it also causes an inecient sensor readout. This is the case of sensors that show a noisy common mode voltage, that obviously has to be rejected.

• High PSRR

PSRR, that is Power Supply Rejection Ratio, is dened as P SRR = ∆Vdd

∆Vd−out

Add (1.15)

This expression quanties, for a given power supply change ∆Vdd, the

corresponding ∆Vd−out

Add , that is the input dierential voltage ∆Vd−in, that

would produce the same output variation.

As mentioned in a previous paragraph, the higher this quantity is, the better the In-Amp performance.

Like CMRR, it is often expressed in dB as

P SRR|dB = 20 log10(P SRR) (1.16)

and it typically varies from 80dB to 120dB.

PSRR is especially important for mixed signal systems, where both analog and digital circuits are present at the same time. This is because the digital domain obviously works thanks to a clock signal. However, as it toggles, it causes a spike in the supply voltage which can not be an ideal source. These variations are also perceived by the analog part of the circuit, that without a proper PSRR would see them as a disturbance and their performance would be degraded.

• Input common mode range

An In-Amp with a large input common mode range is very exible and could be used for numerous kinds of applications. In fact, dierent types of sensors can work with dierent values of CM and an In-Amp

(17)

with a large input CM range means that it can, potentially, work with all of them. Ideally, this range would be rail-to-rail, i.e. it can vary between the ground and the supply voltage.

• Low noise, oset, bias current

Figure 1.3: A real In-Amp connected to a real voltage source

Picture 1.3 shows a real instrumentation amplier. The dierence com-pared to and ideal one lies in noise: an In-Amp inherently adds its own to the system where it is embedded. For analyses purposes, it is useful modelling the real device with an ideal one that does not introduce noise. To make it real, three generators are added at his input ter-minals: one voltage source, vn, and two current sources, iB1 and iB2.

Their DC components are exactly the amplier's oset voltage and bias currents. Moreover, the oset current IIO is the dierence between IB1

and IB2.

Beside the amplier, it is useful modelling the sensor that has to be placed before it as well. It can be represented by three voltage sources connected as shown in the picture. VCM gives the common mode

volt-age, while VS1 and VS2 provide the dierential one. Since the sensor is

never an ideal voltage source, two resistances RS1 and RS2 are placed

at the sensor's terminals to make it real.

Considering this setup, it is clear how the amplier's input voltage is not the ideal vS1− vS2, but rather it is equal to

(18)

vin = (vS1− vS2) − vn− (RS1iB1+ RS2iB2) (1.17)

If the source is balanced, that is RS1 = RS2= RS, then

vin = (vS1− vS2) − vn− RS(iB1+ iB2) (1.18)

Clearly a good instrumentation amplier should keep these noise sources as low as possible. In-Amps that include MOSFET usually have very low bias currents, as they are mainly caused by the inverse currents of gate-protection diodes or small leakages coming through the gates oxide of the transistors. On the other hand, if the architecture involves JFET or BJT, its bias current might not be negligible and should be taken into consideration.

Noise voltage, instead, is characterized by two dierent components. The rst one is the thermal noise mentioned earlier, that shows itself at higher frequencies and is reduced by increasing current consumption. Instead, at smaller frequencies another type of noise dominates, that is the icker noise, which is proportional to 1/f. This component is par-ticularly relevant for MOSFETs, therefore circuits have to be carefully designed to deal with it. As a rule of thumb, larger transistor areas reduce icker noise, though obviously they increase the chip's dimen-sions.

Lastly, oset voltage is mainly determined by mismatches between cir-cuit's component that are supposed to be identical. Moreover, it can change in a signicant way due to changes in temperature. This drift can not be cancelled with a one time calibration, therefore it has to be dealt with other techniques.

To reduce low frequency noise and oset voltages, various solutions are invented, each with its strengths and weaknesses. For example some of the most common approaches are Correlated Double Sampling (CDS), Auto-Zero (AZ) or Chopper Stabilization (CS). They will be discussed in detail in section 1.4.

• Low power consumption and NEF

Another quantity that has to be taken into consideration is the ampli-er's power consumption. Ideally it has to be kept as low as possible, for instance by decreasing current consumption, yet this contrasts with the low noise requirement mentioned in the previous section.

This requisite is important as many sensor systems are battery pow-ered. Moreover, high power consumption causes self-heating, degrading

(19)

characteristics that might depend on temperature (as the previously mentioned oset) or other circuits embedded on the same chip.

In order to draw a fair comparison between dierent architectures from the power consumption's point of view, a commonly employed gure of merit is the Noise Eciency Factor (NEF), which was rst introduced in [1]. Its denition is N EF = vn−amp vn−bjt = _s vn−amp 4kT VT Isupply Bπ 2 (1.19)

This factor compares the noise of the amplier, considered as total input Root Mean Square (RMS) value, with the one of an amplier made up of a single BJT transistor. To be exact, the term in the denominator is proportional to the thermal noise given by a single BJT biased with the same collector current Isupply, as the amplier

being tested. Moreover, they also share the same Bπ

2, which is the

In-Amp's eective noise bandwidth if its frequency response was a rst order low-pass lter and B is the -3 dB bandwidth. This denition is based on the fact that BJTs have the best tradeo between input voltage noise and current consumption, therefore it is reasonable using it as a touchstone.

1.2 Main topologies

Instrumentation ampliers can be built in several dierent ways. Every sin-gle topology has to consider the characteristics mentioned in the previous section and achieve the best tradeo between all of them.

Even though BJTs carry lower oset and icker noise, CMOS technology is now preferred over bipolar one. Its low cost, its capability of being integrated with digital circuits, its high scaling level, its zero gate current and so on, make its diusion widespread. Of course, problems arising from its disadvan-tages, as high noise, drift and component mismatch, have to be dealt with. Hence, the topologies taken into consideration (for further details, see [2], chapter 1) in the next sections are all implicitly based on CMOS technology, unless stated otherwise.

(20)

1.2.1 Three Op-Amp topology

Figure 1.4: The three Op-Amp topology

This topology is characterized by two stages: the rst one is made up of two Operational Ampliers (also referred to as Op-Amps) and the resistances RG

and R1. Together, they form a FD amplier. The rest of the circuit is the

second stage, which is a dierential amplier. The overall gain is A = 1 + 2R1

RG (1.20)

where RGcan be external and its value be changed to obtain the desired gain.

This expression holds true if the Op-Amps' open-loop gain is high enough. The CMRR of the second stage is determined by the matching of its feed-back resistors and, multiplied by the gain of the rst stage, it gives the total CMRR. It also depends on the gain, thus it decreases with small values of A. With resistor trimming, it can reach 80 dB, which according to the ap-plication might not be high enough.

Another disadvantage is that power consumption will not be very low and this amplier's power eciency will not be excellent.

This amplier's input common mode voltage needs to stay within its own output swing, since they share the same CM. By summing the amplied dierential output, it is likely that the amplier saturates, even with small variations of input common mode voltage.

(21)

voltage source whose output impedance must be rather small, that is negligi-ble compared to R. Otherwise, the second stage's performance (for instance its CMRR) would be strongly worsened.

1.2.2 Switched-Capacitor Topology

Figure 1.5: The switched-capacitor topology

As its name suggests, Switched-Capacitor (SC) ampliers exploit capacitors and switches in order to obtain the needed function. Figure 1.5 shows an example of SC charge amplier used for interfacing capacitive sensors. The sensor is represented by CX and CR and their dierence, ∆C = CX − CR,

is the quantity that needs to be measured. The amplier is made up of an Op-Amp and another capacitor C2. VR, instead, is a constant reference

voltage. These components terminals are connected to dierent wires thanks to the switches. Thus, there are two distinct phases of operations according to a clock signal fs. In the rst one, the switches are closed in the position

marked with the label 1. This is a reset phase. At the end of the second one, instead, the output voltage is ready to be read. A complete analysis of the circuit's behaviour during the two phases of operation can be found at [3]. The net result is that the gain is given by

A = VR C2

(1.21) while the amplier's noise is greatly reduced thanks to the dynamic tech-nique, the correlated double sampling, that this topology naturally imple-ments and that will be described in detail in section 1.4.2.

(22)

rst of all, sampling a signal on a capacitance will add kT

C noise. Moreover,

its eect is worsened by CDS: while this strategy eectively decreases DC oset and icker noise, it also causes noise foldover, thus increasing the total one within the Nyquist bandwidth (that is given by fs

2).

Another issue that the SC instrumentation amplier suer from is an input impedance that does not reach high values easily. The presence of input capacitor means that, for every clock commutation, the voltage source needs to charge them, thus creating an equivalent input impedance equal to [4]

Zin =

1 4Cfs

(1.22) where fs is the sampling frequency. It can be increased by designing small

values of C, but that also causes a greater kT

C noise.

Lastly, the switches themselves, that are usually implemented as digital MOSFETs, can be treacherous because of the charge injection phenomenon. This term refers to both the actual charge injection, but also another eect called clock feed-through. The former is caused by the negative charge, ac-cumulated in a turned on MOSFET's channel, released into its drain and source once it is turned o. The latter, instead, is generated by the clock signal: through the two parasitic capacitors between the transistor's drain and source and its gate, the control signal can inject charges into the MOS-FET's terminal as well. If the switch is turned on from the o state, the same phenomenons takes place, but with opposite charges.

In general, charge injection alters the voltage value that is supposed to be sampled across a certain component, capacitors in the case of SC In-Amps, causing an error that might not be negligible. Its eect can be decreased by designing switches with small area or larger capacitance, and also by adding dummy switches that are controlled with the opposite clock signal as the actual switch being improved. Their role is to inject the opposite charge as the latter, thus compensating its eect, that can be decreased of at least one order of magnitude.

(23)

1.2.3 Capacitively-Coupled Topology

Figure 1.6: The capacitively-coupled topology

An implementation of a Capacitively-Coupled Instrumentation Amplier (CCIA) is shown in picture 1.6 and presented in [5]. It is made up of two stages that include an input transconductor Gm1 and a Miller-integrator built around

Gm2. The feedback network consists of capacitors, that obviously block DC

signals. Therefore, a chopping technique is implemented thanks to CHf b

and CHin, so that the DC signals are transformed into AC ones. Thus they

are no longer blocked by the presence of the capacitors. Consequently, an output chopper CHout is added between stages Gm1and Gm2 to demodulate

the signals.

A great advantage of this topology is that the constant common mode volt-age is blocked by the input chopper and Cin, therefore this amplier achieves

a real rail-to-rail DC CM input. The gain of this amplier is given by

A = A0 1 + A0

Cf b

Cin

(1.23) where A0 is Gm1 and Gm2's DC gain. To achieve acceptable gain error, A0

has to be designed rather large (over 130dB) and mismatch errors between the capacitors must be minimized thanks to a careful layout.

The input impedance is the same as the switched-capacitor In-Amp, though boosting techniques have been developed [5] to increase it, and they also share the same charge injection phenomenon caused by the combination of

(24)

capacitors and switches, though it is less severe due to the lack of a proper signal sampling on the capacitors.

1.2.4 Current-Mode Topology

Figure 1.7: The current-mode topology

Figure 1.7 shows the basic components that make up a current-mode In-Amp. The buer conguration of the two input Op-Amps forces the input voltage to be reproduced across a resistor R1, thus causing a current I to ow

through the component. I is then replicated, thanks to dedicated precision current mirrors, so that it is received by another resistor R2. Here, it is

converted into a voltage and then buered by an additional output Op-Amp. The dierential gain is equal to the ratio between the two resistances, that is

A = R2 R1

(1.24) The gain's precision, as well as overall oset, drift and linearity, strongly depend on the DC precision of the current mirrors, while their matching sets the total CMRR of the In-Amp.

The use of Op-Amps provides good input and output impedance, though they need to have a rail-to-rail output, if the amplier is to guarantee a common mode swing that reaches the supply rails.

(25)

1.2.5 Direct Current Feedback Topology

Figure 1.8: The direct current feedback topology

Figure 1.8 shows the basic principle of a direct current feedback IA. In this topology, the input transconductor and the feedback one share the same bias current, therefore their signal currents are able to compensate each other directly. This feature makes this architecture suitable for low power con-sumption application. While the example shown here is implemented with BJTs, later on a version employing MOSFETs [6] has been developed . This topology entail stacking two transconductors, thus minimum supply voltage increases. Furthermore, the input CM swing is limited by the place-ment of the feedback stage (Q21and Q22) placed below it, which sets a usually

(26)

1.2.6 Indirect Current Feedback Topology

Figure 1.9: The indirect current feedback topology

The Indirect Current Feedback Instrumentation Amplier (ICFIA) topology diers from the direct version since the two main transconductors do not share the same bias current. It is a very popular architecture, thus the acronym CFIA usually refers to this particular version. Figure 1.9 shows the basic elements that constitute it. It is made up of two transconductors, Gm2

and Gm3. The former receives the input voltage, while the latter a fraction

of the output voltage. The feedback network, in fact, includes three resistors so that Gm3's input is given by

Vf b = Vf b+− Vf b− =

R1

R1+ R2a+ R2b

Vout = βVout (1.25)

Gm2 and Gm3 transform their respective input voltage into dierential

cur-rents. Their outputs are connected so that these current are subtracted and fed to the second stage. This is made up of a Miller compensated integrator, built with Gm1 and two capacitors C1 and C2. Its high gain and the overall

feedback make sure that the output currents it receives are nulled. Under this condition, the gain of this amplier can be derived and its expression is

A = Gm2 Gm3 1 β ≈ 1 β (1.26)

(27)

where the approximation comes from the fact that, normally, Gm2is designed

to be equal to Gm3. However, for them to have exactly the same value is

rather dicult, as mismatch between transconductance values can be quite high. Thus, layout must be done with care, for both the transconductors and the resistors, since the latter's mismatch aects gain error as well.

Beside layout, another issue decreases matching of transconductance values. In fact, they depend on the common mode value that the component receives. Thus, if the input and feedback voltages dier, gain error is due to increase. This problem should not be left unattended.

Despite these drawbacks, the CFIA topology is characterized by important advantages: rst of all the CMRR (that mainly depends on Gm2's) can

achieve high values. Moreover, the input CM voltage itself can swing be-tween the rails, if the input transconductor, that is usually implemented with dierential pairs, include two of these: an n pair to accept the positive rail and a p pair for the negative one.

Furthermore, this amplier's input impedance is rather high, especially com-pared to the capacitively-coupled topology, since there is no need to periodi-cally charge its input capacitance. This problem, however, arises if a chopper modulation has to be implemented. In fact, the input parasitic capacitance of the transconductors, combined with the chopper's switches' charge injection, would create the same phenomenon present is SC ampliers that ends up low-ering input impedance. However, chopper stabilization technique is rather suitable with this architecture, and though it does degrade input impedance creating a disadvantage that has to be addressed, it also greatly improves noise performance. In fact, if not taken care of, oset and icker noise would otherwise be excessive and a hindrance to actual application of this topology.

1.3 Low frequency errors

Generally, the bandwidth needed for sensor systems is rather narrow and it usually varies from several Hz to a few kHz. In this range, oset, drift and icker noise are predominant, especially for circuits employing CMOS tech-nology. Nevertheless, MOSFETs' advantages mentioned in previous sections make them widely popular, therefore the problem of low frequency noise has to be addressed. However, before discussing the most common techniques, a brief description about the nature of the mentioned error sources is needed.

(28)

1.3.1 Oset

A real amplier, when its input terminals are short-circuited, does not output the expected null voltage. Instead, it is actually provided by the amplier if a dierential input voltage is applied and this quantity is called oset voltage. This disturbance is mainly caused by slight variations with respect to the nominal values of components' parameters, that the manufacturing process necessarily introduce. For example, MOSFETs' threshold voltage, Vth, might

not be the expected one because the actual doping level of the transistors' channels and gates varies randomly. The same happens with devices' actual dimensions.

Though, as mentioned earlier, fully dierential topologies naturally show lower oset due to their symmetry, mismatch between components that are also caused by manufacturing errors, can alter it, thus creating a non-zero oset value.

For instance, let us consider a MOSFET. Its threshold voltage Vt and its

proportionality coecient β between squared overdrive and current are im-portant parameters that can vary due to process errors. These variations can be expressed by σ∆β β = C∆β β √ W L σVt = CVt √ W L (1.27) where σ is the standard deviation of the distributions, CVt and C∆β

β are two

parameters that depend on the specic process employed, and W and L are the transistor's channel width and length.

The standard deviations' expressions show that mismatch problem benets from devices with larger areas, since a certain process error would have less inuence with respect to a smaller transistor. However, this increases chip area.

Beside dimensions, proper layout helps with components' mismatch as well. For instance, devices that are required to be equal should be placed with the same orientation and as close as possible, so that wafer's electric parame-ters' or process's variations aect them in a similar manner. Another useful strategy is to place devices in a common-centroid layout, so that gradients of electric parameters are overall compensated.

Despite these attentions, oset voltage can be very high, as it still reaches several mV, therefore other techniques must be implemented to overcome this problem.

(29)

1.3.2 Drift

Some parameters that cause or worsen errors are inuenced by temperature variations or passage of time. Generally they produce a change in oset or gain. Clearly, these changes should be kept as low as possible, since drift would be mistaken as an output signal coming from the sensor.

Since drift is usually rather slow, it shows itself at low frequencies, thus it can be eciently rejected by the dynamic techniques that will be discussed in following sections.

1.3.3 Flicker noise

Flicker noise is a phenomenon that shows at low frequencies. Its origin is not entirely clear, however models that describe it have been developed, though they are not universally considered an exhaustive representation of this eect. For MOSFETs, a useful model [3] consists in describing the Power Spectral Density (PSD) of its drain-source current's noise due to the icker phenomenon as SIn−F(f ) = Nf W Lg 2 m 1 f (1.28)

In this expression, W and L are the transistor's width and length, gm its

transconductance, and Nf is a parameter that depends on the process and

the type of MOSFET being considered, nMOS or pMOS.

Other models have been presented, but the main element they share and that characterizes icker noise is its proportionality to 1/f, resulting in its typical behaviour of great increase at low frequencies. At higher frequencies, however, its contribution ends up being overcome by the broad-band noise. This component has a at PSD and is mainly due the inevitable thermal noise that every electrical component produce. An expression that describes it is

SIn−T(f ) =

8

3kT gm(1 + m) (1.29) where k is the Kelvin constant, T is the temperature in Kelvin and m is a pa-rameter that depends on the transistor being considered and is equal to gmb

gm.

In the latter expression, gmb represents the body eect transconductance.

A notable parameter is the so-called corner frequency fk, that is the

fre-quency where the icker and the broad-band components are equal.

Though it is possible to reduce icker noise by designing larger transistors' area, this would also increase chips' dimensions. Moreover, this solution is of-ten not eective enough. In fact, MOSFETs' frequency corner is ofof-ten rather

(30)

high, usually in the order of kHz up to several MHz. Therefore 1/f noise is denitely not negligible within usual bandwidth of interest and needs to be dealt with other strategies.

The elements discussed here are clearly shown in gure 1.10. It depicts the typical noise power spectral density of a CMOS amplier, where all the contributions discussed in previous paragraphs are being considered.

It is clear that, at low frequencies, 1/f noise, oset and drift are the main error sources, that are not negligible and greatly degrades an amplier's performance. Thus, they have to be decreased with dynamic techniques, as the ones being discussed in the following section.

Figure 1.10: Typical low frequency noise spectrum for CMOS amplier

1.4 Dynamic techniques for low frequencies

re-duction

Given the error sources previously described, various strategies have been studied in order to deal with them and suppress their contribution. The most common techniques are Auto-Zero (AZ), Correlated Double Sampling (CDS) and Chopper Stabilization (CS). Detailed analysis can be found in [7], but here their operating principle and net results will be discussed.

1.4.1 Auto-Zero

Auto-zero is a technique based on a simple principle: it considers two dier-ent phases of operation. In the rst one, noise is sampled and stored, so that it can be subtracted from the signal during the second one. These two phases alternate periodically, so that not only DC noise is compensated, but also all

(31)

low frequency contributions that could change over time, but not in a signif-icant way between the two phases. Circuitry details depend on the specic implementation of this technique. In particular, three basic topologies have been developed: output oset storage, input oset storage and closed-loop oset cancellation with an auxiliary amplier.

• Output Oset Storage

Figure 1.11: Auto-zero with output oset storage

Figure 1.11 depicts a basic implementation of auto-zero with output oset storage. As shown in the picture, the amplier is considered ideal (that is it does not introduce any noise), while a RTI noise volt-age source, vn, is connected to one of its input terminals. In addition,

there are two capacitors, C1 and C2, and several switches being

con-trolled by proper control signals.

During the rst phase, the CK signal is high, thus it closes the switches it controls. In particular, the amplier's inputs are short-circuited, and its output is simply v0

out = Avn. This voltage value is also stored across

C1 and C2, as the overall output, vout is also shorted.

In the second phase of operation, all switches commute. The input voltage is connected to the amplier that process it. vn undergoes the

amplication as well, however, since it was already sampled in the two capacitors, during this phase vout is cleaned out by its contribution.

Therefore, the output voltage is just Avin, where noise is completely

cancelled, supposing it did not change during the two phases of opera-tion.

(32)

can not be too high, because otherwise the amplied input noise could saturate the output.

• Input Oset Storage

Figure 1.12: Auto-zero with input oset storage

This topology, as its name suggests, still stores the oset into two capacitors, but they are placed at the amplier's input.

During the auto-zero phase, CK closes its switches, while the others are open. Thus, the input voltage is disconnected, and the amplier is forced in a unity-gain conguration. The output voltage is given by

vout =

A

1 + Avn ≈ vn (1.30) and is replicated at the X and Y nodes, therefore it is also stored in the two input capacitors. The approximation is valid if the amplier's gain, A, is high enough. During the second stage, the noise's eect is cancelled by the voltage stored in C1 and C2.

To be exact, the referred to input residual oset is vres =

vout

A = vn

1 + A (1.31) where the oset is eciently reduced by the amplier's gain.

In the auto-zero with input storage, as well as in the the case of output storage, it is necessary to guarantee that the loading eect of the ca-pacitors during the AZ phase does not lead the amplier to instability.

(33)

• Closed-Loop Oset Cancellation with Auxiliary Amplier

Figure 1.13: Auto-zero with closed-loop oset cancellation

This topology helps with the degraded stability of the previous archi-tectures, as the capacitors are no longer in the signal path, but in the feedback network.

Figure 1.13 shows a basic implementation of this architecture. Dur-ing the auto-zero phase, only switches controlled by CK are closed, thus Gm1's inputs are short-circuited and the capacitors C1 and C2 are

connected to the output. In this setup, the output voltage is

[Gm1vn1− Gm2(vout−AZ− vn2)]R = vout−AZ (1.32) thus vout−AZ = Gm1Rvn1+ Gm2Rvn2 1 + Gm2R (1.33) This voltage value is then stored in C1 and C2.

The referred to input oset value is vres= vout−AZ Gm1R ≈ vn1 Gm2R + vn2 Gm1R (1.34) thus the two noise sources are suppressed by the ampliers' gain. All the auto-zero topologies described here suer from common draw-backs. First, they use switches to sample voltage values into capacitors, thus they suer from charge injection that ends up altering the actual

(34)

residual oset. This introduces an additional error source. Second, the presence of capacitors, especially if external, causes the amplier to require longer overload recovery, that is it takes more time to recover if its output saturates. Lastly, this topology is not able to provide a continuous-time output, since having a periodic auto-zero phase means that during this time interval, the amplier is not available to process the input voltage. This particular issue can be solved if a ping-pong architecture is implemented.

Noise considerations

The auto-zero technique is able to cancel noise contribution that do not vary signicantly between two consecutive phases of operation. This means that only part of the noise's spectrum is eciently compensated, that is frequencies much smaller that the clock signal's, fs.

An extended noise analysis when employing auto-zero can be found in [7]. However, the relevant results can be discussed: an important eect that takes place is noise foldover. Outside the band corresponding to the sampling frequency, that is for f > fs, noise is not aected and only the thermal

contribution is present. Instead, for f < fs, the broad-band noise Sn−T is

replicated multiple times, so that the total result is Sn−tot ≈ 2

Bn

fs

Sn−T (1.35)

where Bn is the noise's bandwidth. This expression holds true if fs > fk,

that is the icker noise is entirely cancelled.

(35)

Picture 1.14 shows the comparison between noise PSD before and after the eect of auto-zero, as well as the suppressed baseband component and the foldover phenomenon.

1.4.2 Correlated Double Sampling

Figure 1.15: Basic correlated double sampling system

Correlated Double Sampling (CDS) is another noise-cancelling technique. Like auto-zero, it employs capacitors and switches, but it diers since it does not sample only noise, but also the signals, thus it is a discrete time system. Like AZ, there are two phases of operations. During the rst one noise is sampled, while in the second one it is subtracted from the signal. The out-put voltage is available at the end of the second phase, when the signals are stabilized.

An amplier that implements CDS is the SC In-Amp already discussed. An-other simple architecture is the one shown again in gure 1.15. The switches are open ore closed during the two phases of operation according to the the label placed next to it. Thus, at the end of the rst phase, when all values are stabilized, the following expressions can be considered valid:

V_out(1) = −V_n(1) (1.36) V_C(1) 1 = −V (1) n (1.37) V_C(1) 2 = V (1) n (1.38)

(36)

When the switches commute, part of the charge previously stored in the capacitor C1 is forced to ow into C2, according to the equations

V_C(2) 1 = −V (2) n − Vin (1.39) ∆Q = C1(V_C(2)₁ − V_C(1)₁ ) = C1(−Vn(2)− Vin+ Vn(1)) (1.40) V_C(2) 2 = V (1) C2 + ∆Q C2 = V_n(1)+ C1 C2 (−V_n(2)− Vin+ Vn(1)) (1.41)

Thus, the valid output voltage, that is at the end of the second phase, is given by V_out(2) = −V_n(2)+ V_C(2)₂ = −C1 C2 Vin− (1 + C1 C2 )[V_n(2)− V_n(1)] (1.42) This analysis overlooks additional contributions due to charge injection from the switches and kT/C noise, that would alter the voltage values with respect to the ones being considered in this study.

It is evident that, while the rst addendum of this expression is the useful signal amplied, the second depends on the dierence of the noise samples during two consecutive phases. Since oset does not change over time, it is completely cancelled. However, also noise that stays rather constant is greatly reduced. These noise contributions are clearly correlated, hence the name of this technique.

Noise considerations Like in auto-zero technique, a detailed analysis of the eect of CDS on noise's spectrum can be done and found in [7]. The net results are the following: rst of all, icker noise is completely rejected, if the sampling frequency is higher that the its corner frequency. However, due to sampling, the foldover phenomenon appears in this technique like in AZ. The thermal noise (that is the only contribution present for frequencies higher that the sampling frequency fs) is replicated within the Nyquist band

multiple times, thus increasing noise and producing a power spectral density that can be approximated as

Sn−tot ≈ 4

Bn

fs

Sn−T (1.43)

Compared to auto-zero, the rst thing that stands out is the multiplying factor 4, instead of the AZ's 2. It might look like AZ's performance is better, however its auto-zero phase is usually very short compared to the sampling period, thus B = Bn >> fs. Therefore, the factor B_f_sn can be rather high.

(37)

CDS, instead, does not have this limit, since the two phases of operation can be equally long, therefore this factor will not penalize noise as much as AZ.

1.4.3 Chopper Stabilization

Figure 1.16: Block diagram of chopper stabilization

Chopper Stabilization (CS) is another technique that helps against low fre-quency noise, whose basic implementation is shown in picture 1.15.

The operating principle is as follows: at the input and output of the ampli-er A, two modulators are placed. They multiply the incoming signal by a square wave m(t), characterized by a certain frequency fch and a duty cycle

δ = 0.5. The rst modulator receives only the input signal Vin, thus it shifts

it around fch and its multiples, for both positive and negative frequencies.

This modulated signal is then fed into the amplier. However, also oset and noise are summed, thus amplied, though they do not undergo any modu-lation. The next step is demodulation, that is the amplier's output, VoA,

is multiplied once again by m(t). This causes oset and noise to be shifted around fch, that is to higher frequencies than the baseband, where instead

the input signal is brought back by the demodulation. Lastly, a Low-Pass Filter (LPF) eliminates the modulated noise and oset, while preserving the useful amplied signal.

A detailed analysis in the frequency domain can be done as follows: rst m(t) can be expressed as

(38)

m(t) = ∞ X k=−∞ ckej2πfcht with |ck| = ( 0 if k is even 2 πk if k is odd (1.44) In the frequency domain, its eect as modulating signal is to shift the input signal spectrum Vin(f ) around integer multiples of fch, while multiplying

them by the proper coecient ck, thus the modulated signal becomes

ViA(f ) = ∞

X

k=−∞

ckVin(f − kfch) (1.45)

The amplier takes this signal as input and processes it by multiplying it by its gain A. This, however, only happens within the amplier's bandwidth Ba,

while outside this interval the signal is suppressed. Then, the demodulator brings the signal back into baseband while multiplying the replicas by the corresponding c−k = c∗_k. Lastly, the LPF isolates the useful signal while

eliminating the high frequency components. As a result, the output signal is Vout(f ) = Vin(f )A

N

X

k=−N

||ck||2 = αAVin(f ) (1.46)

In this expression, the summation does not consider innite values of har-monics k, since that would happen only if the amplier's bandwidth was innite. Instead, since Ba is nite, only a number N equal to _fBa

ch of

har-monics would still be present after being processed by the amplier. As a consequence, the factor α, that is the result of the summation, is not equal to 1, that is the square wave's power. Instead, its value will be a little smaller that 1, since a part of the power, the one corresponding to the harmonics being eliminated, can not be recovered into baseband and thus considered. The net result is a slight decrease of the amplier's gain, as the eective re-duction is not huge: since ckis inversely proportional to k, higher harmonics'

contribution is rather small.

The aforementioned problem would not exist if, instead of square waves, sine waves were employed in this technique, since only a single replica would be present (in the positive interval of frequencies) and brought back to baseband entirely. However, implementing an analog multiplier is not an easy task, since it would add its own noise and oset to the input signal, degrading the system's performance excessively. Instead, multiplication by a square wave can be implemented with ease: considering a fully dierential system, it is sucient to use four switches controlled by two opposite clock signals as shown in gure 1.17. They can be implemented by digital MOSFETs and

(39)

can be designed to introduce minimal level of noise and oset. The net result is that during one phase, the terminals are normally connected, that is the signal is multiplied by 1. In the second one, instead, they are inverted, and that corresponds to multiplying by -1.

Figure 1.17: Chopper stabilization employing switches

Compared to signal, noise and oset are processed in a dierent way. The important element is that they are multiplied by the square wave only once, thus only modulation takes place and not demodulation. Let's consider their power spectral density, shown in picture 1.18. The top gure shows it at the amplier's output, thus the noise's PSD is multiplied by A2_{. The bottom}

picture, shows the numerous replicas that are created after modulation, each one centred around kfch and multiplied by the proper coecient |ck|2.

Figure 1.18: Noise's PSD before and after chopper modulation

Since the replicas are not brought back into baseband, the LPF is able to lter all the noise and oset that were, originally, at low frequencies. Indeed, after modulation and supposing that fch > fk, only the broad-band component of

(40)

the replicas is located within the baseband.

To be exact, the resulting PSD of the output noise in baseband is given by Sn−out= A2Sn−T

N

X

k−N

|ck|2 = αA2Sn−T (1.47)

Than, the RTI noise PSD is

Sn−ef f =

Sn−out

(αA)2 =

Sn−T

αA (1.48)

which is derived considering that the eective gain is actually αA.

This time the eect of the nite bandwidth Ba causes the RTI noise to

in-crease, since α is not equal to one (as in the ideal case) but it has a smaller value. Once again, since α is very close to one, it is generally neglected and the RTI noise is assumed to be equal to Sn−T

A great advantage of chopper stabilization, compared to auto-zero and cor-related double sampling, is that it is a continuous time operation, thus no sampling is required. As a direct consequence, it does not suer from noise foldover like the other two techniques. However, CS also comes with its own drawbacks: rst of all the amplier's gain can not be too high. Even in the absence of an input signal, noise would still be present and processed by the amplier. Its output is then chopped by the modulator. In particular, the amplied oset, Avio, becomes a square wave called chopper ripple or oset

ripple. It is characterized by the same frequency as the modulator, fch, and

an amplitude of ±Avio. Even though the LPF would eciently suppress

this noise component, great care must be placed anyway: like in the case of output oset storage AZ, if gain is too high, it would cause the amplier's output to saturate. This would limit the available output swing, and the amplier could have diculty in providing the amplied input signal. Another important issue with chopper stabilization is residual oset. It is caused by either a non-perfect square wave, or charge injection.

Let us consider the rst eect. If m(t) is not a perfect square wave with the ideal duty cycle 50%, even though this would not aect the input signal processing, it would produce an output chopper ripple whose average is not null. This means that there is an additional DC noise component, that will not be suppressed by the LPF and will remain in the overall system's output. To be exact, its expression is

< AVio >=

AVio(δ + )Tch− AVio(δ − )Tch

Tch

(41)

where the ideal value of duty cycle, δ = 0.5, is corrected by summing an error, ±.

Thus, m(t)'s duty cycle must be as precise as possible. One method to obtain it is to rst produce a wave whose frequency is two times the expected value, 2fch, but with no strict requirement on duty cycle. Then, this signal is fed

to a digital divider, like a T-Flip Flop, resulting in a square wave with both exact duty cycle and frequency.

The second phenomenon that causes residual oset is the charge injection that the input modulator switches suer from. Every time they commute, they inject a certain charge ∆Q into the input capacitance of the amplier. Thus, a spike with amplitude Vinj = ∆Q_C_in is created and discharged

exponen-tially.

Figure 1.19: Spikes caused charge injection and residual oset

Figure 1.19 depicts the eect being discussed. The rst plot shows the spikes being created by the input switches. The polarity is opposite during two consecutive phases since the corresponding charge being injected is opposite as well. This signal is periodic in Tch = _f1

ch. However, since m(t) has the

same frequency, the demodulated spikes are all positive, as shown in the last plot. This signal does not have a null mean value, therefore a DC component is left within baseband and is not ltered by the LPF, hence increasing the output's oset.

The advantages of chopper stabilization make it a very popular choice when decreasing noise and oset. However, its drawbacks discussed here must be

(42)

taken into account and dealt with. Dierent solutions have been developed to eciently reject oset ripple, and a discussion is presented in [2].

Here, only strategies specically designed towards CFIA, that is the archi-tecture being considered in this thesis, will be briey discussed. They can be divided into two categories: static oset reduction and dynamic oset reduction.

Static Oset Reduction

This method is the most straightforward: it simply integrates a low-pass lter in the system that should be able to reject oset ripple. An external LPF is not a viable solution, since its noise and oset would degrade the circuit's performance. Thus, strategies to embed it into the CFIA architecture have been developed. One solution is presented in [8] and shown in picture 1.20

Figure 1.20: Embedded LPF in a CFIA

Here, a three-staged amplier has been studied. The rst two are a regular CFIA that has been chopped to deal with noise and oset. The third stage, instead, is a Miller integrator. The capacitors placed in the nested-Miller compensation feedback help ltering out ripple present at the chopping fre-quency, as well as improving stability.

Beside this strategy, another solution to integrate a LPF is the state variable lter. This method is considered in this thesis, thus it will be discussed in section 2.1.

(43)

Dynamic Oset Reduction

An example of this technique is shown in [9] and is shown in picture 1.21. Here, the output ripple is still ltered, thanks to the main Miller compen-sation capacitor C2. However, to reject it more eciently, an additional

mechanism is integrated: a continuous-time Ripple Reduction Loop (RRL).

Figure 1.21: Block diagram of a CFIA with RRL

A sense capacitor, C4, is able to transform the output ripple into a

propor-tional AC current. This is demodulated by CH6 and converted into a DC

current that is then integrated. The result is a DC compensation voltage proportional to the output ripple's amplitude. Lastly, it is fed back into the outputs of the two input transconductors, Gm3 and Gm4, by injecting a

(44)

Chapter 2 Reference design

In order to achieve the characteristic described previously in section 1.1, this thesis implements a CFIA architecture, with the addition of various strate-gies to improve its performance. This work is based on a previous study, that will now be described before delving into the specic improvements made in this thesis.

Figure 2.1: Reference design's schematic

The reference design is shown in picture 2.1 and it is described in detail in [4]. Compared to the basic CFIA previously discussed in 1.2.6, some changes were made, that will now be presented.

(45)

2.1 Chopper stabilization and state variable

l-ter

First of all, in order to reduce noise and oset's eect, chopper stabilization was implemented. This technique is particularly suitable with this topology, but as a direct consequence, a low-pass lter has to be included. Instead of the strategies mentioned in 1.4.3, here another static oset reduction tech-nique was implemented, that is the State Variable Filter (SVF). This allows to embed a CFIA architecture with a ltering behaviour, without harming the frequency response within the desired bandwidth. At the same time, it is able to suppress unwanted disturbances, including the oset ripple caused by chopper stabilization.

State variable lter consists in cascading one or more integrators, while also connecting them through a feedback network. By choosing their number and each one's parameters, the frequency response of the overall output can be adjusted to the desired one. In this case, a two-stage architecture was chosen, with the addition of a feedback block called β. Thus, its block schematic can be represented as in picture 2.2.

Figure 2.2: Block digram of a two-stage SVF

Each block implements an ideal integrator, whose transfer function in given by

Hint−i(s) =

ω0i

s (2.1)

where ω0i is the unity-gain pulsation, that is the one corresponding to a gain

of 0 dB. In this notation, i denotes the i-th integrator.

In this conguration, the overall Signal Transfer Function (STF) between vin