 m CMOS Technology with Sensor Level Analog Processing A Novel Monolithic Active Pixel detector in 0.13

Pixel 2005 Pixel 2005 International Workshop on Semiconductor Pixel International Workshop on Semiconductor Pixel

Detectors for Particles and Imaging Detectors for Particles and Imaging

Bonn, September 5-8 2005 Bonn, September 5-8 2005

G. Rizzo^a, S. Bettarini^a, G. Calderini^a, R. Cenci^a, F. Forti^a, M.A.

Giorgi^a, F. Morsani^a, V. Speziali^b,d, L. Ratti^b,d, M. Manghisoni^c,d V. Re^c,d,^, G. Traversi^c,d, L. Bosisio^e

aINFN Pisa and Università degli Studi di Pisa, ^bUniversità degli Studi di Pavia,

cUniversità degli Studi di Bergamo, ^dINFN Pavia,

eINFN Trieste and Università degli Studi di Trieste

A Novel Monolithic Active Pixel detector in 0.13  m CMOS Technology with Sensor

Level Analog Processing

Outline

• CMOS MAPS for tracking in future high energy physics experiments

• Characteristics of our MAPS in triple well with signal processing at pixel level

• Front end electronics characterization

• Response of the sensor to

– Infrared laser

– Ionizing radiation (

Fe,

Sr )

• Conclusions

• Developed for imaging applications, recently proven to be suitable as tracking devices for ionizing particles

• Several characteristics make them very appealing for such application

– same substrate for detector-readout  less material in the detection region – radiation hardness

– high functional density and versatility

– low power consumption and fabrication costs

CMOS MAPS

• Electrons generated by the

impinging particle are reflected by the potential barriers due to

doping differences and collected by thermal diffusion by the n- well/p-epitaxial diode

– Charge-to-voltage conversion provided by sensor capacitance – Extremely simple in-pixel

readout configuration (3 NMOSFETs)

electronics &

interconnects

epitaxial layer (~ 10 m thick)

substrate

(~ 300 m thick)

Triple well CMOS processes

This feature can be exploited in the design of CMOS pixels:

• The deep n-well can be used as the collecting electrode

• NMOS transistors can be overlaid on the collecting electrode area:

– maximise the fill factor – shield against digital noise

• A full signal processing circuit can be implemented at the pixel level

In triple-well processes a deep n-well is used to

provide N-channel MOSFETs with better insulation from digital signals

Use of the deep n-well was proposed by Turchetta et al. (2004 IEEE NSS Conference Record, N28-1) to address radiation hardness issues

Deep n-well sensor

• NMOS devices of the analog section built in the deep n-well

• PMOS devices needed for full exploitation of CMOS technology functionalities

• Ratio of the deep n-well area to the area covered by all the n-type wells should be kept as large as possible (never less than 0.85 in the

prototype test structures)

• Charge preamplifier used for Q-V conversion:

-> Gain is independent of the sensor capacitance -> readout electrode doesn’t need to be extremely small

Readout scheme compatible with existent architectures for data sparsification at the level of the elementary cell

Standard processing chain for capacitive detector implemented at pixel level

Pixel level processor

• High sensitivity charge preamplifier with

continuous reset

• Input device (W/L=3/0.35) optimized for a 100 fF

detector capacitance and operated at a drain

current of about 1 A

• Sensor actual capacitance is higher than initially expected: readout performance greatly affected. Room for

improvement in next chip submission

• RC-CR shaper with programmable peaking time (0.5, 1 and 2 s)

• A threshold discriminator is used to drive a NOR latch featuring an external reset

• Power consumption: 10 W

Device Simulation (ISE-TCAD)

• Detailed physical simulations performed using ISE-TCAD software to:

– understand the charge collection mechanism and its time properties

– study influence of neighbouring pixel and n-wells – optimize sensor design (needs 3D simulation, in

progress)

• Preliminary results:

– Collected charge ~ 1500 e-

• assuming pepi thickness  15 m: likely to be true.

• Charge collection drops rapidly out of deep nwell area

– Collection time: ~50 ns

Uncertainties about process:

Test structure chip realized to measure some

process parameters -> a crucial input for simulation

Single devices

channel 4 - pixel with large (2670 m²) collecting electrode

area channel 3- pixel with

medium (1730 m²) collecting electrode

area

channel 6 - pixel with small (830 m²)

collecting electrode area

channel 5 - pixel with input pad for

charge injection (830 m² collecting

electrode area)

channel 1 - pixel with input pad for

charge injection

channel 2 - pixel with input pad for

charge injection (100 fF detector

simulating capacitance)

0.13 m CMOS HCMOS9GP by STMicroelectronics: epitaxial, triple well process (available through CMP, Circuits Multi-Projets)

Test Chip Layout

channel 1-2-5 have integrated injection capacitance for readout electronics characterization

NMOS

analog section (including input

device) +

collecting electrode

PMOS

analog section

PMOS digital section

NMOS digital section

Shaper input MiM cap.

Shaper feedbac

k MiM cap.

N-WELL

DEEP N-WELL

N-WELL

~40 m

~40 m

Pixel Cell Layout

channel 5

Front-end Electronics Characterization

• Shaper response to a 560 e^- input charge at the three different peaking times

• About 15% variation in peak amplitude moving from the shortest to the longest peaking time

• The latch preserves the signal until it has been retrieved

• External reset signal sent to the latch returns it to the initial condition

-0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01

0 4 8 12 16

t_p=0.5 s t_p=1 s t_p=2 s

Shaper output [V]

t [s]

Channel 1

0 0.5 1 1.5

Latch output [V]

-0.08 -0.06 -0.04 -0.02 0 0.02

Shaper output [V]

tP= 1 s Channel 2

-0.5 0 0.5 1 1.5

Reset [V]

threshold

0

1

0 20 40 60 80 100 120

0 200 400 600 800 1000 1200

Measurements PLS

V peak [mV]

Qin [e-]

448 mV/fC

431 mV/fC

Channel 5 tP=1 s

Gain & Noise Measurements

• Measured gain agrees within 10%

with the post layout simulation results (PLS).

0 50 100 150 200 250

0 50 100 150 200 250 300 350

ENC [e- rms]

CT [fF]

t_P=1 s

ENC = 11e^- + 425e^-/pF

Channel 2 Channel 5

Channel 1

• Equivalent Noise Charge is linear with CT=CD+CF+Cinj+Cin (^CD=detector capacitance, CF=preamplifier feedback capacitance,

Cin=preamplifier input capacitance)

• Equivalent Noise Charge model:

f 2 p

W 1

T A A

t S A C

ENC 

• Charge sensitivity and Equivalent Noise Charge measured in the three channels with integrated injection capacitance Cinj

S_W=series white noise spectral density A_f=1/f noise power coefficient

A₁, A₂=shaping coefficients

dominant contribution

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02

-5 0 5 10 15 20 25

Channel 3 Channel 4 Channel 6

shaper output [V]

t [s]

tP=1 s

Response to infrared laser

• Infrared laser used to emulate charge released by particle

 =1060 nm  absorption coefficient=10 cm^-1 in Si  pixel can be back illuminated

• Total charge released equivalent to ~ 6 MIPs

• Charge released in a broad region under the sensor: fraction of the charge collected by pixel depends on the laser spot intensity profile (not well known yet)

• Largest charge collected in the largest pixel.

• Charge does not scale linearly  laser spot larger than the pixel area and with non uniform profile

• Results roughly compatible with a gaussian laser spot profile of about 50 m …

Threshold set cuts this region

Peak value of the shaper output:

• blue - ⁵⁵Fe source (5.9 keV)

• green - No source (same acquisition time)

Response to

Fe X-ray

• Soft X-ray from

Fe source used to calibrate pixel noise and gain in channels with no injection capacitance

1640 2200 3000 (e-)

• 5.9 keV line corresponds to about 1640 e/h pairs:

• with charge entirely collected clear peak @ 105 mV -> gain=400 mV/fC

• below 100 mV evident excess w.r.t. noise events <- due to charge only partially collected by the single pixel

=105 mV

=12 mV

Charge only partially collected by single pixel

Charge entirely collected

Calibration with

Fe

Calibration with ⁵⁵Fe source in good

agreement with results obtained with the injection capacitance and within ~ 15%

from PLS (ENC=150 e-, gain=430 mV/fC expected)

Signal expected from M.I.P is about 1500 e- (sensor simulation with pepi thickness  15 m, assuming MIP most probable signal 80 e-/m)

S/N expected = 12

Pixel noise distribution

mean=8mV

Using gain measured with

Fe

Pixel noise 8 mV ENC=125 e-

Response to

Sr electrons

Acquisition triggered by coincidence scintillator & pixel signal above

threshold (set @ ~0.5 MIP)

Setup not easy as it seems: you need to fire a single pixel ~30x30 m² !

Response to M.I.P from

Sr beta source used to measure S/N ratio

Pixel

90Sr beta source Scintillator

Si chip 300 um

e-

Y e

Sr

90 38

 

Y   e

Zr

1.00 10.00

0.0 0.5 1.0 1.5 2.0 2.5

Ek MeV

dE/dx Mev/g/cm2

Series1

Sr-90 beta spectrum

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

0 0.5 1 1.5 2 2.5

Ek (MeV)

dN/dE

Sr90 Y90

45% are ~ M.I.P:

Landau peak

15% die in Si

40% release more than a M.I.P, they deform Landau shape or saturate the shaper

Response to

Sr electrons

Landau peak 80 mV

1250 2200 3000 (e-)

saturation due to low energy particle.

• Landau peak clearly visible

@80 mV

• Using M.I.P signal from ⁹⁰Sr and average pixel noise

S/N=10

• Using gain measured with ⁵⁵Fe, M.I.P most probable energy loss corresponds to about 1250 e-

• Fair agreement with sensor simulation:  1500 e- expected for pepi layer thickness  15

m. Hint on the process secrets!

Peak value of the shaper output:

• blue - ⁹⁰Sr beta source

• green - No source

Threshold set cuts this region

First chip successfully tested

• Results obtained with infrared laser and radiative source demonstrate the full functionality of the pixel:

sensor+readout electronics

• Good agreement observed among various results:

– Readout calibration with injection capacitance – Results from Post Layout Simulation

– Response to ⁵⁵Fe and ⁹⁰Sr source

– Signal expected from sensor simulation

• Present S/N=10 is not outstanding but will be improved by about a factor 3 in the next chip (submitted end of August 05)

– Input element: W/L=19/0.25, optimized for a more realistic detector capacitance of about 320 fF. Noise expected from PLS ENC ~ 50 e- (actual channel ~ 150 e-)

Conclusions

• New CMOS MAPS detector with analog processing at pixel level fabricated in 0.13 m triple well process:

– Part of the readout electronics overlaid on the collecting

electrode (deep n-well) to allow more complex processing at the pixel level

• First test chip with single pixels successfully tested with infrared laser and radiative source

• Already in production a pixel matrix with sequential readout and improved noise performance: S/N expected ~ 30

• Final goal is to develop a matrix with sparsified readout suitable to be used in a trigger system based on associative memories

• This project will be pursued with the new SLIM (Silicon

detectors with Low Interaction with Material) Collaboration

Backup slides

Post layout simulations (PLS) within 10% of measured gain

Change in the charge sensitivity probably due to loop gain

degradation in the charge preamplifier (high detector capacitance, small forward gain)

0 20 40 60 80 100 120

0 200 400 600 800 1000 1200

Measurements PLS

V peak [mV]

Qin [e-]

tP=1 s

588 mV/fC

533 mV/fC

Channel 1

0 20 40 60 80 100 120

0 200 400 600 800 1000 1200

Measurements PLS

V peak [mV]

Qin [e-]

448 mV/fC

431 mV/fC

Channel 5 tP=1 s

0 20 40 60 80 100 120

0 200 400 600 800 1000 1200

Measurements PLS

V peak [mV]

Qin [e-]

550 mV/fC

520 mV/fC

Channel 2 tP=1 s

Charge Sensitivity

Details on test channels

Channel Aniso+nwell collecting electAtot nwell Ratio Atot pixel Fill factor Noise Power

electrode/totnwell expectedconsumption uW

3 1.73E+03 1.87E+03 9.25E-01 2256 7.67E-01 10

4 2.67E+03 2.81E+03 9.50E-01 3504 7.62E-01 10

6 8.30E+02 9.70E+02 8.56E-01 1764 4.71E-01 150 10 new submission 2.00E+03 2.14E+03 9.35E-01 2250 8.89E-01 50 60

Response to infrared laser

Channel no. C_D [fF] Charge sensitivity

[mV/fC]

Collected charge

[e^-]

3 660 360 1250

4 1280 330 1500

6 270 430 880

Largest charge collected in the largest pixel

Charge does not scale linearly with the pixel area  laser spot larger than the pixel area and with non uniform profile

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02

-5 0 5 10 15 20 25

Channel 3 Channel 4 Channel 6

shaper output [V]

t [s]

tP=1 s

Results roughly compatible with a gaussian laser spot profile of about 50 m …

Still p type epitaxial layer thickness not known!

MAPS sensor & test

structure chip

currently under test

Capacitance niso_pepi vs Vbias

0 0.5 1 1.5 2 2.5 3 3.5

0 5 10 15

C (pF)

0 0.2 0.4 0.6 0.8 1 1.2

1/C^2 (pF-2)

C 1/c^2 Capacitance niso_pwell vs Vbias

0 2 4 6 8 10 12 14 16

0 5 10 15

Vbias (V)

C (pF)

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045

1/C^2 (pF-2)

C 1/c2

pepi pepi

niso

3

1017

5 . 1 9 .

0   ^

 cm

N_pwell

3

1015

5 . 1

1  ^

 cm

N_pepi

Diode_niso_pepi

Pwell max depletion 0.4 um

pepi max depletion 3 um p+ p+

p+ n+ n+

Breakdown @ 10V !

Test structure test under way!