This is the current definition of the so called Moore’s Law and most experts expect it to hold for at least another decade.

Introduction

Semiconductor electronics is a very fast developing field and its history, since its birth marked by the invention of the bipolar transistor in 1948 by Bardeen, Brattain and Shockley at the Bell Laboratories[1,2], is full of stunning technical improvements that have allowed to fabricate devices with progressively higher performances and smaller dimensions.

There are two phenomena that we should consider: on one hand, the number of components per chip is continously increasing while the device dimensions are shrinking. In 1965 Gordon Moore, the then director of the Fairchild Research Laboratories, observed that the number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented, in 1958. He made a powerful prediction[3]: the number of components per unit area would double approximately every 18 months.

This is the current definition of the so called Moore’s Law and most experts expect it to hold for at least another decade.

On the other hand, in the past 30 years improvements in lithography

techniques (the minimum feature size for the CMOS technology has shrunk

from 2 µm in the 1980’s to less than 100 nm these days) and, most of all, in

molecular beam epitaxial growth have led to the fabrication of mesoscopic

systems. Indeed, molecular beam epitaxy is responsible for the availability of high-quality multilayer heterostructures which have made possible to obtain, for example, two dimensional electron gases and delta doping.

Scaling–down of CMOS technology

Actually, the incredible progress of microelectronics in the last decades has been possible because of the scaling–down characteristics of the CMOS tech- nology, which are extremely good, because the smaller are the dimensions W and L of the MOSFETs, the better are the performances and the lower is the cost per transistor[4].

On the hypothesis of constant–field scaling, if W and L are divided by a factor K > 1, the power–delay product is reduced by K

and the power dissipation per unit area is constant, while the number of transistors is proportional to K

.

Unfortunately, in practice we do not assist at a constant–field scaling,

because reducing the power supply V

by the same factor K is not conve-

nient, from a signal to noise ratio point of view: the electric field E in the

device is then increased by a factor α > 1. As a consequence, the power con-

sumption per unit area is proportional to α

and there are problems related

to heat dissipation, which is indeed a limiting factor to the integration of a

greater number of components on a small area.

As a result of this scaling–down process, at present it is possible to fab- ricate MOSFETs with L less than 100 nm and an oxide layer a few nanome- ters thick, and, according to the the International Technology Roadmap for Semiconductors (ITRS), the 50-nm node will be reached in 2010. This trend cannot continue forever even if technology would allow it, since we are fast ap- proaching the atomic scale (the atomic radius is about 1 ˚ A, which is 0.1 nm) and the channel length is getting closer to the Fermi wavelength, λ

, which in semiconductors is some tens of nanometers.

This implies that other mechanisms, such as the quantum behavior of electrons, begin to influence electronic transport in the devices, and tradi- tional transistor structures cannot operate properly any longer, since they work in the classical diffusive regime. Thus, while the traditional approaches to CMOS scaling are being pushed to their limits, new devices, materials, and designs are being developed.

Mesoscopic systems

The word mesoscopic refers to the fact that these kinds of systems stand be-

tween the microscopic and the macroscopic world, because their dimensions

are neither atomic nor large enough[5]. This leads to the fact that in such

small conductors electronic transport is no longer diffusive but ballistic be- cause electrons do not experiment scattering events. Moreover, usually the dimensions of mesoscopic conductors make them quantum systems.

Hence the necessity and opportunity to develop new kinds of amplifi- cating systems, based on other principles than those of classical physics, to move further in the process of device shrinking: the aim of this thesis is to demonstrate that is possible to obtain a transistor effect in a nanostructure based on quantum point contacts (QPC), that is to prove that it is possible to obtain a voltage gain greater than 1.

We have designed and fabricated this QPC based transistor and charac- terized it at low temperatures.

Quantum point contacts

Quantum point contacts are examples of mesoscopic systems: they are basic nanostructures for investigating one dimensional conduction. Since it has been possible to realize such conductors about 20 years ago, they have been widely employed in the study of electronic transport for their interesting properties.

A quantum point contact is a sort of constriction in a two–dimensional

electron gas (2DEG) of a high mobility GaAs–AlGaAs heterostructure, it is

wide some tens or hundreds of nanometers and the constriction is due to lat- eral confinement, which is obtained by means of metallic split gates placed upon the surface of the heterostructure: when a negative bias voltage V

is applied, the electron gas underneath the gate is electrostatically depleted (provided that V

is greater than a certain threshold, depending on the di- mension of the constriction). The result is a 1D conductor in the small region of the point contact.

When specific geometrical conditions are satisfied, electronic transport is in the quantum ballistic regime: this occurs when the width of the channel is comparable to the Fermi wavelength and when dimensions of the channel are much less than the mean free path in the sample (and assuming that the phase relaxation length is much greater than the channel dimensions)[4].

Quantum point contacts have been helpful in discovering novel quantum

properties of electrons. One of these is the quantization of the conductance

G of this small conductor in discrete steps of 2e

/h (e is the electron charge,

h is the Planck constant), corresponding to 77.48 µS. This phenomenon was

discovered in 1988, independently by two groups[6,7], and takes place because

in a 1D conductor the product between the density of states and the group

velocity, which gives the current I through the conductor, does not depend

on energy.

Variations in V

make the channel width W change: when W is in- creased by λ

/2 another 1D subband, which is the analogous of a propagating channel in a waveguide, participates to conduction and G is increased by a quantity 2e

/h, because every single 1D subband gives the same contribution.

The transistor effect

The conductance quantization phenomenon occurs when the drain bias V

is very small, a few millivolts, that is in the linear regime. In this case, the drain electrochemical potential µ

and the source electrochemical potential µ

lie in the same 1D subband.

However, to obtain the transistor effect it is necessary to operate in the non-linear regime, as it happens in a traditional field effect transistor. Since the expression of the voltage gain A

is the transconductance g

over the output conductance g

, we must work in a region of the characteristics where this ratio is as large as possible.

A high value for g

can be accomplished by means of a good heterostruc- ture, with the 2DEG very close to the surface of the wafer. Reducing g

means that the variations of I

depend weakly from the variations of drain

bias, or in other words, saturation occurs. This happens when V

is greater

than in the case of the linear regime and about some tens of millivolts. This

also implies that, since Ids is some microamperes, the power consumption will be extremely low, a few nanowatts.

Nevertheless, in a ballistic quantum point contact, saturation is caused by a mechanism different from that active in a FET: here saturation occurs when the number of 1D subbands occupied respectively by the drain and the source electrochemical potential is different.

Fabrication of the devices and measurements

The whole process for the fabrication of the device has required several months, in which I have been trained to work in a clean room, using all the equipment we needed (electron beam lithography system, processes of III-V compound semiconductors, scanning electron microscope etc.).

After processing, we have electrically characterized part of the produced devices at 4.2 K in liquid helium. We have examined the quantization of the conductance as a function of the gate geometry and the voltage gain as a function of the drain and gate polarization.

At present, to think that quantum transistors will be able to replace

traditional transistors is not realistic, because they work at very low temper-

atures, so that it is impossible to use them for commercial purposes (which

require room temperature operation), but they could represent a smart al-

ternative to conventional transistors at least for specific applications such as

low temperature sensoring and spatial applications, where ultra-low noise is required.

In this thesis I am presenting a description of the work we have done, up to the time when I left the laboratory, in all its aspects: design, fabrication and measurements. Chapter 1 provides a brief outline of the subject, with the theoretical basis on which the device has been designed. Chapter 2 is about the fabrication of the device. In Chapter 3 results obtained from measurements are reported. Finally, conclusions on our work are presented.

Every aspect of this work has been carried on under the guidance of Dr. Yong Jin, permanent researcher, and in collaboration with Emile Gr´emion, Ph. D. student, both of them from the Laboratoire de Photonique et Nanostructure (LPN) of the CNRS, Marcoussis, France, where the whole project has been developed over a 6 month period. They are going to con- tinue working on this project in the next future, with the aim of perfecting the device and characterizing it from the point of view of noise behavior.

BIBLIOGRAPHY

[1] J. Bardeen, W.H. Brattain, The transistor, a semi-conductor triode,

Phys. Rev. 74, p. 230-231, (1948).

[2] W. Shockley, The theory of p-n junctions in semiconductors and p-n junction transistors, Bell Syst. Tech. J. 28, p. 435-489, (1949).

[3] G.E. Moore, Cramming more components onto integrated circuits, Elec- tronics 38, p. 114 (1965).

[4] M. Macucci, Appunti di nanolettronica, A.A. 2003–04.

[5] S. Datta, Electronic transport in mesoscopic systems, Cambridge Uni- versity Press (1995).

[6] B.J. van Wees, H. van Houten, C.W.J. Beenakker, J.C Williamson, L.P.

Kouwenhoven, D. van der Marel, C.T. Foxon, Quantized conductance of point contacts in a two–dimensional electron gas, Phys. Rev. Lett. 60, 9, p. 848 (1988).

[7] D.A. Wharam, T.J. Thornton, R. Newbury, M. Pepper, H. Ahmed,

J.E.F. Frost, D.G. Hasko, D.C. Peacock, D.A. Ritchie, G.A.C. Jones,

One–dimensional transport and the quantization of the ballistic resis-

tance, J. Phys. C 21, L209 (1988).